1; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s 2 3declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) 4define void @buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i1 %bool) { 5 ; CHECK: immarg operand has non-immediate parameter 6 ; CHECK-NEXT: i1 %bool 7 ; CHECK-NEXT: %data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 %bool, i1 false) 8 %data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 %bool, i1 false) 9 10 ; CHECK: immarg operand has non-immediate parameter 11 ; CHECK-NEXT: i1 %bool 12 ; CHECK-NEXT: %data1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 %bool) 13 %data1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 %bool) 14 ret void 15} 16 17declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) 18define void @raw_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs, i32 %arg) { 19 ; CHECK: immarg operand has non-immediate parameter 20 ; CHECK-NEXT: i32 %arg 21 ; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg) 22 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg) 23 ret void 24} 25 26declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32) 27define void @raw_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs, i32 %arg) { 28 ; CHECK: immarg operand has non-immediate parameter 29 ; CHECK-NEXT: i32 %arg 30 ; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg) 31 %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg) 32 ret void 33} 34 35declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) 36define void @struct_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) { 37 ; CHECK: immarg operand has non-immediate parameter 38 ; CHECK-NEXT: i32 %arg 39 ; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) 40 %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) 41 ret void 42} 43 44declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) 45define void @struct_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) { 46 ; CHECK: immarg operand has non-immediate parameter 47 ; CHECK-NEXT: i32 %arg 48 ; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) 49 %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) 50 ret void 51} 52 53declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) 54define void @invalid_image_sample_1d_v4f32_f32(float %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc, i32 %dmask, i1 %bool, i32 %arg) { 55 ; CHECK: immarg operand has non-immediate parameter 56 ; CHECK-NEXT: i32 %dmask 57 ; CHECK-NEXT: %data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 %dmask, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) 58 %data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 %dmask, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) 59 60 ; CHECK: immarg operand has non-immediate parameter 61 ; CHECK-NEXT: i1 %bool 62 ; CHECK-NEXT: %data1 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 %bool, i32 0, i32 0) 63 %data1 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 %bool, i32 0, i32 0) 64 65 ; CHECK: immarg operand has non-immediate parameter 66 ; CHECK-NEXT: i32 %arg 67 ; CHECK-NEXT: %data2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 %arg, i32 0) 68 %data2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 %arg, i32 0) 69 70 ; CHECK: immarg operand has non-immediate parameter 71 ; CHECK-NEXT: i32 %arg 72 ; CHECK-NEXT: %data3 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 %arg) 73 %data3 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 %arg) 74 ret void 75} 76 77declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) 78define void @exp_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) { 79 ; CHECK: immarg operand has non-immediate parameter 80 ; CHECK-NEXT: i32 %en 81 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 %en, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 true, i1 false) 82 call void @llvm.amdgcn.exp.f32(i32 0, i32 %en, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) 83 84 ; CHECK: immarg operand has non-immediate parameter 85 ; CHECK-NEXT: i32 %tgt 86 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 %tgt, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 true, i1 false) 87 call void @llvm.amdgcn.exp.f32(i32 %tgt, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) 88 89 ; CHECK: immarg operand has non-immediate parameter 90 ; CHECK-NEXT: i1 %bool 91 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 %bool, i1 false) 92 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 %bool, i1 false) 93 94 ; CHECK: immarg operand has non-immediate parameter 95 ; CHECK-NEXT: i1 %bool 96 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 false, i1 %bool) 97 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 %bool) 98 ret void 99} 100 101declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) 102 103define void @exp_compr_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) { 104 ; CHECK: immarg operand has non-immediate parameter 105 ; CHECK-NEXT: i32 %en 106 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false) 107 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false) 108 109 ; CHECK: immarg operand has non-immediate parameter 110 ; CHECK-NEXT: i32 %tgt 111 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false) 112 call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false) 113 114 ; CHECK: immarg operand has non-immediate parameter 115 ; CHECK-NEXT: i1 %bool 116 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 %bool, i1 false) 117 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 %bool, i1 false) 118 119 ; CHECK: immarg operand has non-immediate parameter 120 ; CHECK-NEXT: i1 %bool 121 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 false, i1 %bool) 122 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 false, i1 %bool) 123 ret void 124} 125 126declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32) 127 128define i64 @invalid_nonconstant_icmp_code(i32 %a, i32 %b, i32 %c) { 129 ; CHECK: immarg operand has non-immediate parameter 130 ; CHECK-NEXT: i32 %c 131 ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c) 132 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c) 133 ret i64 %result 134} 135 136declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32) 137define i64 @invalid_nonconstant_fcmp_code(float %a, float %b, i32 %c) { 138 ; CHECK: immarg operand has non-immediate parameter 139 ; CHECK-NEXT: i32 %c 140 ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c) 141 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c) 142 ret i64 %result 143} 144 145declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) 146define amdgpu_kernel void @invalid_atomic_inc(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %var, i1 %bool) { 147 ; CHECK: immarg operand has non-immediate parameter 148 ; CHECK-NEXT: i32 %var 149 ; CHECK-NEXT: %result0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 %var, i32 0, i1 false) 150 %result0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 %var, i32 0, i1 false) 151 152 ; CHECK: immarg operand has non-immediate parameter 153 ; CHECK-NEXT: i32 %var 154 ; CHECK-NEXT: %result1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 %var, i1 false) 155 %result1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 %var, i1 false) 156 157 ; CHECK: immarg operand has non-immediate parameter 158 ; CHECK-NEXT: i1 %bool 159 ; CHECK-NEXT: %result2 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 %bool) 160 %result2 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 %bool) 161 ret void 162} 163 164declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) 165define amdgpu_kernel void @invalid_atomic_dec(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %var, i1 %bool) { 166 ; CHECK: immarg operand has non-immediate parameter 167 ; CHECK-NEXT: i32 %var 168 ; CHECK-NEXT: %result0 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 %var, i32 0, i1 false) 169 %result0 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 %var, i32 0, i1 false) 170 171 ; CHECK: immarg operand has non-immediate parameter 172 ; CHECK-NEXT: i32 %var 173 ; CHECK-NEXT: %result1 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 %var, i1 false) 174 %result1 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 %var, i1 false) 175 176 ; CHECK: immarg operand has non-immediate parameter 177 ; CHECK-NEXT: i1 %bool 178 ; CHECK-NEXT: %result2 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 %bool) 179 %result2 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 %bool) 180 ret void 181} 182 183declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) 184define amdgpu_kernel void @test_div_scale_f32_val_undef_undef(float addrspace(1)* %out) { 185 ; CHECK: immarg operand has non-immediate parameter 186 ; CHECK: i1 undef 187 ; CHECK: %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.000000e+00, float undef, i1 undef) 188 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 undef) 189 %result0 = extractvalue { float, i1 } %result, 0 190 store float %result0, float addrspace(1)* %out, align 4 191 ret void 192} 193 194declare void @llvm.amdgcn.init.exec(i64) 195define amdgpu_ps void @init_exec(i64 %var) { 196 ; CHECK: immarg operand has non-immediate parameter 197 ; CHECK-NEXT: i64 %var 198 ; CHECK-NEXT: call void @llvm.amdgcn.init.exec(i64 %var) 199 call void @llvm.amdgcn.init.exec(i64 %var) 200 ret void 201} 202 203declare i32 @llvm.amdgcn.s.sendmsg(i32, i32) 204define void @sendmsg(i32 %arg0, i32 %arg1) { 205 ; CHECK: immarg operand has non-immediate parameter 206 ; CHECK-NEXT: i32 %arg0 207 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.sendmsg(i32 %arg0, i32 %arg1) 208 %val = call i32 @llvm.amdgcn.s.sendmsg(i32 %arg0, i32 %arg1) 209 ret void 210} 211 212declare i32 @llvm.amdgcn.s.sendmsghalt(i32, i32) 213define void @sendmsghalt(i32 %arg0, i32 %arg1) { 214 ; CHECK: immarg operand has non-immediate parameter 215 ; CHECK-NEXT: i32 %arg0 216 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.sendmsghalt(i32 %arg0, i32 %arg1) 217 %val = call i32 @llvm.amdgcn.s.sendmsghalt(i32 %arg0, i32 %arg1) 218 ret void 219} 220 221declare i32 @llvm.amdgcn.s.waitcnt(i32) 222define void @waitcnt(i32 %arg0) { 223 ; CHECK: immarg operand has non-immediate parameter 224 ; CHECK-NEXT: i32 %arg0 225 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.waitcnt(i32 %arg0) 226 %val = call i32 @llvm.amdgcn.s.waitcnt(i32 %arg0) 227 ret void 228} 229 230declare i32 @llvm.amdgcn.s.getreg(i32) 231define void @getreg(i32 %arg0, i32 %arg1) { 232 ; CHECK: immarg operand has non-immediate parameter 233 ; CHECK-NEXT: i32 %arg0 234 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.getreg(i32 %arg0) 235 %val = call i32 @llvm.amdgcn.s.getreg(i32 %arg0) 236 ret void 237} 238 239declare i32 @llvm.amdgcn.s.sleep(i32) 240define void @sleep(i32 %arg0, i32 %arg1) { 241 ; CHECK: immarg operand has non-immediate parameter 242 ; CHECK-NEXT: i32 %arg0 243 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.sleep(i32 %arg0) 244 %val = call i32 @llvm.amdgcn.s.sleep(i32 %arg0) 245 ret void 246} 247 248declare i32 @llvm.amdgcn.s.incperflevel(i32) 249define void @incperflevel(i32 %arg0, i32 %arg1) { 250 ; CHECK: immarg operand has non-immediate parameter 251 ; CHECK-NEXT: i32 %arg0 252 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.incperflevel(i32 %arg0) 253 %val = call i32 @llvm.amdgcn.s.incperflevel(i32 %arg0) 254 ret void 255} 256 257declare i32 @llvm.amdgcn.s.decperflevel(i32) 258define void @decperflevel(i32 %arg0, i32 %arg1) { 259 ; CHECK: immarg operand has non-immediate parameter 260 ; CHECK-NEXT: i32 %arg0 261 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.decperflevel(i32 %arg0) 262 %val = call i32 @llvm.amdgcn.s.decperflevel(i32 %arg0) 263 ret void 264} 265 266declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) 267define void @ds_swizzle(i32 %arg0, i32 %arg1) { 268 ; CHECK: immarg operand has non-immediate parameter 269 ; CHECK-NEXT: i32 %arg1 270 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.ds.swizzle(i32 %arg0, i32 %arg1) 271 %val = call i32 @llvm.amdgcn.ds.swizzle(i32 %arg0, i32 %arg1) 272 ret void 273} 274 275declare i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1) 276define amdgpu_kernel void @ds_ordered_add(i32 addrspace(2)* %gds, i32 addrspace(1)* %out, i32 %var, i1 %bool) { 277 ; CHECK: immarg operand has non-immediate parameter 278 ; CHECK-NEXT: i32 %var 279 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true) 280 %val0 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true) 281 282 ; CHECK: immarg operand has non-immediate parameter 283 ; CHECK-NEXT: i32 %var 284 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true) 285 %val1 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true) 286 287 ; CHECK: immarg operand has non-immediate parameter 288 ; CHECK-NEXT: i1 %bool 289 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true) 290 %val2 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true) 291 292 ; CHECK: immarg operand has non-immediate parameter 293 ; CHECK-NEXT: i32 %var 294 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true) 295 %val3 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true) 296 297 ; CHECK: immarg operand has non-immediate parameter 298 ; CHECK-NEXT: i1 %bool 299 ; CHECK-NEXT: %val4 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true) 300 %val4 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true) 301 302 ; CHECK: immarg operand has non-immediate parameter 303 ; CHECK-NEXT: i1 %bool 304 ; CHECK-NEXT: %val5 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool) 305 %val5 = call i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool) 306 ret void 307} 308 309declare i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1) 310define amdgpu_kernel void @ds_ordered_swap(i32 addrspace(2)* %gds, i32 addrspace(1)* %out, i32 %var, i1 %bool) { 311 ; CHECK: immarg operand has non-immediate parameter 312 ; CHECK-NEXT: i32 %var 313 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true) 314 %val0 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true) 315 316 ; CHECK: immarg operand has non-immediate parameter 317 ; CHECK-NEXT: i32 %var 318 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true) 319 %val1 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true) 320 321 ; CHECK: immarg operand has non-immediate parameter 322 ; CHECK-NEXT: i1 %bool 323 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true) 324 %val2 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true) 325 326 ; CHECK: immarg operand has non-immediate parameter 327 ; CHECK-NEXT: i32 %var 328 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true) 329 %val3 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true) 330 331 ; CHECK: immarg operand has non-immediate parameter 332 ; CHECK-NEXT: i1 %bool 333 ; CHECK-NEXT: %val4 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true) 334 %val4 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true) 335 336 ; CHECK: immarg operand has non-immediate parameter 337 ; CHECK-NEXT: i1 %bool 338 ; CHECK-NEXT: %val5 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool) 339 %val5 = call i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool) 340 ret void 341} 342 343declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) 344define amdgpu_kernel void @mov_dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %var, i1 %bool) { 345 ; CHECK: immarg operand has non-immediate parameter 346 ; CHECK-NEXT: i32 %var 347 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 %var, i32 1, i32 1, i1 true) 348 %val0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 %var, i32 1, i32 1, i1 1) 349 350 ; CHECK: immarg operand has non-immediate parameter 351 ; CHECK-NEXT: i32 %var 352 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 %var, i32 1, i1 true) 353 %val1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 %var, i32 1, i1 1) 354 355 ; CHECK: immarg operand has non-immediate parameter 356 ; CHECK-NEXT: i32 %var 357 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 %var, i1 true) 358 %val2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 %var, i1 1) 359 360 ; CHECK: immarg operand has non-immediate parameter 361 ; CHECK-NEXT: i1 %bool 362 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 1, i1 %bool) 363 %val3 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 1, i1 %bool) 364 ret void 365} 366 367declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) 368define amdgpu_kernel void @update_dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2, i32 %var, i1 %bool) { 369 ; CHECK: immarg operand has non-immediate parameter 370 ; CHECK-NEXT: i32 %var 371 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 %var, i32 1, i32 1, i1 true) 372 %val0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 %var, i32 1, i32 1, i1 1) 373 374 ; CHECK: immarg operand has non-immediate parameter 375 ; CHECK-NEXT: i32 %var 376 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 %var, i32 1, i1 true) 377 %val1 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 %var, i32 1, i1 1) 378 379 ; CHECK: immarg operand has non-immediate parameter 380 ; CHECK-NEXT: i32 %var 381 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 %var, i1 true) 382 %val2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 %var, i1 1) 383 384 ; CHECK: immarg operand has non-immediate parameter 385 ; CHECK-NEXT: i1 %bool 386 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 %bool) 387 %val3 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 %bool) 388 ret void 389} 390 391declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) 392define amdgpu_ps void @load_1d(<8 x i32> inreg %rsrc, i32 %s, i32 %var) { 393 ; CHECK: immarg operand has non-immediate parameter 394 ; CHECK-NEXT: i32 %var 395 ; CHECK-NEXT: %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 %var, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 396 %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 %var, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 397 398 ; CHECK: immarg operand has non-immediate parameter 399 ; CHECK-NEXT: i32 %var 400 ; CHECK-NEXT: %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %var, i32 0) 401 %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %var, i32 0) 402 403 ; CHECK: immarg operand has non-immediate parameter 404 ; CHECK-NEXT: i32 %var 405 ; CHECK-NEXT: %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 %var) 406 %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 %var) 407 ret void 408} 409 410declare {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32, i32, <8 x i32>, i32, i32) 411define amdgpu_ps void @load_1d_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %val) { 412 ; CHECK: immarg operand has non-immediate parameter 413 ; CHECK-NEXT: i32 %val 414 ; CHECK-NEXT: %val0 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 %val, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) 415 %val0 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 %val, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) 416 417 ; CHECK: immarg operand has non-immediate parameter 418 ; CHECK-NEXT: i32 %val 419 ; CHECK-NEXT: %val1 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 420 %val1 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 421 422 ; CHECK: immarg operand has non-immediate parameter 423 ; CHECK-NEXT: i32 %val 424 ; CHECK-NEXT: %val2 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 %val) 425 %val2 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 %val) 426 ret void 427} 428 429declare {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) 430define amdgpu_ps void @sample_1d_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 addrspace(1)* inreg %out, float %s, i32 %var, i1 %bool) { 431 ; CHECK: immarg operand has non-immediate parameter 432 ; CHECK-NEXT: i32 %var 433 ; CHECK-NEXT: %val0 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0) 434 %val0 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0) 435 436 ; CHECK: immarg operand has non-immediate parameter 437 ; CHECK-NEXT: i1 %bool 438 ; CHECK-NEXT: %val1 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 %bool, i32 1, i32 0) 439 %val1 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 %bool, i32 1, i32 0) 440 441 ; CHECK: immarg operand has non-immediate parameter 442 ; CHECK-NEXT: i32 %var 443 ; CHECK-NEXT: %val2 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 %var, i32 0) 444 %val2 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 %var, i32 0) 445 446 ; CHECK: immarg operand has non-immediate parameter 447 ; CHECK-NEXT: i32 %var 448 ; CHECK-NEXT: %val3 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 %var) 449 %val3 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 %var) 450 ret void 451} 452 453declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) 454define amdgpu_ps void @load_1d_a16(<8 x i32> inreg %rsrc, <2 x i16> %coords, i16 %s, i32 %var) { 455 ; CHECK: immarg operand has non-immediate parameter 456 ; CHECK-NEXT: i32 %var 457 ; CHECK-NEXT: %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 %var, i16 %s, <8 x i32> %rsrc, i32 0, i32 0) 458 %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 %var, i16 %s, <8 x i32> %rsrc, i32 0, i32 0) 459 460 ; CHECK: immarg operand has non-immediate parameter 461 ; CHECK-NEXT: i32 %var 462 ; CHECK-NEXT: %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 %var, i32 0) 463 %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 %var, i32 0) 464 465 ; CHECK: immarg operand has non-immediate parameter 466 ; CHECK-NEXT: i32 %var 467 ; CHECK-NEXT: %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 %var) 468 %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 %var) 469 ret void 470} 471 472declare i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32) 473define amdgpu_ps void @raw_buffer_atomic_swap(<4 x i32> inreg %rsrc, i32 %data, i32 %var) { 474 ; CHECK: immarg operand has non-immediate parameter 475 ; CHECK-NEXT: i32 %var 476 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 %var) 477 %val2 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 %var) 478 ret void 479} 480 481declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) 482define amdgpu_ps void @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %val) { 483 ; CHECK: immarg operand has non-immediate parameter 484 ; CHECK-NEXT: i32 %val 485 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 486 %val0 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 487 488 ; CHECK: immarg operand has non-immediate parameter 489 ; CHECK-NEXT: i32 %val 490 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val) 491 %val1 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val) 492 ret void 493} 494 495declare i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0 496define amdgpu_ps void @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s, i32 %val) { 497 ; CHECK: immarg operand has non-immediate parameter 498 ; CHECK-NEXT: i32 %val 499 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 500 %val0 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0) 501 502 ; CHECK: immarg operand has non-immediate parameter 503 ; CHECK-NEXT: i32 %val 504 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val) 505 %val1 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val) 506 ret void 507} 508 509declare float @llvm.amdgcn.fdot2(<2 x half>, <2 x half>, float, i1) 510define float @test_fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3) { 511 ; CHECK: immarg operand has non-immediate parameter 512 ; CHECK-NEXT: i1 %arg3 513 ; CHECK-NEXT: %val = call float @llvm.amdgcn.fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3) 514 %val = call float @llvm.amdgcn.fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3) 515 ret float %val 516} 517 518declare i32 @llvm.amdgcn.sdot2(<2 x i16>, <2 x i16>, i32, i1) 519define i32 @test_sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) { 520 ; CHECK: immarg operand has non-immediate parameter 521 ; CHECK-NEXT: i1 %arg3 522 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) 523 %val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) 524 ret i32 %val 525} 526 527declare i32 @llvm.amdgcn.udot2(<2 x i16>, <2 x i16>, i32, i1) 528define i32 @test_udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) { 529 ; CHECK: immarg operand has non-immediate parameter 530 ; CHECK-NEXT: i1 %arg3 531 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) 532 %val = call i32 @llvm.amdgcn.udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) 533 ret i32 %val 534} 535 536declare i32 @llvm.amdgcn.sdot4(i32, i32, i32, i1) 537define i32 @test_sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) { 538 ; CHECK: immarg operand has non-immediate parameter 539 ; CHECK-NEXT: i1 %arg3 540 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) 541 %val = call i32 @llvm.amdgcn.sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) 542 ret i32 %val 543} 544 545declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1) 546define i32 @test_udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) { 547 ; CHECK: immarg operand has non-immediate parameter 548 ; CHECK-NEXT: i1 %arg3 549 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) 550 %val = call i32 @llvm.amdgcn.udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) 551 ret i32 %val 552} 553 554declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) 555define i32 @test_permlane16(i32 addrspace(1)* %out, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 %arg4) { 556 ; CHECK: immarg operand has non-immediate parameter 557 ; CHECK-NEXT: i1 %arg3 558 ; CHECK-NEXT: %v1 = call i32 @llvm.amdgcn.permlane16(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false) 559 %v1 = call i32 @llvm.amdgcn.permlane16(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false) 560 561 ; CHECK: immarg operand has non-immediate parameter 562 ; CHECK-NEXT: i1 %arg4 563 ; CHECK-NEXT: call i32 @llvm.amdgcn.permlane16(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4) 564 %v2 = call i32 @llvm.amdgcn.permlane16(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4) 565 ret i32 %v2 566} 567 568declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) 569define i32 @test_permlanex16(i32 addrspace(1)* %out, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 %arg4) { 570 ; CHECK: immarg operand has non-immediate parameter 571 ; CHECK-NEXT: i1 %arg3 572 ; CHECK-NEXT: %v1 = call i32 @llvm.amdgcn.permlanex16(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false) 573 %v1 = call i32 @llvm.amdgcn.permlanex16(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false) 574 575 ; CHECK: immarg operand has non-immediate parameter 576 ; CHECK-NEXT: i1 %arg4 577 ; CHECK-NEXT: call i32 @llvm.amdgcn.permlanex16(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4) 578 %v2 = call i32 @llvm.amdgcn.permlanex16(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4) 579 ret i32 %v2 580} 581 582declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) 583define void @test_interp_p1(float %arg0, i32 %arg1, i32 %arg2, i32 %arg3) { 584 ; CHECK: immarg operand has non-immediate parameter 585 ; CHECK-NEXT: i32 %arg1 586 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 %arg1, i32 0, i32 0) 587 %val0 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 %arg1, i32 0, i32 0) 588 store volatile float %val0, float addrspace(1)* undef 589 590 ; CHECK: immarg operand has non-immediate parameter 591 ; CHECK-NEXT: i32 %arg2 592 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 0, i32 %arg2, i32 0) 593 %val1 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 0, i32 %arg2, i32 0) 594 store volatile float %val1, float addrspace(1)* undef 595 ret void 596} 597 598declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) 599define void @test_interp_p2(float %arg0, float %arg1, i32 %arg2, i32 %arg3, i32 %arg4) { 600 ; CHECK: immarg operand has non-immediate parameter 601 ; CHECK-NEXT: i32 %arg2 602 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 %arg2, i32 0, i32 0) 603 604 %val0 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 %arg2, i32 0, i32 0) 605 store volatile float %val0, float addrspace(1)* undef 606 607 ; CHECK: immarg operand has non-immediate parameter 608 ; CHECK-NEXT: i32 %arg3 609 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 0, i32 %arg3, i32 0) 610 %val1 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 0, i32 %arg3, i32 0) 611 store volatile float %val1, float addrspace(1)* undef 612 ret void 613} 614 615declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) 616define void @test_interp_mov(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3) { 617 ; CHECK: immarg operand has non-immediate parameter 618 ; CHECK-NEXT: i32 %arg0 619 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.mov(i32 %arg0, i32 0, i32 0, i32 0) 620 %val0 = call float @llvm.amdgcn.interp.mov(i32 %arg0, i32 0, i32 0, i32 0) 621 store volatile float %val0, float addrspace(1)* undef 622 623 ; CHECK: immarg operand has non-immediate parameter 624 ; CHECK-NEXT: i32 %arg1 625 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.mov(i32 0, i32 %arg1, i32 0, i32 0) 626 %val1 = call float @llvm.amdgcn.interp.mov(i32 0, i32 %arg1, i32 0, i32 0) 627 store volatile float %val1, float addrspace(1)* undef 628 629 ; CHECK: immarg operand has non-immediate parameter 630 ; CHECK-NEXT: i32 %arg2 631 ; CHECK-NEXT: %val2 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 %arg2, i32 0) 632 %val2 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 %arg2, i32 0) 633 store volatile float %val2, float addrspace(1)* undef 634 635 ret void 636} 637 638declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) 639define void @test_interp_p1_f16(float %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg4) { 640 ; CHECK: immarg operand has non-immediate parameter 641 ; CHECK-NEXT: i32 %arg1 642 ; CHECK-NEXT:%val0 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 %arg1, i32 2, i1 false, i32 %arg4) 643 %val0 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 %arg1, i32 2, i1 0, i32 %arg4) 644 store volatile float %val0, float addrspace(1)* undef 645 646 ; CHECK: immarg operand has non-immediate parameter 647 ; CHECK-NEXT:i32 %arg2 648 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 %arg2, i1 false, i32 %arg4) 649 %val1 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 %arg2, i1 0, i32 %arg4) 650 store volatile float %val1, float addrspace(1)* undef 651 652 ; CHECK: immarg operand has non-immediate parameter 653 ; CHECK-NEXT:i1 %arg3 654 ; CHECK-NEXT: %val2 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 0, i1 %arg3, i32 %arg4) 655 %val2 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 0, i1 %arg3, i32 %arg4) 656 store volatile float %val2, float addrspace(1)* undef 657 658 ret void 659} 660 661declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32) 662define void @test_interp_p2_f16(float %arg0, float %arg1, i32 %arg2, i32 %arg3, i1 %arg4, i32 %arg5) { 663 ; CHECK: immarg operand has non-immediate parameter 664 ; CHECK-NEXT: i32 %arg2 665 ; CHECK-NEXT: %val0 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 %arg2, i32 2, i1 false, i32 %arg5) 666 %val0 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 %arg2, i32 2, i1 false, i32 %arg5) 667 store volatile half %val0, half addrspace(1)* undef 668 669 ; CHECK: immarg operand has non-immediate parameter 670 ; CHECK-NEXT: i32 %arg3 671 ; CHECK-NEXT: %val1 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 %arg3, i1 false, i32 %arg5) 672 %val1 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 %arg3, i1 false, i32 %arg5) 673 store volatile half %val1, half addrspace(1)* undef 674 675 ; CHECK: immarg operand has non-immediate parameter 676 ; CHECK-NEXT: i1 %arg4 677 ; CHECK-NEXT: %val2 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 0, i1 %arg4, i32 %arg5) 678 %val2 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 0, i1 %arg4, i32 %arg5) 679 store volatile half %val2, half addrspace(1)* undef 680 681 ret void 682} 683 684declare <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x i32>, i32, i32, i32) 685define void @test_mfma_f32_32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 %arg3, i32 %arg4, i32 %arg5) { 686 ; CHECK: immarg operand has non-immediate parameter 687 ; CHECK-NEXT: i32 %arg3 688 ; CHECK-NEXT: %val0 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 %arg3, i32 2, i32 3) 689 %val0 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 %arg3, i32 2, i32 3) 690 store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef 691 692 ; CHECK: immarg operand has non-immediate parameter 693 ; CHECK-NEXT: i32 %arg4 694 ; CHECK-NEXT: %val1 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 1, i32 %arg4, i32 3) 695 %val1 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 1, i32 %arg4, i32 3) 696 store volatile <32 x i32> %val1, <32 x i32> addrspace(1)* undef 697 698 ; CHECK: immarg operand has non-immediate parameter 699 ; CHECK-NEXT: i32 %arg5 700 ; CHECK-NEXT: %val2 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 1, i32 2, i32 %arg5) 701 %val2 = call <32 x i32> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2, i32 1, i32 2, i32 %arg5) 702 store volatile <32 x i32> %val2, <32 x i32> addrspace(1)* undef 703 704 ret void 705} 706 707declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1) 708define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) { 709 ; CHECK: immarg operand has non-immediate parameter 710 ; CHECK-NEXT: i1 %slc 711 ; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc) 712 call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc) 713 ret void 714} 715