1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6ld3 {v0.s, v1.s, v2.s}[0], [sp] 7ld3r {v0.2s, v1.2s, v2.2s}, [sp] 8ld3 {v0.2s, v1.2s, v2.2s}, [sp] 9 10ld3 {v0.d, v1.d, v2.d}[0], [sp] 11ld3r {v0.2d, v1.2d, v2.2d}, [sp] 12ld3 {v0.2d, v1.2d, v2.2d}, [sp] 13 14ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 15ld3r {v0.2s, v1.2s, v2.2s}, [sp], #12 16ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 17 18ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 19ld3r {v0.2d, v1.2d, v2.2d}, [sp], #24 20ld3 {v0.2d, v1.2d, v2.2d}, [sp], #48 21 22ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 23ld3r {v0.2s, v1.2s, v2.2s}, [sp], x0 24ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 25 26ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 27ld3r {v0.2d, v1.2d, v2.2d}, [sp], x0 28ld3 {v0.2d, v1.2d, v2.2d}, [sp], x0 29 30# ALL: Iterations: 100 31# ALL-NEXT: Instructions: 1800 32 33# M3-NEXT: Total Cycles: 12501 34# M4-NEXT: Total Cycles: 11804 35# M5-NEXT: Total Cycles: 12903 36 37# ALL-NEXT: Total uOps: 7500 38 39# ALL: Dispatch Width: 6 40 41# M3-NEXT: uOps Per Cycle: 0.60 42# M3-NEXT: IPC: 0.14 43# M3-NEXT: Block RThroughput: 84.0 44 45# M4-NEXT: uOps Per Cycle: 0.64 46# M4-NEXT: IPC: 0.15 47# M4-NEXT: Block RThroughput: 54.0 48 49# M5-NEXT: uOps Per Cycle: 0.58 50# M5-NEXT: IPC: 0.14 51# M5-NEXT: Block RThroughput: 22.5 52 53# ALL: Instruction Info: 54# ALL-NEXT: [1]: #uOps 55# ALL-NEXT: [2]: Latency 56# ALL-NEXT: [3]: RThroughput 57# ALL-NEXT: [4]: MayLoad 58# ALL-NEXT: [5]: MayStore 59# ALL-NEXT: [6]: HasSideEffects (U) 60 61# ALL: [1] [2] [3] [4] [5] [6] Instructions: 62 63# M3-NEXT: 4 7 1.00 * ld3 { v0.s, v1.s, v2.s }[0], [sp] 64# M3-NEXT: 3 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp] 65# M3-NEXT: 3 12 9.00 * ld3 { v0.2s, v1.2s, v2.2s }, [sp] 66# M3-NEXT: 5 6 6.00 * ld3 { v0.d, v1.d, v2.d }[0], [sp] 67# M3-NEXT: 3 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp] 68# M3-NEXT: 3 12 9.00 * ld3 { v0.2d, v1.2d, v2.2d }, [sp] 69# M3-NEXT: 5 7 1.00 * ld3 { v0.s, v1.s, v2.s }[0], [sp], #12 70# M3-NEXT: 4 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], #12 71# M3-NEXT: 4 12 9.00 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], #24 72# M3-NEXT: 6 6 6.00 * ld3 { v0.d, v1.d, v2.d }[0], [sp], #24 73# M3-NEXT: 4 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], #24 74# M3-NEXT: 4 12 9.00 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], #48 75# M3-NEXT: 5 7 1.00 * ld3 { v0.s, v1.s, v2.s }[0], [sp], x0 76# M3-NEXT: 4 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], x0 77# M3-NEXT: 4 12 9.00 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], x0 78# M3-NEXT: 6 6 6.00 * ld3 { v0.d, v1.d, v2.d }[0], [sp], x0 79# M3-NEXT: 4 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], x0 80# M3-NEXT: 4 12 9.00 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], x0 81 82# M4-NEXT: 4 7 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp] 83# M4-NEXT: 3 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp] 84# M4-NEXT: 3 12 4.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp] 85# M4-NEXT: 5 7 4.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp] 86# M4-NEXT: 3 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp] 87# M4-NEXT: 3 12 4.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp] 88# M4-NEXT: 5 7 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp], #12 89# M4-NEXT: 4 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], #12 90# M4-NEXT: 4 12 4.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], #24 91# M4-NEXT: 6 7 4.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp], #24 92# M4-NEXT: 4 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], #24 93# M4-NEXT: 4 12 4.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], #48 94# M4-NEXT: 5 7 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp], x0 95# M4-NEXT: 4 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], x0 96# M4-NEXT: 4 12 4.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], x0 97# M4-NEXT: 6 7 4.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp], x0 98# M4-NEXT: 4 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], x0 99# M4-NEXT: 4 12 4.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], x0 100 101# M5-NEXT: 4 8 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp] 102# M5-NEXT: 3 7 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp] 103# M5-NEXT: 3 13 1.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp] 104# M5-NEXT: 5 8 1.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp] 105# M5-NEXT: 3 7 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp] 106# M5-NEXT: 3 13 1.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp] 107# M5-NEXT: 5 8 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp], #12 108# M5-NEXT: 4 7 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], #12 109# M5-NEXT: 4 13 1.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], #24 110# M5-NEXT: 6 8 1.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp], #24 111# M5-NEXT: 4 7 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], #24 112# M5-NEXT: 4 13 1.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], #48 113# M5-NEXT: 5 8 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp], x0 114# M5-NEXT: 4 7 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp], x0 115# M5-NEXT: 4 13 1.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp], x0 116# M5-NEXT: 6 8 1.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp], x0 117# M5-NEXT: 4 7 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp], x0 118# M5-NEXT: 4 13 1.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp], x0 119