1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6ldr s0, 1f 7ldr q0, 1f 8 9ldur d0, [sp, #2] 10ldur q0, [sp, #16] 11 12ldr b0, [sp], #1 13ldr q0, [sp], #16 14 15ldr h0, [sp, #2]! 16ldr q0, [sp, #16]! 17 18ldr s0, [sp, #4] 19ldr q0, [sp, #16] 20 21ldr d0, [sp, x0, lsl #3] 22ldr q0, [sp, x0, lsl #4] 23 24ldr b0, [sp, x0] 25ldr q0, [sp, x0] 26 27ldr h0, [sp, w0, sxtw #1] 28ldr q0, [sp, w0, uxtw #4] 29 30ldr s0, [sp, w0, sxtw] 31ldr q0, [sp, w0, uxtw] 32 33ldp d0, d1, [sp], #16 34ldp q0, q1, [sp], #32 35 36ldp s0, s1, [sp, #8]! 37ldp q0, q1, [sp, #32]! 38 39ldp d0, d1, [sp, #16] 40ldp q0, q1, [sp, #32] 41 421: 43 44# ALL: Iterations: 100 45# ALL-NEXT: Instructions: 2400 46 47# M3-NEXT: Total Cycles: 4708 48# M3-NEXT: Total uOps: 3200 49 50# M4-NEXT: Total Cycles: 4708 51# M4-NEXT: Total uOps: 3200 52 53# M5-NEXT: Total Cycles: 5509 54# M5-NEXT: Total uOps: 3300 55 56# ALL: Dispatch Width: 6 57 58# M3-NEXT: uOps Per Cycle: 0.68 59# M3-NEXT: IPC: 0.51 60# M3-NEXT: Block RThroughput: 13.5 61 62# M4-NEXT: uOps Per Cycle: 0.68 63# M4-NEXT: IPC: 0.51 64# M4-NEXT: Block RThroughput: 13.0 65 66# M5-NEXT: uOps Per Cycle: 0.60 67# M5-NEXT: IPC: 0.44 68# M5-NEXT: Block RThroughput: 13.5 69 70# ALL: Instruction Info: 71# ALL-NEXT: [1]: #uOps 72# ALL-NEXT: [2]: Latency 73# ALL-NEXT: [3]: RThroughput 74# ALL-NEXT: [4]: MayLoad 75# ALL-NEXT: [5]: MayStore 76# ALL-NEXT: [6]: HasSideEffects (U) 77 78# ALL: [1] [2] [3] [4] [5] [6] Instructions: 79 80# M3-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp0 81# M3-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp0 82# M3-NEXT: 1 5 0.50 * ldur d0, [sp, #2] 83# M3-NEXT: 1 5 0.50 * ldur q0, [sp, #16] 84# M3-NEXT: 1 5 0.50 * ldr b0, [sp], #1 85# M3-NEXT: 1 5 0.50 * ldr q0, [sp], #16 86# M3-NEXT: 1 5 0.50 * ldr h0, [sp, #2]! 87# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16]! 88# M3-NEXT: 1 5 0.50 * ldr s0, [sp, #4] 89# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16] 90# M3-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3] 91# M3-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4] 92# M3-NEXT: 1 5 0.50 * ldr b0, [sp, x0] 93# M3-NEXT: 1 5 0.50 * ldr q0, [sp, x0] 94# M3-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1] 95# M3-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4] 96# M3-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw] 97# M3-NEXT: 1 5 0.50 * ldr q0, [sp, w0, uxtw] 98# M3-NEXT: 2 5 0.50 * ldp d0, d1, [sp], #16 99# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp], #32 100# M3-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]! 101# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]! 102# M3-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16] 103# M3-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32] 104 105# M4-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp0 106# M4-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp0 107# M4-NEXT: 1 5 0.50 * ldur d0, [sp, #2] 108# M4-NEXT: 1 5 0.50 * ldur q0, [sp, #16] 109# M4-NEXT: 1 5 0.50 * ldr b0, [sp], #1 110# M4-NEXT: 1 5 0.50 * ldr q0, [sp], #16 111# M4-NEXT: 1 5 0.50 * ldr h0, [sp, #2]! 112# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16]! 113# M4-NEXT: 1 5 0.50 * ldr s0, [sp, #4] 114# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16] 115# M4-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3] 116# M4-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4] 117# M4-NEXT: 1 5 0.50 * ldr b0, [sp, x0] 118# M4-NEXT: 1 5 0.50 * ldr q0, [sp, x0] 119# M4-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1] 120# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4] 121# M4-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw] 122# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw] 123# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp], #16 124# M4-NEXT: 2 5 0.50 * ldp q0, q1, [sp], #32 125# M4-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]! 126# M4-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]! 127# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16] 128# M4-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32] 129 130# M5-NEXT: 1 6 0.50 * ldr s0, {{\.?}}Ltmp0 131# M5-NEXT: 1 6 0.50 * ldr q0, {{\.?}}Ltmp0 132# M5-NEXT: 1 6 0.50 * ldur d0, [sp, #2] 133# M5-NEXT: 1 6 0.50 * ldur q0, [sp, #16] 134# M5-NEXT: 1 6 0.50 * ldr b0, [sp], #1 135# M5-NEXT: 1 6 0.50 * ldr q0, [sp], #16 136# M5-NEXT: 1 6 0.50 * ldr h0, [sp, #2]! 137# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16]! 138# M5-NEXT: 1 6 0.50 * ldr s0, [sp, #4] 139# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16] 140# M5-NEXT: 1 6 0.50 * ldr d0, [sp, x0, lsl #3] 141# M5-NEXT: 2 7 0.50 * ldr q0, [sp, x0, lsl #4] 142# M5-NEXT: 1 6 0.50 * ldr b0, [sp, x0] 143# M5-NEXT: 1 6 0.50 * ldr q0, [sp, x0] 144# M5-NEXT: 2 7 0.50 * ldr h0, [sp, w0, sxtw #1] 145# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw #4] 146# M5-NEXT: 2 7 0.50 * ldr s0, [sp, w0, sxtw] 147# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw] 148# M5-NEXT: 2 6 0.50 * ldp d0, d1, [sp], #16 149# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp], #32 150# M5-NEXT: 2 6 0.50 * ldp s0, s1, [sp, #8]! 151# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp, #32]! 152# M5-NEXT: 1 6 0.50 * ldp d0, d1, [sp, #16] 153# M5-NEXT: 1 6 1.00 * ldp q0, q1, [sp, #32] 154