1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-1
3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-2
4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=3 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-3
5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-4
6# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-DEC-2
7
8# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-1
9# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-2
10# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-DEC-1
11
12add %eax, %eax
13add %ebx, %ebx
14add %ecx, %ecx
15add %edx, %edx
16
17# BTVER2-DEC-2:        Iterations:        1500
18# BTVER2-DEC-2-NEXT:   Instructions:      6000
19# BTVER2-DEC-2-NEXT:   Total Cycles:      3003
20# BTVER2-DEC-2-NEXT:   Total uOps:        6000
21
22# BTVER2-DEC-2:        Dispatch Width:    2
23# BTVER2-DEC-2-NEXT:   uOps Per Cycle:    2.00
24# BTVER2-DEC-2-NEXT:   IPC:               2.00
25# BTVER2-DEC-2-NEXT:   Block RThroughput: 2.0
26
27# BTVER2-DEC-1:        Iterations:        1500
28# BTVER2-DEC-1-NEXT:   Instructions:      6000
29# BTVER2-DEC-1-NEXT:   Total Cycles:      6003
30# BTVER2-DEC-1-NEXT:   Total uOps:        6000
31
32# BTVER2-UOPQ-1:       Iterations:        1500
33# BTVER2-UOPQ-1-NEXT:  Instructions:      6000
34# BTVER2-UOPQ-1-NEXT:  Total Cycles:      6003
35# BTVER2-UOPQ-1-NEXT:  Total uOps:        6000
36
37# BTVER2-UOPQ-2:       Iterations:        1500
38# BTVER2-UOPQ-2-NEXT:  Instructions:      6000
39# BTVER2-UOPQ-2-NEXT:  Total Cycles:      3003
40# BTVER2-UOPQ-2-NEXT:  Total uOps:        6000
41
42# HASWELL-DEC-2:       Iterations:        1500
43# HASWELL-DEC-2-NEXT:  Instructions:      6000
44# HASWELL-DEC-2-NEXT:  Total Cycles:      3003
45# HASWELL-DEC-2-NEXT:  Total uOps:        6000
46
47# HASWELL-UOPQ-1:      Iterations:        1500
48# HASWELL-UOPQ-1-NEXT: Instructions:      6000
49# HASWELL-UOPQ-1-NEXT: Total Cycles:      6003
50# HASWELL-UOPQ-1-NEXT: Total uOps:        6000
51
52# HASWELL-UOPQ-2:      Iterations:        1500
53# HASWELL-UOPQ-2-NEXT: Instructions:      6000
54# HASWELL-UOPQ-2-NEXT: Total Cycles:      3003
55# HASWELL-UOPQ-2-NEXT: Total uOps:        6000
56
57# HASWELL-UOPQ-3:      Iterations:        1500
58# HASWELL-UOPQ-3-NEXT: Instructions:      6000
59# HASWELL-UOPQ-3-NEXT: Total Cycles:      2003
60# HASWELL-UOPQ-3-NEXT: Total uOps:        6000
61
62# HASWELL-UOPQ-4:      Iterations:        1500
63# HASWELL-UOPQ-4-NEXT: Instructions:      6000
64# HASWELL-UOPQ-4-NEXT: Total Cycles:      1503
65# HASWELL-UOPQ-4-NEXT: Total uOps:        6000
66
67# BTVER2-DEC-1:        Dispatch Width:    2
68# BTVER2-DEC-1-NEXT:   uOps Per Cycle:    1.00
69# BTVER2-DEC-1-NEXT:   IPC:               1.00
70# BTVER2-DEC-1-NEXT:   Block RThroughput: 2.0
71
72# BTVER2-UOPQ-1:       Dispatch Width:    2
73# BTVER2-UOPQ-1-NEXT:  uOps Per Cycle:    1.00
74# BTVER2-UOPQ-1-NEXT:  IPC:               1.00
75# BTVER2-UOPQ-1-NEXT:  Block RThroughput: 2.0
76
77# BTVER2-UOPQ-2:       Dispatch Width:    2
78# BTVER2-UOPQ-2-NEXT:  uOps Per Cycle:    2.00
79# BTVER2-UOPQ-2-NEXT:  IPC:               2.00
80# BTVER2-UOPQ-2-NEXT:  Block RThroughput: 2.0
81
82# HASWELL-DEC-2:       Dispatch Width:    4
83# HASWELL-DEC-2-NEXT:  uOps Per Cycle:    2.00
84# HASWELL-DEC-2-NEXT:  IPC:               2.00
85# HASWELL-DEC-2-NEXT:  Block RThroughput: 1.0
86
87# HASWELL-UOPQ-1:      Dispatch Width:    4
88# HASWELL-UOPQ-1-NEXT: uOps Per Cycle:    1.00
89# HASWELL-UOPQ-1-NEXT: IPC:               1.00
90# HASWELL-UOPQ-1-NEXT: Block RThroughput: 1.0
91
92# HASWELL-UOPQ-2:      Dispatch Width:    4
93# HASWELL-UOPQ-2-NEXT: uOps Per Cycle:    2.00
94# HASWELL-UOPQ-2-NEXT: IPC:               2.00
95# HASWELL-UOPQ-2-NEXT: Block RThroughput: 1.0
96
97# HASWELL-UOPQ-3:      Dispatch Width:    4
98# HASWELL-UOPQ-3-NEXT: uOps Per Cycle:    3.00
99# HASWELL-UOPQ-3-NEXT: IPC:               3.00
100# HASWELL-UOPQ-3-NEXT: Block RThroughput: 1.0
101
102# HASWELL-UOPQ-4:      Dispatch Width:    4
103# HASWELL-UOPQ-4-NEXT: uOps Per Cycle:    3.99
104# HASWELL-UOPQ-4-NEXT: IPC:               3.99
105# HASWELL-UOPQ-4-NEXT: Block RThroughput: 1.0
106