1 //===- llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/MC/MCRegisterInfo.h"
10 #include "llvm/MC/MCTargetOptions.h"
11 #include "llvm/Support/TargetRegistry.h"
12 #include "llvm/Support/TargetSelect.h"
13 #include "llvm/Target/TargetMachine.h"
14 #include "gtest/gtest.h"
15 #include <thread>
16
17 using namespace llvm;
18
19 std::once_flag flag;
20
InitializeAMDGPUTarget()21 void InitializeAMDGPUTarget() {
22 std::call_once(flag, []() {
23 LLVMInitializeAMDGPUTargetInfo();
24 LLVMInitializeAMDGPUTarget();
25 LLVMInitializeAMDGPUTargetMC();
26 });
27 }
28
29 std::unique_ptr<LLVMTargetMachine>
createTargetMachine(std::string TStr,StringRef CPU,StringRef FS)30 createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
31 InitializeAMDGPUTarget();
32
33 std::string Error;
34 const Target *T = TargetRegistry::lookupTarget(TStr, Error);
35 if (!T)
36 return nullptr;
37
38 TargetOptions Options;
39 return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
40 T->createTargetMachine(TStr, CPU, FS, Options, None, None)));
41 }
42
TEST(AMDGPUDwarfRegMappingTests,TestWave64DwarfRegMapping)43 TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
44 for (auto Triple :
45 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
46 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
47 if (TM && TM->getMCRegisterInfo()) {
48 auto MRI = TM->getMCRegisterInfo();
49 // Wave64 Dwarf register mapping test numbers
50 // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
51 // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
52 // A0 => 3072, A255 => 3327
53 for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
54 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
55 EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
56 }
57 }
58 }
59 }
60
TEST(AMDGPUDwarfRegMappingTests,TestWave32DwarfRegMapping)61 TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
62 for (auto Triple :
63 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
64 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
65 if (TM && TM->getMCRegisterInfo()) {
66 auto MRI = TM->getMCRegisterInfo();
67 // Wave32 Dwarf register mapping test numbers
68 // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
69 // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
70 // A0 => 2048, A255 => 2303
71 for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
72 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
73 EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
74 }
75 }
76 }
77 }
78