1{
2   "arrays": [
3      {
4         "name": "MemRef_arg",
5         "sizes": [
6            "*"
7         ],
8         "type": "i32"
9      },
10      {
11         "name": "MemRef_arg2",
12         "sizes": [
13            "*"
14         ],
15         "type": "i32"
16      }
17   ],
18   "context": "[arg1] -> {  : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
19   "name": "%bb3---%bb19",
20   "statements": [
21      {
22         "accesses": [
23            {
24               "kind": "read",
25               "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
26            },
27            {
28               "kind": "write",
29               "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg2[1 + i0] : arg1 <= 2305843009213693952 }"
30            }
31         ],
32         "domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
33         "name": "Stmt_bb3__TO__bb10",
34         "schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
35      },
36      {
37         "accesses": [
38            {
39               "kind": "read",
40               "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
41            },
42            {
43               "kind": "write",
44               "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
45            }
46         ],
47         "domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
48         "name": "Stmt_bb10",
49         "schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
50      }
51   ]
52}