1; RUN: opt %loadPolly -polly-allow-nonaffine -polly-scops -analyze < %s | FileCheck %s 2; 3; Verify only the incoming scalar x is modeled as a read in the non-affine 4; region. 5; 6; void f(int *A, int b) { 7; int x; 8; for (int i = 0; i < 1024; i++) { 9; if (b > i) 10; x = 0; 11; else if (b < 2 * i) 12; x = 3; 13; else 14; x = b; 15; 16; if (A[x]) 17; A[x] = 0; 18; } 19; } 20; 21; CHECK: Statements { 22; CHECK-NEXT: Stmt_bb3 23; CHECK-NEXT: Domain := 24; CHECK-NEXT: [b] -> { Stmt_bb3[i0] : 0 <= i0 <= 1023 and i0 < b }; 25; CHECK-NEXT: Schedule := 26; CHECK-NEXT: [b] -> { Stmt_bb3[i0] -> [i0, 2] }; 27; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] 28; CHECK-NEXT: [b] -> { Stmt_bb3[i0] -> MemRef_x_1__phi[] }; 29; CHECK-NEXT: Stmt_bb7 30; CHECK-NEXT: Domain := 31; CHECK-NEXT: [b] -> { Stmt_bb7[i0] : i0 >= b and 0 <= i0 <= 1023 and 2i0 > b }; 32; CHECK-NEXT: Schedule := 33; CHECK-NEXT: [b] -> { Stmt_bb7[i0] -> [i0, 1] }; 34; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] 35; CHECK-NEXT: [b] -> { Stmt_bb7[i0] -> MemRef_x_1__phi[] }; 36; CHECK-NEXT: Stmt_bb8 37; CHECK-NEXT: Domain := 38; CHECK-NEXT: [b] -> { Stmt_bb8[0] : b = 0 }; 39; CHECK-NEXT: Schedule := 40; CHECK-NEXT: [b] -> { Stmt_bb8[i0] -> [0, 0] }; 41; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] 42; CHECK-NEXT: [b] -> { Stmt_bb8[i0] -> MemRef_x_1__phi[] }; 43; CHECK-NEXT: Stmt_bb10__TO__bb18 44; CHECK-NEXT: Domain := 45; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] : 0 <= i0 <= 1023 }; 46; CHECK-NEXT: Schedule := 47; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> [i0, 3] } 48; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] 49; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_x_1__phi[] }; 50; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] 51; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_A[o0] }; 52; CHECK-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 0] 53; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_A[o0] }; 54; CHECK-NEXT: } 55 56target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 57 58define void @f(i32* %A, i32 %b) { 59bb: 60 br label %bb1 61 62bb1: ; preds = %bb19, %bb 63 %i.0 = phi i32 [ 0, %bb ], [ %tmp20, %bb19 ] 64 %exitcond = icmp ne i32 %i.0, 1024 65 br i1 %exitcond, label %bb2, label %bb21 66 67bb2: ; preds = %bb1 68 %tmp = icmp slt i32 %i.0, %b 69 br i1 %tmp, label %bb3, label %bb4 70 71bb3: ; preds = %bb2 72 br label %bb10 73 74bb4: ; preds = %bb2 75 %tmp5 = mul nsw i32 %i.0, 2 76 %tmp6 = icmp sgt i32 %tmp5, %b 77 br i1 %tmp6, label %bb7, label %bb8 78 79bb7: ; preds = %bb4 80 br label %bb10 81 82bb8: ; preds = %bb4 83 br label %bb10 84 85bb10: ; preds = %bb9, %bb3 86 %x.1 = phi i32 [ 0, %bb3 ], [ 3, %bb7 ], [ %b, %bb8 ] 87 %tmp11 = sext i32 %x.1 to i64 88 %tmp12 = getelementptr inbounds i32, i32* %A, i64 %tmp11 89 %tmp13 = load i32, i32* %tmp12, align 4 90 %tmp14 = icmp eq i32 %tmp13, 0 91 br i1 %tmp14, label %bb18, label %bb15 92 93bb15: ; preds = %bb10 94 %tmp16 = sext i32 %x.1 to i64 95 %tmp17 = getelementptr inbounds i32, i32* %A, i64 %tmp16 96 store i32 0, i32* %tmp17, align 4 97 br label %bb18 98 99bb18: ; preds = %bb10, %bb15 100 br label %bb19 101 102bb19: ; preds = %bb18 103 %tmp20 = add nuw nsw i32 %i.0, 1 104 br label %bb1 105 106bb21: ; preds = %bb1 107 ret void 108} 109