1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the Hexagon target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Target-independent interfaces which we are implementing
16//===----------------------------------------------------------------------===//
17
18include "llvm/Target/Target.td"
19
20//===----------------------------------------------------------------------===//
21// Hexagon Subtarget features.
22//===----------------------------------------------------------------------===//
23
24// Hexagon Architectures
25def ArchV4:  SubtargetFeature<"v4",  "HexagonArchVersion", "V4",  "Hexagon V4">;
26def ArchV5:  SubtargetFeature<"v5",  "HexagonArchVersion", "V5",  "Hexagon V5">;
27def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">;
28def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
29
30// Hexagon ISA Extensions
31def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
32                                   "true", "Hexagon HVX instructions">;
33def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
34                                   "true", "Hexagon HVX Double instructions">;
35
36//===----------------------------------------------------------------------===//
37// Hexagon Instruction Predicate Definitions.
38//===----------------------------------------------------------------------===//
39def HasV5T             : Predicate<"HST->hasV5TOps()">;
40def NoV5T              : Predicate<"!HST->hasV5TOps()">;
41def HasV55T            : Predicate<"HST->hasV55TOps()">,
42                         AssemblerPredicate<"ArchV55">;
43def HasV60T            : Predicate<"HST->hasV60TOps()">,
44                         AssemblerPredicate<"ArchV60">;
45def UseMEMOP           : Predicate<"HST->useMemOps()">;
46def IEEERndNearV5T     : Predicate<"HST->modeIEEERndNear()">;
47def UseHVXDbl          : Predicate<"HST->useHVXDblOps()">,
48                         AssemblerPredicate<"ExtensionHVXDbl">;
49def UseHVXSgl          : Predicate<"HST->useHVXSglOps()">;
50def UseHVX             : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,
51                         AssemblerPredicate<"ExtensionHVX">;
52
53//===----------------------------------------------------------------------===//
54// Classes used for relation maps.
55//===----------------------------------------------------------------------===//
56
57class ImmRegShl;
58// PredRel - Filter class used to relate non-predicated instructions with their
59// predicated forms.
60class PredRel;
61// PredNewRel - Filter class used to relate predicated instructions with their
62// predicate-new forms.
63class PredNewRel: PredRel;
64// ImmRegRel - Filter class used to relate instructions having reg-reg form
65// with their reg-imm counterparts.
66class ImmRegRel;
67// NewValueRel - Filter class used to relate regular store instructions with
68// their new-value store form.
69class NewValueRel: PredNewRel;
70// NewValueRel - Filter class used to relate load/store instructions having
71// different addressing modes with each other.
72class AddrModeRel: NewValueRel;
73class IntrinsicsRel;
74
75//===----------------------------------------------------------------------===//
76// Generate mapping table to relate non-predicate instructions with their
77// predicated formats - true and false.
78//
79
80def getPredOpcode : InstrMapping {
81  let FilterClass = "PredRel";
82  // Instructions with the same BaseOpcode and isNVStore values form a row.
83  let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
84  // Instructions with the same predicate sense form a column.
85  let ColFields = ["PredSense"];
86  // The key column is the unpredicated instructions.
87  let KeyCol = [""];
88  // Value columns are PredSense=true and PredSense=false
89  let ValueCols = [["true"], ["false"]];
90}
91
92//===----------------------------------------------------------------------===//
93// Generate mapping table to relate predicate-true instructions with their
94// predicate-false forms
95//
96def getFalsePredOpcode : InstrMapping {
97  let FilterClass = "PredRel";
98  let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
99  let ColFields = ["PredSense"];
100  let KeyCol = ["true"];
101  let ValueCols = [["false"]];
102}
103
104//===----------------------------------------------------------------------===//
105// Generate mapping table to relate predicate-false instructions with their
106// predicate-true forms
107//
108def getTruePredOpcode : InstrMapping {
109  let FilterClass = "PredRel";
110  let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
111  let ColFields = ["PredSense"];
112  let KeyCol = ["false"];
113  let ValueCols = [["true"]];
114}
115
116//===----------------------------------------------------------------------===//
117// Generate mapping table to relate predicated instructions with their .new
118// format.
119//
120def getPredNewOpcode : InstrMapping {
121  let FilterClass = "PredNewRel";
122  let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
123  let ColFields = ["PNewValue"];
124  let KeyCol = [""];
125  let ValueCols = [["new"]];
126}
127
128//===----------------------------------------------------------------------===//
129// Generate mapping table to relate .new predicated instructions with their old
130// format.
131//
132def getPredOldOpcode : InstrMapping {
133  let FilterClass = "PredNewRel";
134  let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
135  let ColFields = ["PNewValue"];
136  let KeyCol = ["new"];
137  let ValueCols = [[""]];
138}
139
140//===----------------------------------------------------------------------===//
141// Generate mapping table to relate store instructions with their new-value
142// format.
143//
144def getNewValueOpcode : InstrMapping {
145  let FilterClass = "NewValueRel";
146  let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
147  let ColFields = ["NValueST"];
148  let KeyCol = ["false"];
149  let ValueCols = [["true"]];
150}
151
152//===----------------------------------------------------------------------===//
153// Generate mapping table to relate new-value store instructions with their old
154// format.
155//
156def getNonNVStore : InstrMapping {
157  let FilterClass = "NewValueRel";
158  let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
159  let ColFields = ["NValueST"];
160  let KeyCol = ["true"];
161  let ValueCols = [["false"]];
162}
163
164def getBaseWithImmOffset : InstrMapping {
165  let FilterClass = "AddrModeRel";
166  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
167                   "isFloat"];
168  let ColFields = ["addrMode"];
169  let KeyCol = ["Absolute"];
170  let ValueCols = [["BaseImmOffset"]];
171}
172
173def getAbsoluteForm : InstrMapping {
174  let FilterClass = "AddrModeRel";
175  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
176                   "isFloat"];
177  let ColFields = ["addrMode"];
178  let KeyCol = ["BaseImmOffset"];
179  let ValueCols = [["Absolute"]];
180}
181
182def getBaseWithRegOffset : InstrMapping {
183  let FilterClass = "AddrModeRel";
184  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
185  let ColFields = ["addrMode"];
186  let KeyCol = ["BaseImmOffset"];
187  let ValueCols = [["BaseRegOffset"]];
188}
189
190def xformRegToImmOffset : InstrMapping {
191  let FilterClass = "AddrModeRel";
192  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
193  let ColFields = ["addrMode"];
194  let KeyCol = ["BaseRegOffset"];
195  let ValueCols = [["BaseImmOffset"]];
196}
197
198def getBaseWithLongOffset : InstrMapping {
199  let FilterClass = "ImmRegShl";
200  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
201  let ColFields = ["addrMode"];
202  let KeyCol = ["BaseRegOffset"];
203  let ValueCols = [["BaseLongOffset"]];
204}
205
206def getRegForm : InstrMapping {
207  let FilterClass = "ImmRegRel";
208  let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
209  let ColFields = ["InputType"];
210  let KeyCol = ["imm"];
211  let ValueCols = [["reg"]];
212}
213
214def getRegShlForm : InstrMapping {
215  let FilterClass = "ImmRegShl";
216  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
217  let ColFields = ["InputType"];
218  let KeyCol = ["imm"];
219  let ValueCols = [["reg"]];
220}
221
222def notTakenBranchPrediction : InstrMapping {
223  let FilterClass = "PredRel";
224  let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
225  let ColFields = ["isBrTaken"];
226  let KeyCol = ["true"];
227  let ValueCols = [["false"]];
228}
229
230def takenBranchPrediction : InstrMapping {
231  let FilterClass = "PredRel";
232  let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
233  let ColFields = ["isBrTaken"];
234  let KeyCol = ["false"];
235  let ValueCols = [["true"]];
236}
237
238def getRealHWInstr : InstrMapping {
239  let FilterClass = "IntrinsicsRel";
240  let RowFields = ["BaseOpcode"];
241  let ColFields = ["InstrType"];
242  let KeyCol = ["Pseudo"];
243  let ValueCols = [["Pseudo"], ["Real"]];
244}
245//===----------------------------------------------------------------------===//
246// Register File, Calling Conv, Instruction Descriptions
247//===----------------------------------------------------------------------===//
248include "HexagonSchedule.td"
249include "HexagonRegisterInfo.td"
250include "HexagonCallingConv.td"
251include "HexagonInstrInfo.td"
252include "HexagonIntrinsics.td"
253include "HexagonIntrinsicsDerived.td"
254
255def HexagonInstrInfo : InstrInfo;
256
257//===----------------------------------------------------------------------===//
258// Hexagon processors supported.
259//===----------------------------------------------------------------------===//
260
261class Proc<string Name, SchedMachineModel Model,
262           list<SubtargetFeature> Features>
263 : ProcessorModel<Name, Model, Features>;
264
265def : Proc<"hexagonv4",  HexagonModelV4,
266           [ArchV4]>;
267def : Proc<"hexagonv5",  HexagonModelV4,
268           [ArchV4, ArchV5]>;
269def : Proc<"hexagonv55", HexagonModelV55,
270           [ArchV4, ArchV5, ArchV55]>;
271def : Proc<"hexagonv60", HexagonModelV60,
272           [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
273
274//===----------------------------------------------------------------------===//
275// Declare the target which we are implementing
276//===----------------------------------------------------------------------===//
277
278def HexagonAsmParser : AsmParser {
279  let ShouldEmitMatchRegisterAltName = 1;
280  bit HasMnemonicFirst = 0;
281}
282
283def HexagonAsmParserVariant : AsmParserVariant {
284  int Variant = 0;
285  string TokenizingCharacters = "#()=:.<>!+*";
286}
287
288def Hexagon : Target {
289  // Pull in Instruction Info:
290  let InstructionSet = HexagonInstrInfo;
291  let AssemblyParsers = [HexagonAsmParser];
292  let AssemblyParserVariants = [HexagonAsmParserVariant];
293}
294