1//=-  MicroMips64r6InstrInfo.td - Instruction Information  -*- tablegen -*- -=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes MicroMips64r6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15//
16// Instruction Encodings
17//
18//===----------------------------------------------------------------------===//
19
20class DAUI_MMR6_ENC : DAUI_FM_MMR6;
21class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
22class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
23class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
24class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
25class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
26class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
27class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
28class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
29class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
30class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
31class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
32class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
33class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
34class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
35class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
36class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
37class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
38class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
39class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
40class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
41class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
42class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
43class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
44class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
45class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
46class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
47class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
48class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
49class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
50class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dsbh", 0b0111101100>;
51class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
52class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll", 0b000000000>;
53class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll32", 0b000001000>;
54class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsllv", 0b000010000>;
55class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
56class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra", 0b010000000>;
57class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra32", 0b010000100>;
58class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
59class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
60class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
61class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
62class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
63class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
64class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
65class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
66class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
67class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
68class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
69class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
70
71//===----------------------------------------------------------------------===//
72//
73// Instruction Descriptions
74//
75//===----------------------------------------------------------------------===//
76
77class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
78    : MMR6Arch<instr_asm>, MipsR6Inst {
79  dag OutOperandList = (outs GPROpnd:$rt);
80  dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
81  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
82  list<dag> Pattern = [];
83}
84class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
85
86class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
87    : MMR6Arch<instr_asm>, MipsR6Inst {
88  dag OutOperandList = (outs GPROpnd:$rs);
89  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
90  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
91  string Constraints = "$rs = $rt";
92}
93class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
94class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
95
96class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
97                        Operand SizeOpnd, SDPatternOperator Op = null_frag>
98    : MMR6Arch<instr_asm>, MipsR6Inst {
99  dag OutOperandList = (outs RO:$rt);
100  dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
101  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
102  list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
103  InstrItinClass Itinerary = II_EXT;
104  Format Form = FrmR;
105  string BaseOpcode = instr_asm;
106}
107// TODO: Add 'pos + size' constraint check to dext* instructions
108//       DEXT: 0 < pos + size <= 63
109//       DEXTM, DEXTU: 32 < pos + size <= 64
110class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
111                                         uimm5_plus1, MipsExt>;
112class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
113                                          uimm5_plus33, MipsExt>;
114class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
115                                          uimm5_plus1, MipsExt>;
116
117class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
118                      Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
119  dag OutOperandList = (outs GPROpnd:$rd);
120  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
121  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
122  list<dag> Pattern = [];
123}
124
125class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
126
127class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
128class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
129class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
130class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
131
132class DCLO_MM64R6_DESC {
133  dag OutOperandList = (outs GPR64Opnd:$rt);
134  dag InOperandList = (ins GPR64Opnd:$rs);
135  string AsmString = !strconcat("dclo", "\t$rt, $rs");
136  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
137  InstrItinClass Itinerary = II_CLO;
138  Format Form = FrmR;
139  string BaseOpcode = "dclo";
140}
141
142class DCLZ_MM64R6_DESC {
143  dag OutOperandList = (outs GPR64Opnd:$rt);
144  dag InOperandList = (ins GPR64Opnd:$rs);
145  string AsmString = !strconcat("dclz", "\t$rt, $rs");
146  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
147  InstrItinClass Itinerary = II_CLZ;
148  Format Form = FrmR;
149  string BaseOpcode = "dclz";
150}
151
152class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
153                                  uimm5_inssize_plus1, MipsIns>;
154class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
155class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
156                                 MipsIns>;
157class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
158class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
159                                              II_DMTC1, bitconvert>;
160class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
161
162class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
163class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
164                                              II_DMFC1, bitconvert>;
165class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
166
167class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
168class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
169                                       II_DADDIU, immSExt16, add>,
170                           IsAsCheapAsAMove;
171class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
172
173class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
174                     InstrItinClass Itin = NoItinerary,
175                     SDPatternOperator OpNode = null_frag>
176                     : MipsR6Inst {
177  dag OutOperandList = (outs RO:$rd);
178  dag InOperandList = (ins RO:$rs, RO:$rt);
179  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
180  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
181  InstrItinClass Itinerary = Itin;
182  Format Form = FrmR;
183  string BaseOpcode = instr_asm;
184  let isCommutable = 0;
185  let isReMaterializable = 1;
186  let TwoOperandAliasConstraint = "$rd = $rs";
187}
188class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
189class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
190
191class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
192
193class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
194                           InstrItinClass Itin = NoItinerary,
195                           SDPatternOperator Op = null_frag> : MipsR6Inst {
196  dag OutOperandList = (outs GPROpnd:$rd);
197  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
198  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
199  InstrItinClass Itinerary = Itin;
200  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
201}
202
203class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
204class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
205                                              mulhs>;
206class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
207class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
208                                               mulhu>;
209
210class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
211  dag OutOperandList = (outs GPROpnd:$rt);
212  dag InOperandList = (ins GPROpnd:$rs);
213  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
214  bit hasSideEffects = 0;
215  list<dag> Pattern = [];
216  InstrItinClass Itinerary = NoItinerary;
217  Format Form = FrmR;
218  string BaseOpcode = instr_asm;
219}
220
221class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd>;
222class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
223
224class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
225                              InstrItinClass itin,
226                              SDPatternOperator OpNode = null_frag,
227                              SDPatternOperator PO = null_frag> {
228  dag OutOperandList = (outs GPR64Opnd:$rt);
229  dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
230  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
231  list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
232  InstrItinClass Itinerary = itin;
233  Format Form = FrmR;
234  string TwoOperandAliasConstraint = "$rs = $rt";
235  string BaseOpcode = instr_asm;
236}
237
238class SHIFT_ROTATE_REG_MM64R6<string instr_asm, InstrItinClass itin,
239                              SDPatternOperator OpNode = null_frag> {
240  dag OutOperandList = (outs GPR64Opnd:$rd);
241  dag InOperandList = (ins GPR64Opnd:$rt, GPR32Opnd:$rs);
242  string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
243  list<dag> Pattern = [(set GPR64Opnd:$rd,
244                       (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
245  InstrItinClass Itinerary = itin;
246  Format Form = FrmR;
247  string BaseOpcode = instr_asm;
248}
249
250class DSLL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll", uimm6, II_DSLL, shl,
251                                                 immZExt6>;
252class DSLL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll32", uimm5, II_DSLL32>;
253class DSLLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsllv", II_DSLLV, shl>;
254class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
255class DSRA_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra", uimm6, II_DSRA, sra,
256                                                 immZExt6>;
257class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
258class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
259                                                  rotr, immZExt6>;
260class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
261                                                    II_DROTR32>;
262class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
263class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
264                                                 immZExt6>;
265class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
266class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
267
268class Load_MM64R6<string instr_asm, Operand MemOpnd, InstrItinClass itin,
269                  SDPatternOperator OpNode = null_frag> {
270  dag OutOperandList = (outs GPR64Opnd:$rt);
271  dag InOperandList = (ins MemOpnd:$addr);
272  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
273  list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
274  InstrItinClass Itinerary = itin;
275  Format Form = FrmI;
276  bit mayLoad = 1;
277  bit canFoldAsLoad = 1;
278  string BaseOpcode = instr_asm;
279}
280
281class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
282  string DecoderMethod = "DecodeMemMMImm16";
283}
284class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
285  string DecoderMethod = "DecodeMemMMImm12";
286}
287
288class LLD_MM64R6_DESC {
289  dag OutOperandList = (outs GPR64Opnd:$rt);
290  dag InOperandList = (ins mem_simm12:$addr);
291  string AsmString = "lld\t$rt, $addr";
292  list<dag> Pattern = [];
293  bit mayLoad = 1;
294  InstrItinClass Itinerary = II_LLD;
295  string BaseOpcode = "lld";
296  string DecoderMethod = "DecodeMemMMImm12";
297}
298
299class SD_MM64R6_DESC {
300  dag OutOperandList = (outs);
301  dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
302  string AsmString = "sd\t$rt, $addr";
303  list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
304  InstrItinClass Itinerary = II_SD;
305  Format Form = FrmI;
306  bit mayStore = 1;
307  string BaseOpcode = "sd";
308  string DecoderMethod = "DecodeMemMMImm16";
309}
310
311//===----------------------------------------------------------------------===//
312//
313// Instruction Definitions
314//
315//===----------------------------------------------------------------------===//
316
317let DecoderNamespace = "MicroMipsR6" in {
318  def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
319  def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
320  def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
321  def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
322                    ISA_MICROMIPS64R6;
323  def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
324                     ISA_MICROMIPS64R6;
325  def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
326                     ISA_MICROMIPS64R6;
327  def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
328                      ISA_MICROMIPS64R6;
329  def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
330                    ISA_MICROMIPS64R6;
331  def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
332                    ISA_MICROMIPS64R6;
333  def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
334                     ISA_MICROMIPS64R6;
335  def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
336                     ISA_MICROMIPS64R6;
337  def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
338                    ISA_MICROMIPS64R6;
339  def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
340                    ISA_MICROMIPS64R6;
341  def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
342                   ISA_MICROMIPS64R6;
343  def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
344                     ISA_MICROMIPS64R6;
345  def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
346                     ISA_MICROMIPS64R6;
347  def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
348                     ISA_MICROMIPS64R6;
349  def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
350                     ISA_MICROMIPS64R6;
351  def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
352                     ISA_MICROMIPS64R6;
353  def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
354                     ISA_MICROMIPS64R6;
355  def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
356                   ISA_MICROMIPS64R6;
357  def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
358                     ISA_MICROMIPS64R6;
359  def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
360                    ISA_MICROMIPS64R6;
361  def LDPC_MM64R6 :  R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
362                     ISA_MICROMIPS64R6;
363  def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
364                    ISA_MICROMIPS64R6;
365  def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
366                     ISA_MICROMIPS64R6;
367  def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
368                    ISA_MICROMIPS64R6;
369  def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
370                    ISA_MICROMIPS64R6;
371  def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
372                     ISA_MICROMIPS64R6;
373  def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
374                     ISA_MICROMIPS64R6;
375  def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_ENC, DSBH_MM64R6_DESC,
376                    ISA_MICROMIPS64R6;
377  def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_ENC, DSHD_MM64R6_DESC,
378                    ISA_MICROMIPS64R6;
379  def DSLL_MM64R6 : StdMMR6Rel, DSLL_MM64R6_ENC, DSLL_MM64R6_DESC,
380                    ISA_MICROMIPS64R6;
381  def DSLL32_MM64R6 : StdMMR6Rel, DSLL32_MM64R6_ENC, DSLL32_MM64R6_DESC,
382                    ISA_MICROMIPS64R6;
383  def DSLLV_MM64R6 : StdMMR6Rel, DSLLV_MM64R6_ENC, DSLLV_MM64R6_DESC,
384                     ISA_MICROMIPS64R6;
385  def DSRAV_MM64R6 : StdMMR6Rel, DSRAV_MM64R6_ENC, DSRAV_MM64R6_DESC,
386                    ISA_MICROMIPS64R6;
387  def DSRA_MM64R6 : StdMMR6Rel, DSRA_MM64R6_ENC, DSRA_MM64R6_DESC,
388                    ISA_MICROMIPS64R6;
389  def DSRA32_MM64R6 : StdMMR6Rel, DSRA32_MM64R6_ENC, DSRA32_MM64R6_DESC,
390                    ISA_MICROMIPS64R6;
391  def DCLO_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLO_MM64R6_ENC, DCLO_MM64R6_DESC,
392                    ISA_MICROMIPS64R6;
393  def DCLZ_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLZ_MM64R6_ENC, DCLZ_MM64R6_DESC,
394                    ISA_MICROMIPS64R6;
395  def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_ENC, DROTR_MM64R6_DESC,
396                     ISA_MICROMIPS64R6;
397  def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_ENC, DROTR32_MM64R6_DESC,
398                       ISA_MICROMIPS64R6;
399  def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
400                      ISA_MICROMIPS64R6;
401  def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
402                  ISA_MICROMIPS64R6;
403  def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
404                   ISA_MICROMIPS64R6;
405  def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
406                   ISA_MICROMIPS64R6;
407  def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
408                  ISA_MICROMIPS64R6;
409  def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
410                    ISA_MICROMIPS64R6;
411  def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
412                      ISA_MICROMIPS64R6;
413  def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
414                     ISA_MICROMIPS64R6;
415}
416
417//===----------------------------------------------------------------------===//
418//
419// Arbitrary patterns that map to one or more instructions
420//
421//===----------------------------------------------------------------------===//
422
423def : MipsPat<(MipsLo tglobaladdr:$in),
424              (DADDIU_MM64R6 ZERO_64, tglobaladdr:$in)>, ISA_MICROMIPS64R6;
425def : MipsPat<(MipsLo tblockaddress:$in),
426              (DADDIU_MM64R6 ZERO_64, tblockaddress:$in)>, ISA_MICROMIPS64R6;
427def : MipsPat<(MipsLo tjumptable:$in),
428              (DADDIU_MM64R6 ZERO_64, tjumptable:$in)>, ISA_MICROMIPS64R6;
429def : MipsPat<(MipsLo tconstpool:$in),
430              (DADDIU_MM64R6 ZERO_64, tconstpool:$in)>, ISA_MICROMIPS64R6;
431def : MipsPat<(MipsLo tglobaltlsaddr:$in),
432              (DADDIU_MM64R6 ZERO_64, tglobaltlsaddr:$in)>, ISA_MICROMIPS64R6;
433def : MipsPat<(MipsLo texternalsym:$in),
434              (DADDIU_MM64R6 ZERO_64, texternalsym:$in)>, ISA_MICROMIPS64R6;
435
436def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
437              (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
438def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
439              (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
440def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
441              (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
442def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
443              (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
444def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
445              (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
446
447def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
448              (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
449def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
450              (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
451
452
453def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
454              (DROTRV_MM64R6 GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
455              ISA_MICROMIPS64R6;
456
457
458def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
459def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
460def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
461def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
462def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
463def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
464
465// Carry pattern
466def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
467              (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
468
469def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
470
471//===----------------------------------------------------------------------===//
472//
473// Instruction aliases
474//
475//===----------------------------------------------------------------------===//
476
477def : MipsInstAlias<"dmtc0 $rt, $rd",
478                    (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
479def : MipsInstAlias<"dmfc0 $rt, $rd",
480                    (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
481                    ISA_MICROMIPS64R6;
482def : MipsInstAlias<"daddu $rs, $rt, $imm",
483                    (DADDIU_MM64R6 GPR64Opnd:$rs,
484                                   GPR64Opnd:$rt,
485                                   simm16_64:$imm),
486                    0>, ISA_MICROMIPS64R6;
487def : MipsInstAlias<"daddu $rs, $imm",
488                    (DADDIU_MM64R6 GPR64Opnd:$rs,
489                                   GPR64Opnd:$rs,
490                                   simm16_64:$imm),
491                    0>, ISA_MICROMIPS64R6;
492def : MipsInstAlias<"dsubu $rt, $rs, $imm",
493                    (DADDIU_MM64R6 GPR64Opnd:$rt,
494                                   GPR64Opnd:$rs,
495                                   InvertedImOperand64:$imm),
496                    0>, ISA_MICROMIPS64R6;
497def : MipsInstAlias<"dsubu $rs, $imm",
498                    (DADDIU_MM64R6 GPR64Opnd:$rs,
499                                   GPR64Opnd:$rs,
500                                   InvertedImOperand64:$imm),
501                    0>, ISA_MICROMIPS64R6;
502def : MipsInstAlias<"dneg $rt, $rs",
503                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
504                    ISA_MICROMIPS64R6;
505def : MipsInstAlias<"dneg $rt",
506                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
507                    ISA_MICROMIPS64R6;
508def : MipsInstAlias<"dnegu $rt, $rs",
509                    (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
510                    ISA_MICROMIPS64R6;
511def : MipsInstAlias<"dnegu $rt",
512                    (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
513                    ISA_MICROMIPS64R6;
514