1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines hazard recognizers for scheduling on PowerPC processors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
16 
17 #include "PPCInstrInfo.h"
18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
19 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 
22 namespace llvm {
23 
24 /// PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based
25 /// hazard recognizer for PPC ooo processors with dispatch-group hazards.
26 class PPCDispatchGroupSBHazardRecognizer : public ScoreboardHazardRecognizer {
27   const ScheduleDAG *DAG;
28   SmallVector<SUnit *, 7> CurGroup;
29   unsigned CurSlots, CurBranches;
30 
31   bool isLoadAfterStore(SUnit *SU);
32   bool isBCTRAfterSet(SUnit *SU);
33   bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
34 public:
PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData * ItinData,const ScheduleDAG * DAG_)35   PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData,
36                          const ScheduleDAG *DAG_) :
37     ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
38     CurSlots(0), CurBranches(0) {}
39 
40   HazardType getHazardType(SUnit *SU, int Stalls) override;
41   bool ShouldPreferAnother(SUnit* SU) override;
42   unsigned PreEmitNoops(SUnit *SU) override;
43   void EmitInstruction(SUnit *SU) override;
44   void AdvanceCycle() override;
45   void RecedeCycle() override;
46   void Reset() override;
47   void EmitNoop() override;
48 };
49 
50 /// PPCHazardRecognizer970 - This class defines a finite state automata that
51 /// models the dispatch logic on the PowerPC 970 (aka G5) processor.  This
52 /// promotes good dispatch group formation and implements noop insertion to
53 /// avoid structural hazards that cause significant performance penalties (e.g.
54 /// setting the CTR register then branching through it within a dispatch group),
55 /// or storing then loading from the same address within a dispatch group.
56 class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
57   const ScheduleDAG &DAG;
58 
59   unsigned NumIssued;  // Number of insts issued, including advanced cycles.
60 
61   // Various things that can cause a structural hazard.
62 
63   // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
64   bool HasCTRSet;
65 
66   // StoredPtr - Keep track of the address of any store.  If we see a load from
67   // the same address (or one that aliases it), disallow the store.  We can have
68   // up to four stores in one dispatch group, hence we track up to 4.
69   //
70   // This is null if we haven't seen a store yet.  We keep track of both
71   // operands of the store here, since we support [r+r] and [r+i] addressing.
72   const Value *StoreValue[4];
73   int64_t StoreOffset[4];
74   uint64_t StoreSize[4];
75   unsigned NumStores;
76 
77 public:
78   PPCHazardRecognizer970(const ScheduleDAG &DAG);
79   HazardType getHazardType(SUnit *SU, int Stalls) override;
80   void EmitInstruction(SUnit *SU) override;
81   void AdvanceCycle() override;
82   void Reset() override;
83 
84 private:
85   /// EndDispatchGroup - Called when we are finishing a new dispatch group.
86   ///
87   void EndDispatchGroup();
88 
89   /// GetInstrType - Classify the specified powerpc opcode according to its
90   /// pipeline.
91   PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
92                                   bool &isFirst, bool &isSingle,bool &isCracked,
93                                   bool &isLoad, bool &isStore);
94 
95   bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
96                              const Value *LoadValue) const;
97 };
98 
99 } // end namespace llvm
100 
101 #endif
102 
103