1; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
2
3define signext i8 @test_vminv_s8(<8 x i8> %a1) {
4; CHECK: test_vminv_s8
5; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
6; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
7; CHECK-NEXT: ret
8entry:
9  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
10  %0 = trunc i32 %vminv.i to i8
11  ret i8 %0
12}
13
14define signext i16 @test_vminv_s16(<4 x i16> %a1) {
15; CHECK: test_vminv_s16
16; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
17; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
18; CHECK-NEXT: ret
19entry:
20  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
21  %0 = trunc i32 %vminv.i to i16
22  ret i16 %0
23}
24
25define i32 @test_vminv_s32(<2 x i32> %a1) {
26; CHECK: test_vminv_s32
27; 2 x i32 is not supported by the ISA, thus, this is a special case
28; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
29; CHECK-NEXT: fmov w0, s[[REGNUM]]
30; CHECK-NEXT: ret
31entry:
32  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
33  ret i32 %vminv.i
34}
35
36define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
37; CHECK: test_vminvq_s8
38; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
39; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
40; CHECK-NEXT: ret
41entry:
42  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
43  %0 = trunc i32 %vminv.i to i8
44  ret i8 %0
45}
46
47define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
48; CHECK: test_vminvq_s16
49; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
50; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
51; CHECK-NEXT: ret
52entry:
53  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
54  %0 = trunc i32 %vminv.i to i16
55  ret i16 %0
56}
57
58define i32 @test_vminvq_s32(<4 x i32> %a1) {
59; CHECK: test_vminvq_s32
60; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
61; CHECK-NEXT: fmov w0, [[REGNUM]]
62; CHECK-NEXT: ret
63entry:
64  %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
65  ret i32 %vminv.i
66}
67
68define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
69; CHECK-LABEL: test_vminv_s8_used_by_laneop:
70; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
71; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
72; CHECK-NEXT: ret
73entry:
74  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
75  %1 = trunc i32 %0 to i8
76  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
77  ret <8 x i8> %2
78}
79
80define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
81; CHECK-LABEL: test_vminv_s16_used_by_laneop:
82; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
83; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
84; CHECK-NEXT: ret
85entry:
86  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
87  %1 = trunc i32 %0 to i16
88  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
89  ret <4 x i16> %2
90}
91
92define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
93; CHECK-LABEL: test_vminv_s32_used_by_laneop:
94; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
95; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
96; CHECK-NEXT: ret
97entry:
98  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
99  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
100  ret <2 x i32> %1
101}
102
103define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
104; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
105; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
106; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
107; CHECK-NEXT: ret
108entry:
109  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
110  %1 = trunc i32 %0 to i8
111  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
112  ret <16 x i8> %2
113}
114
115define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
116; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
117; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
118; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
119; CHECK-NEXT: ret
120entry:
121  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
122  %1 = trunc i32 %0 to i16
123  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
124  ret <8 x i16> %2
125}
126
127define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
128; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
129; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
130; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
131; CHECK-NEXT: ret
132entry:
133  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
134  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
135  ret <4 x i32> %1
136}
137
138declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
139declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
140declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
141declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
142declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
143declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
144
145