1; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s
3; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
4; RUN: llc -mtriple=armv6-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
5
6; The performance monitor we're looking for is an ARMv7 extension. It should be
7; possible to disable it, but realistically present on at least every v7-A
8; processor (but not on v6, at least by default).
9
10declare i64 @llvm.readcyclecounter()
11
12define i64 @get_count() {
13  %val = call i64 @llvm.readcyclecounter()
14  ret i64 %val
15
16  ; As usual, exact registers only sort of matter but the cycle-count had better
17  ; end up in r0 in the end.
18
19; CHECK: mrc p15, #0, r0, c9, c13, #0
20; CHECK: {{movs?}} r1, #0
21
22; CHECK-NO-PERFMON: {{movs?}} r0, #0
23; CHECK-NO-PERFMON: {{movs?}} r1, #0
24}
25