1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2; Check that gp-relative instructions are being generated.
3
4@a = common global i32 0, align 4
5@b = common global i32 0, align 4
6@c = common global i32 0, align 4
7
8define i32 @foo(i32 %p) #0 {
9entry:
10; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a)
11; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b)
12; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
13  %0 = load i32, i32* @a, align 4
14  %1 = load i32, i32* @b, align 4
15  %add = add nsw i32 %1, %0
16  %cmp = icmp eq i32 %0, %1
17  br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
18
19entry.if.end_crit_edge:
20  %.pre = load i32, i32* @c, align 4
21  br label %if.end
22
23if.then:
24  %add1 = add nsw i32 %add, %0
25  store i32 %add1, i32* @c, align 4
26  br label %if.end
27
28if.end:
29  %2 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %add1, %if.then ]
30  %cmp2 = icmp eq i32 %add, %2
31  %sel1 = select i1 %cmp2, i32 %2, i32 %1
32  ret i32 %sel1
33}
34