1; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
2
3; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
4; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
5; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
6; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
7; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
8; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
9; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
10; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
11
12define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
13entry:
14        %tmp1 = zext i64 %AL to i128
15        %tmp23 = zext i64 %AH to i128
16        %tmp4 = shl i128 %tmp23, 64
17        %tmp5 = or i128 %tmp4, %tmp1
18        %tmp67 = zext i64 %BL to i128
19        %tmp89 = zext i64 %BH to i128
20        %tmp11 = shl i128 %tmp89, 64
21        %tmp12 = or i128 %tmp11, %tmp67
22        %tmp15 = sub i128 %tmp5, %tmp12
23        %tmp1617 = trunc i128 %tmp15 to i64
24        store i64 %tmp1617, i64* %RL
25        %tmp21 = lshr i128 %tmp15, 64
26        %tmp2122 = trunc i128 %tmp21 to i64
27        store i64 %tmp2122, i64* %RH
28        ret void
29}
30