1; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60  < %s | FileCheck %s
2
3; CHECK: q{{[0-3]}} = v{{[0-9]*}}and(v{{[0-9]*}},r{{[0-9]*}})
4target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
5target triple = "hexagon"
6
7@K = global i64 0, align 8
8@src = global i8 -1, align 1
9@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64
10@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
11@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64
12@VectorResult = common global <16 x i32> zeroinitializer, align 64
13@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128
14@VectorPairResult = common global <32 x i32> zeroinitializer, align 128
15@dst_addresses = common global [15 x i8] zeroinitializer, align 8
16@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8
17@src_addresses = common global [15 x i8*] zeroinitializer, align 8
18@dst = common global i8 0, align 1
19@ptr = common global [32768 x i8] zeroinitializer, align 8
20
21; Function Attrs: nounwind
22define i32 @main() #0 {
23entry:
24  %retval = alloca i32, align 4
25  store i32 0, i32* %retval, align 4
26  %0 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64
27  %1 = bitcast <16 x i32> %0 to <512 x i1>
28  %2 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 1), align 64
29  %3 = bitcast <16 x i32> %2 to <512 x i1>
30  %4 = call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %1, <512 x i1> %3)
31  %5 = bitcast <512 x i1> %4 to <16 x i32>
32  store volatile <16 x i32> %5, <16 x i32>* @Q6VecPredResult, align 64
33  %6 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64
34  %7 = bitcast <16 x i32> %6 to <512 x i1>
35  %8 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 1), align 64
36  %9 = bitcast <16 x i32> %8 to <512 x i1>
37  %10 = call <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1> %7, <512 x i1> %9)
38  %11 = bitcast <512 x i1> %10 to <16 x i32>
39  store volatile <16 x i32> %11, <16 x i32>* @Q6VecPredResult, align 64
40  ret i32 0
41
42}
43
44; Function Attrs: nounwind readnone
45declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1
46
47; Function Attrs: nounwind readnone
48declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1
49
50attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" }
51attributes #1 = { nounwind readnone }
52