1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s -O0
2
3; This is a regression test which makes sure that the offset check
4; is available for STRiw_indexed instruction. This is required
5; by 'Hexagon Expand Predicate Spill Code' pass.
6
7define i32 @f(i32 %a, i32 %b) nounwind {
8entry:
9  %retval = alloca i32, align 4
10  %a.addr = alloca i32, align 4
11  %b.addr = alloca i32, align 4
12  store i32 %a, i32* %a.addr, align 4
13  store i32 %b, i32* %b.addr, align 4
14  %0 = load i32, i32* %a.addr, align 4
15  %1 = load i32, i32* %b.addr, align 4
16  %cmp = icmp sgt i32 %0, %1
17  br i1 %cmp, label %if.then, label %if.else
18
19if.then:
20  %2 = load i32, i32* %a.addr, align 4
21  %3 = load i32, i32* %b.addr, align 4
22  %add = add nsw i32 %2, %3
23  store i32 %add, i32* %retval
24  br label %return
25
26if.else:
27  %4 = load i32, i32* %a.addr, align 4
28  %5 = load i32, i32* %b.addr, align 4
29  %sub = sub nsw i32 %4, %5
30  store i32 %sub, i32* %retval
31  br label %return
32
33return:
34  %6 = load i32, i32* %retval
35  ret i32 %6
36}
37