1; RUN: llc -march=hexagon < %s
2; REQUIRES: asserts
3
4target triple = "hexagon"
5
6; Function Attrs: nounwind
7define void @fred() #0 {
8entry:
9  br label %for.body9.us
10
11for.body9.us:
12  %cmp10.us = icmp eq i32 0, undef
13  %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
14  %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
15  %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0)
16  %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
17  %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
18  %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
19  store <16 x i32> %4, <16 x i32>* undef, align 64
20  br i1 undef, label %for.body9.us, label %for.body43.us.preheader
21
22for.body43.us.preheader:                          ; preds = %for.body9.us
23  ret void
24}
25
26declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
27declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1
28declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
29declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
30declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
31
32attributes #0 = { nounwind }
33attributes #1 = { nounwind readnone }
34