1; RUN: llc < %s | FileCheck %s
2
3; Test custom lowering for 32-bit integer multiplication.
4
5target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
6target triple = "lanai"
7
8; CHECK-LABEL: f6:
9; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
10; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
11; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
12define i32 @f6(i32 inreg %a) #0 {
13  %1 = mul nsw i32 %a, 6
14  ret i32 %1
15}
16
17; CHECK-LABEL: f7:
18; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
19; CHECK: sub %r{{[0-9]+}}, %r6, %rv
20define i32 @f7(i32 inreg %a) #0 {
21  %1 = mul nsw i32 %a, 7
22  ret i32 %1
23}
24
25; CHECK-LABEL: f8:
26; CHECK: sh %r6, 0x3, %rv
27define i32 @f8(i32 inreg %a) #0 {
28  %1 = shl nsw i32 %a, 3
29  ret i32 %1
30}
31
32; CHECK-LABEL: f9:
33; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
34; CHECK: add %r{{[0-9]+}}, %r6, %rv
35define i32 @f9(i32 inreg %a) #0 {
36  %1 = mul nsw i32 %a, 9
37  ret i32 %1
38}
39
40; CHECK-LABEL: f10:
41; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
42; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
43; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
44define i32 @f10(i32 inreg %a) #0 {
45  %1 = mul nsw i32 %a, 10
46  ret i32 %1
47}
48
49; CHECK-LABEL: f1280:
50; CHECK: sh %r6, 0x8, %r{{[0-9]+}}
51; CHECK: sh %r6, 0xa, %r{{[0-9]+}}
52; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
53define i32 @f1280(i32 inreg %a) #0 {
54  %1 = mul nsw i32 %a, 1280
55  ret i32 %1
56}
57
58; CHECK-LABEL: fm6:
59; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
60; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
61; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
62define i32 @fm6(i32 inreg %a) #0 {
63  %1 = mul nsw i32 %a, -6
64  ret i32 %1
65}
66
67; CHECK-LABEL: fm7:
68; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
69; CHECK: sub %r6, %r{{[0-9]+}}, %rv
70define i32 @fm7(i32 inreg %a) #0 {
71  %1 = mul nsw i32 %a, -7
72  ret i32 %1
73}
74
75; CHECK-LABEL: fm8:
76; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
77; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
78define i32 @fm8(i32 inreg %a) #0 {
79  %1 = mul nsw i32 %a, -8
80  ret i32 %1
81}
82
83; CHECK-LABEL: fm9:
84; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
85; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}}
86; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
87define i32 @fm9(i32 inreg %a) #0 {
88  %1 = mul nsw i32 %a, -9
89  ret i32 %1
90}
91
92; CHECK-LABEL: fm10:
93; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
94; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
95; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
96; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
97define i32 @fm10(i32 inreg %a) #0 {
98  %1 = mul nsw i32 %a, -10
99  ret i32 %1
100}
101
102; CHECK-LABEL: h1:
103; CHECK: __mulsi3
104define i32 @h1(i32 inreg %a) #0 {
105  %1 = mul i32 %a, -1431655765
106  ret i32 %1
107}
108