1# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s 2 3# Test the compare fold peephole. 4 5# CHECK-LABEL: name: test0a 6# TODO: Enhance combiner to handle this case. This expands into: 7# sub %r7, %r6, %r3 8# sub.f %r7, %r6, %r0 9# sel.eq %r18, %r3, %rv 10# This is different from the pattern currently matched. If the lowered form had 11# been sub.f %r3, 0, %r0 then it would have matched. 12 13# CHECK-LABEL: name: test1a 14# CHECK: [[IN1:%.*]] = COPY %r7 15# CHECK: [[IN2:%.*]] = COPY %r6 16# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr 17 18# CHECK-LABEL: name: test1b 19# CHECK: [[IN1:%.*]] = COPY %r7 20# CHECK: [[IN2:%.*]] = COPY %r6 21# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr 22 23# CHECK-LABEL: name: test2a 24# CHECK: [[IN1:%.*]] = COPY %r7 25# CHECK: [[IN2:%.*]] = COPY %r6 26# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr 27 28# CHECK-LABEL: name: test2b 29# CHECK: [[IN1:%.*]] = COPY %r7 30# CHECK: [[IN2:%.*]] = COPY %r6 31# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr 32 33# CHECK-LABEL: name: test3 34# CHECK: AND_F_R 35# CHECK: AND_F_R 36# CHECK: AND_F_R 37 38--- | 39 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" 40 target triple = "lanai-unknown-unknown" 41 42 @a = global i32 -1, align 4 43 @b = global i32 0, align 4 44 45 define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 46 entry: 47 %sub = sub i32 %b, %a 48 %cmp = icmp eq i32 %sub, 0 49 %cond = select i1 %cmp, i32 %c, i32 %sub 50 ret i32 %cond 51 } 52 53 define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 54 entry: 55 %cmp = icmp eq i32 %b, %a 56 %cond = select i1 %cmp, i32 %c, i32 %b 57 ret i32 %cond 58 } 59 60 define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 61 entry: 62 %sub = sub i32 %b, %a 63 %cmp = icmp slt i32 %sub, 0 64 %cond = select i1 %cmp, i32 %c, i32 %d 65 ret i32 %cond 66 } 67 68 define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 69 entry: 70 %sub = sub i32 %b, %a 71 %cmp = icmp slt i32 %sub, 0 72 %cond = select i1 %cmp, i32 %c, i32 %d 73 ret i32 %cond 74 } 75 76 define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 77 entry: 78 %sub = sub i32 %b, %a 79 %cmp = icmp sgt i32 %sub, -1 80 %cond = select i1 %cmp, i32 %c, i32 %d 81 ret i32 %cond 82 } 83 84 define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 85 entry: 86 %sub = sub i32 %b, %a 87 %cmp = icmp sgt i32 %sub, -1 88 %cond = select i1 %cmp, i32 %c, i32 %d 89 ret i32 %cond 90 } 91 92 define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 93 entry: 94 %sub = sub i32 %b, %a 95 %cmp = icmp slt i32 %sub, 1 96 %cond = select i1 %cmp, i32 %c, i32 %d 97 ret i32 %cond 98 } 99 100 define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 101 entry: 102 %cmp = icmp ne i32 %a, 0 103 %cmp1 = icmp ult i32 %a, %b 104 %or.cond = and i1 %cmp, %cmp1 105 br i1 %or.cond, label %return, label %if.end 106 107 if.end: ; preds = %entry 108 %cmp2 = icmp ne i32 %b, 0 109 %cmp4 = icmp ult i32 %b, %c 110 %or.cond29 = and i1 %cmp2, %cmp4 111 br i1 %or.cond29, label %return, label %if.end6 112 113 if.end6: ; preds = %if.end 114 %cmp7 = icmp ne i32 %c, 0 115 %cmp9 = icmp ult i32 %c, %d 116 %or.cond30 = and i1 %cmp7, %cmp9 117 br i1 %or.cond30, label %return, label %if.end11 118 119 if.end11: ; preds = %if.end6 120 %cmp12 = icmp ne i32 %d, 0 121 %cmp14 = icmp ult i32 %d, %a 122 %or.cond31 = and i1 %cmp12, %cmp14 123 %b. = select i1 %or.cond31, i32 %b, i32 21 124 ret i32 %b. 125 126 return: ; preds = %if.end6, %if.end, %entry 127 %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ] 128 ret i32 %retval.0 129 } 130 131 define void @testBB() { 132 entry: 133 %0 = load i32, i32* @a, align 4, !tbaa !0 134 %1 = load i32, i32* @b, align 4, !tbaa !0 135 %sub.i = sub i32 %1, %0 136 %tobool = icmp sgt i32 %sub.i, -1 137 br i1 %tobool, label %if.end, label %if.then 138 139 if.then: ; preds = %entry 140 %call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() 141 br label %while.body 142 143 while.body: ; preds = %while.body, %if.then 144 br label %while.body 145 146 if.end: ; preds = %entry 147 %cmp.i = icmp slt i32 %sub.i, 1 148 br i1 %cmp.i, label %if.then4, label %if.end7 149 150 if.then4: ; preds = %if.end 151 %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() 152 br label %while.body6 153 154 while.body6: ; preds = %while.body6, %if.then4 155 br label %while.body6 156 157 if.end7: ; preds = %if.end 158 ret void 159 } 160 161 declare i32 @g(...) 162 163 ; Function Attrs: nounwind 164 declare void @llvm.stackprotector(i8*, i8**) #0 165 166 attributes #0 = { nounwind } 167 168 !0 = !{!1, !1, i64 0} 169 !1 = !{!"int", !2, i64 0} 170 !2 = !{!"omnipotent char", !3, i64 0} 171 !3 = !{!"Simple C/C++ TBAA"} 172 173... 174--- 175name: test0a 176alignment: 2 177exposesReturnsTwice: false 178hasInlineAsm: false 179allVRegsAllocated: false 180isSSA: true 181tracksRegLiveness: true 182tracksSubRegLiveness: false 183registers: 184 - { id: 0, class: gpr } 185 - { id: 1, class: gpr } 186 - { id: 2, class: gpr } 187 - { id: 3, class: gpr } 188 - { id: 4, class: gpr } 189 - { id: 5, class: gpr } 190liveins: 191 - { reg: '%r6', virtual-reg: '%0' } 192 - { reg: '%r7', virtual-reg: '%1' } 193 - { reg: '%r18', virtual-reg: '%2' } 194frameInfo: 195 isFrameAddressTaken: false 196 isReturnAddressTaken: false 197 hasStackMap: false 198 hasPatchPoint: false 199 stackSize: 0 200 offsetAdjustment: 0 201 maxAlignment: 0 202 adjustsStack: false 203 hasCalls: false 204 maxCallFrameSize: 0 205 hasOpaqueSPAdjustment: false 206 hasVAStart: false 207 hasMustTailInVarArgFunc: false 208body: | 209 bb.0.entry: 210 liveins: %r6, %r7, %r18 211 212 %2 = COPY %r18 213 %1 = COPY %r7 214 %0 = COPY %r6 215 %4 = SUB_R %1, %0, 0 216 SFSUB_F_RI_LO %4, 0, implicit-def %sr 217 %5 = SELECT %2, %4, 7, implicit %sr 218 %rv = COPY %5 219 RET implicit %rca, implicit %rv 220 221... 222--- 223name: test0b 224alignment: 2 225exposesReturnsTwice: false 226hasInlineAsm: false 227allVRegsAllocated: false 228isSSA: true 229tracksRegLiveness: true 230tracksSubRegLiveness: false 231registers: 232 - { id: 0, class: gpr } 233 - { id: 1, class: gpr } 234 - { id: 2, class: gpr } 235 - { id: 3, class: gpr } 236 - { id: 4, class: gpr } 237liveins: 238 - { reg: '%r6', virtual-reg: '%0' } 239 - { reg: '%r7', virtual-reg: '%1' } 240 - { reg: '%r18', virtual-reg: '%2' } 241frameInfo: 242 isFrameAddressTaken: false 243 isReturnAddressTaken: false 244 hasStackMap: false 245 hasPatchPoint: false 246 stackSize: 0 247 offsetAdjustment: 0 248 maxAlignment: 0 249 adjustsStack: false 250 hasCalls: false 251 maxCallFrameSize: 0 252 hasOpaqueSPAdjustment: false 253 hasVAStart: false 254 hasMustTailInVarArgFunc: false 255body: | 256 bb.0.entry: 257 liveins: %r6, %r7, %r18 258 259 %2 = COPY %r18 260 %1 = COPY %r7 261 %0 = COPY %r6 262 SFSUB_F_RR %1, %0, implicit-def %sr 263 %4 = SELECT %2, %1, 7, implicit %sr 264 %rv = COPY %4 265 RET implicit %rca, implicit %rv 266 267... 268--- 269name: test1a 270alignment: 2 271exposesReturnsTwice: false 272hasInlineAsm: false 273allVRegsAllocated: false 274isSSA: true 275tracksRegLiveness: true 276tracksSubRegLiveness: false 277registers: 278 - { id: 0, class: gpr } 279 - { id: 1, class: gpr } 280 - { id: 2, class: gpr } 281 - { id: 3, class: gpr } 282 - { id: 4, class: gpr } 283 - { id: 5, class: gpr } 284liveins: 285 - { reg: '%r6', virtual-reg: '%0' } 286 - { reg: '%r7', virtual-reg: '%1' } 287 - { reg: '%r18', virtual-reg: '%2' } 288 - { reg: '%r19', virtual-reg: '%3' } 289frameInfo: 290 isFrameAddressTaken: false 291 isReturnAddressTaken: false 292 hasStackMap: false 293 hasPatchPoint: false 294 stackSize: 0 295 offsetAdjustment: 0 296 maxAlignment: 0 297 adjustsStack: false 298 hasCalls: false 299 maxCallFrameSize: 0 300 hasOpaqueSPAdjustment: false 301 hasVAStart: false 302 hasMustTailInVarArgFunc: false 303body: | 304 bb.0.entry: 305 liveins: %r6, %r7, %r18, %r19 306 307 %3 = COPY %r19 308 %2 = COPY %r18 309 %1 = COPY %r7 310 %0 = COPY %r6 311 %4 = SUB_R %1, %0, 0 312 SFSUB_F_RI_LO killed %4, 0, implicit-def %sr 313 %5 = SELECT %2, %3, 11, implicit %sr 314 %rv = COPY %5 315 RET implicit %rca, implicit %rv 316 317... 318--- 319name: test1b 320alignment: 2 321exposesReturnsTwice: false 322hasInlineAsm: false 323allVRegsAllocated: false 324isSSA: true 325tracksRegLiveness: true 326tracksSubRegLiveness: false 327registers: 328 - { id: 0, class: gpr } 329 - { id: 1, class: gpr } 330 - { id: 2, class: gpr } 331 - { id: 3, class: gpr } 332 - { id: 4, class: gpr } 333 - { id: 5, class: gpr } 334liveins: 335 - { reg: '%r6', virtual-reg: '%0' } 336 - { reg: '%r7', virtual-reg: '%1' } 337 - { reg: '%r18', virtual-reg: '%2' } 338 - { reg: '%r19', virtual-reg: '%3' } 339frameInfo: 340 isFrameAddressTaken: false 341 isReturnAddressTaken: false 342 hasStackMap: false 343 hasPatchPoint: false 344 stackSize: 0 345 offsetAdjustment: 0 346 maxAlignment: 0 347 adjustsStack: false 348 hasCalls: false 349 maxCallFrameSize: 0 350 hasOpaqueSPAdjustment: false 351 hasVAStart: false 352 hasMustTailInVarArgFunc: false 353body: | 354 bb.0.entry: 355 liveins: %r6, %r7, %r18, %r19 356 357 %3 = COPY %r19 358 %2 = COPY %r18 359 %1 = COPY %r7 360 %0 = COPY %r6 361 %4 = SUB_R %1, %0, 0 362 SFSUB_F_RI_LO killed %4, 0, implicit-def %sr 363 %5 = SELECT %2, %3, 11, implicit %sr 364 %rv = COPY %5 365 RET implicit %rca, implicit %rv 366 367... 368--- 369name: test2a 370alignment: 2 371exposesReturnsTwice: false 372hasInlineAsm: false 373allVRegsAllocated: false 374isSSA: true 375tracksRegLiveness: true 376tracksSubRegLiveness: false 377registers: 378 - { id: 0, class: gpr } 379 - { id: 1, class: gpr } 380 - { id: 2, class: gpr } 381 - { id: 3, class: gpr } 382 - { id: 4, class: gpr } 383 - { id: 5, class: gpr } 384liveins: 385 - { reg: '%r6', virtual-reg: '%0' } 386 - { reg: '%r7', virtual-reg: '%1' } 387 - { reg: '%r18', virtual-reg: '%2' } 388 - { reg: '%r19', virtual-reg: '%3' } 389frameInfo: 390 isFrameAddressTaken: false 391 isReturnAddressTaken: false 392 hasStackMap: false 393 hasPatchPoint: false 394 stackSize: 0 395 offsetAdjustment: 0 396 maxAlignment: 0 397 adjustsStack: false 398 hasCalls: false 399 maxCallFrameSize: 0 400 hasOpaqueSPAdjustment: false 401 hasVAStart: false 402 hasMustTailInVarArgFunc: false 403body: | 404 bb.0.entry: 405 liveins: %r6, %r7, %r18, %r19 406 407 %3 = COPY %r19 408 %2 = COPY %r18 409 %1 = COPY %r7 410 %0 = COPY %r6 411 %4 = SUB_R %1, %0, 0 412 SFSUB_F_RI_LO killed %4, 0, implicit-def %sr 413 %5 = SELECT %2, %3, 10, implicit %sr 414 %rv = COPY %5 415 RET implicit %rca, implicit %rv 416 417... 418--- 419name: test2b 420alignment: 2 421exposesReturnsTwice: false 422hasInlineAsm: false 423allVRegsAllocated: false 424isSSA: true 425tracksRegLiveness: true 426tracksSubRegLiveness: false 427registers: 428 - { id: 0, class: gpr } 429 - { id: 1, class: gpr } 430 - { id: 2, class: gpr } 431 - { id: 3, class: gpr } 432 - { id: 4, class: gpr } 433 - { id: 5, class: gpr } 434liveins: 435 - { reg: '%r6', virtual-reg: '%0' } 436 - { reg: '%r7', virtual-reg: '%1' } 437 - { reg: '%r18', virtual-reg: '%2' } 438 - { reg: '%r19', virtual-reg: '%3' } 439frameInfo: 440 isFrameAddressTaken: false 441 isReturnAddressTaken: false 442 hasStackMap: false 443 hasPatchPoint: false 444 stackSize: 0 445 offsetAdjustment: 0 446 maxAlignment: 0 447 adjustsStack: false 448 hasCalls: false 449 maxCallFrameSize: 0 450 hasOpaqueSPAdjustment: false 451 hasVAStart: false 452 hasMustTailInVarArgFunc: false 453body: | 454 bb.0.entry: 455 liveins: %r6, %r7, %r18, %r19 456 457 %3 = COPY %r19 458 %2 = COPY %r18 459 %1 = COPY %r7 460 %0 = COPY %r6 461 %4 = SUB_R %1, %0, 0 462 SFSUB_F_RI_LO killed %4, 0, implicit-def %sr 463 %5 = SELECT %2, %3, 10, implicit %sr 464 %rv = COPY %5 465 RET implicit %rca, implicit %rv 466 467... 468--- 469name: test3 470alignment: 2 471exposesReturnsTwice: false 472hasInlineAsm: false 473allVRegsAllocated: false 474isSSA: true 475tracksRegLiveness: true 476tracksSubRegLiveness: false 477registers: 478 - { id: 0, class: gpr } 479 - { id: 1, class: gpr } 480 - { id: 2, class: gpr } 481 - { id: 3, class: gpr } 482 - { id: 4, class: gpr } 483 - { id: 5, class: gpr } 484liveins: 485 - { reg: '%r6', virtual-reg: '%0' } 486 - { reg: '%r7', virtual-reg: '%1' } 487 - { reg: '%r18', virtual-reg: '%2' } 488 - { reg: '%r19', virtual-reg: '%3' } 489frameInfo: 490 isFrameAddressTaken: false 491 isReturnAddressTaken: false 492 hasStackMap: false 493 hasPatchPoint: false 494 stackSize: 0 495 offsetAdjustment: 0 496 maxAlignment: 0 497 adjustsStack: false 498 hasCalls: false 499 maxCallFrameSize: 0 500 hasOpaqueSPAdjustment: false 501 hasVAStart: false 502 hasMustTailInVarArgFunc: false 503body: | 504 bb.0.entry: 505 liveins: %r6, %r7, %r18, %r19 506 507 %3 = COPY %r19 508 %2 = COPY %r18 509 %1 = COPY %r7 510 %0 = COPY %r6 511 %4 = SUB_R %1, %0, 0 512 SFSUB_F_RI_LO killed %4, 1, implicit-def %sr 513 %5 = SELECT %2, %3, 13, implicit %sr 514 %rv = COPY %5 515 RET implicit %rca, implicit %rv 516 517... 518--- 519name: test4 520alignment: 2 521exposesReturnsTwice: false 522hasInlineAsm: false 523allVRegsAllocated: false 524isSSA: true 525tracksRegLiveness: true 526tracksSubRegLiveness: false 527registers: 528 - { id: 0, class: gpr } 529 - { id: 1, class: gpr } 530 - { id: 2, class: gpr } 531 - { id: 3, class: gpr } 532 - { id: 4, class: gpr } 533 - { id: 5, class: gpr } 534 - { id: 6, class: gpr } 535 - { id: 7, class: gpr } 536 - { id: 8, class: gpr } 537 - { id: 9, class: gpr } 538 - { id: 10, class: gpr } 539 - { id: 11, class: gpr } 540 - { id: 12, class: gpr } 541 - { id: 13, class: gpr } 542 - { id: 14, class: gpr } 543 - { id: 15, class: gpr } 544 - { id: 16, class: gpr } 545 - { id: 17, class: gpr } 546 - { id: 18, class: gpr } 547 - { id: 19, class: gpr } 548 - { id: 20, class: gpr } 549 - { id: 21, class: gpr } 550 - { id: 22, class: gpr } 551liveins: 552 - { reg: '%r6', virtual-reg: '%1' } 553 - { reg: '%r7', virtual-reg: '%2' } 554 - { reg: '%r18', virtual-reg: '%3' } 555 - { reg: '%r19', virtual-reg: '%4' } 556frameInfo: 557 isFrameAddressTaken: false 558 isReturnAddressTaken: false 559 hasStackMap: false 560 hasPatchPoint: false 561 stackSize: 0 562 offsetAdjustment: 0 563 maxAlignment: 0 564 adjustsStack: false 565 hasCalls: false 566 maxCallFrameSize: 0 567 hasOpaqueSPAdjustment: false 568 hasVAStart: false 569 hasMustTailInVarArgFunc: false 570body: | 571 bb.0.entry: 572 successors: %bb.4.return, %bb.1.if.end 573 liveins: %r6, %r7, %r18, %r19 574 575 %4 = COPY %r19 576 %3 = COPY %r18 577 %2 = COPY %r7 578 %1 = COPY %r6 579 SFSUB_F_RI_LO %1, 0, implicit-def %sr 580 %5 = SCC 6, implicit %sr 581 SFSUB_F_RR %1, %2, implicit-def %sr 582 %6 = SCC 4, implicit %sr 583 %7 = AND_R killed %5, killed %6, 0 584 %8 = SLI 1 585 %9 = AND_R killed %7, %8, 0 586 SFSUB_F_RI_LO killed %9, 0, implicit-def %sr 587 BRCC %bb.4.return, 6, implicit %sr 588 BT %bb.1.if.end 589 590 bb.1.if.end: 591 successors: %bb.4.return, %bb.2.if.end6 592 593 SFSUB_F_RI_LO %2, 0, implicit-def %sr 594 %10 = SCC 6, implicit %sr 595 SFSUB_F_RR %2, %3, implicit-def %sr 596 %11 = SCC 4, implicit %sr 597 %12 = AND_R killed %10, killed %11, 0 598 %14 = AND_R killed %12, %8, 0 599 SFSUB_F_RI_LO killed %14, 0, implicit-def %sr 600 BRCC %bb.4.return, 6, implicit %sr 601 BT %bb.2.if.end6 602 603 bb.2.if.end6: 604 successors: %bb.4.return, %bb.3.if.end11 605 606 SFSUB_F_RI_LO %3, 0, implicit-def %sr 607 %15 = SCC 6, implicit %sr 608 SFSUB_F_RR %3, %4, implicit-def %sr 609 %16 = SCC 4, implicit %sr 610 %17 = AND_R killed %15, killed %16, 0 611 %18 = SLI 1 612 %19 = AND_R killed %17, killed %18, 0 613 SFSUB_F_RI_LO killed %19, 0, implicit-def %sr 614 BRCC %bb.4.return, 6, implicit %sr 615 BT %bb.3.if.end11 616 617 bb.3.if.end11: 618 %20 = SLI 21 619 SFSUB_F_RR %4, %1, implicit-def %sr 620 %21 = SELECT %2, %20, 4, implicit %sr 621 SFSUB_F_RI_LO %4, 0, implicit-def %sr 622 %22 = SELECT killed %21, %20, 6, implicit %sr 623 %rv = COPY %22 624 RET implicit %rca, implicit %rv 625 626 bb.4.return: 627 %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6 628 %rv = COPY %0 629 RET implicit %rca, implicit %rv 630 631... 632--- 633name: testBB 634alignment: 2 635exposesReturnsTwice: false 636hasInlineAsm: false 637allVRegsAllocated: false 638isSSA: true 639tracksRegLiveness: true 640tracksSubRegLiveness: false 641registers: 642 - { id: 0, class: gpr } 643 - { id: 1, class: gpr } 644 - { id: 2, class: gpr } 645 - { id: 3, class: gpr } 646 - { id: 4, class: gpr } 647 - { id: 5, class: gpr } 648 - { id: 6, class: gpr } 649 - { id: 7, class: gpr } 650 - { id: 8, class: gpr } 651frameInfo: 652 isFrameAddressTaken: false 653 isReturnAddressTaken: false 654 hasStackMap: false 655 hasPatchPoint: false 656 stackSize: 0 657 offsetAdjustment: 0 658 maxAlignment: 0 659 adjustsStack: false 660 hasCalls: true 661 maxCallFrameSize: 0 662 hasOpaqueSPAdjustment: false 663 hasVAStart: false 664 hasMustTailInVarArgFunc: false 665body: | 666 bb.0.entry: 667 successors: %bb.3.if.end, %bb.1.if.then 668 669 %1 = MOVHI target-flags(lanai-hi) @a 670 %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a 671 %3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0) 672 %4 = MOVHI target-flags(lanai-hi) @b 673 %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b 674 %6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0) 675 %0 = SUB_R killed %6, killed %3, 0 676 SFSUB_F_RI_LO %0, 0, implicit-def %sr 677 BRCC %bb.3.if.end, 10, implicit %sr 678 BT %bb.1.if.then 679 680 bb.1.if.then: 681 successors: %bb.2.while.body 682 683 ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp 684 CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv 685 ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp 686 687 bb.2.while.body: 688 successors: %bb.2.while.body 689 690 BT %bb.2.while.body 691 692 bb.3.if.end: 693 successors: %bb.4.if.then4, %bb.6.if.end7 694 liveins: %sr 695 696 BRCC %bb.6.if.end7, 14, implicit %sr 697 BT %bb.4.if.then4 698 699 bb.4.if.then4: 700 successors: %bb.5.while.body6 701 702 ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp 703 CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv 704 ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp 705 706 bb.5.while.body6: 707 successors: %bb.5.while.body6 708 709 BT %bb.5.while.body6 710 711 bb.6.if.end7: 712 RET implicit %rca 713 714... 715