1; RUN: llc < %s -mtriple=powerpc-apple-darwin8
2
3define void @gcov_exit() nounwind {
4entry:
5  br i1 undef, label %return, label %bb.nph341
6
7bb.nph341:                                        ; preds = %entry
8  br label %bb25
9
10bb25:                                             ; preds = %read_fatal, %bb.nph341
11  br i1 undef, label %bb49.1, label %bb48
12
13bb48:                                             ; preds = %bb25
14  br label %bb49.1
15
16bb51:                                             ; preds = %bb48.4, %bb49.3
17  switch i32 undef, label %bb58 [
18    i32 0, label %rewrite
19    i32 1734567009, label %bb59
20  ]
21
22bb58:                                             ; preds = %bb51
23  br label %read_fatal
24
25bb59:                                             ; preds = %bb51
26  br i1 undef, label %bb60, label %bb3.i156
27
28bb3.i156:                                         ; preds = %bb59
29  br label %read_fatal
30
31bb60:                                             ; preds = %bb59
32  br i1 undef, label %bb78.preheader, label %rewrite
33
34bb78.preheader:                                   ; preds = %bb60
35  br i1 undef, label %bb62, label %bb80
36
37bb62:                                             ; preds = %bb78.preheader
38  br i1 undef, label %bb64, label %read_mismatch
39
40bb64:                                             ; preds = %bb62
41  br i1 undef, label %bb65, label %read_mismatch
42
43bb65:                                             ; preds = %bb64
44  br i1 undef, label %bb75, label %read_mismatch
45
46read_mismatch:                                    ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62
47  br label %read_fatal
48
49bb71:                                             ; preds = %bb75
50  br i1 undef, label %bb72, label %read_mismatch
51
52bb72:                                             ; preds = %bb71
53  br i1 undef, label %bb73, label %read_mismatch
54
55bb73:                                             ; preds = %bb72
56  unreachable
57
58bb74:                                             ; preds = %bb75
59  br label %bb75
60
61bb75:                                             ; preds = %bb74, %bb65
62  br i1 undef, label %bb74, label %bb71
63
64bb80:                                             ; preds = %bb78.preheader
65  unreachable
66
67read_fatal:                                       ; preds = %read_mismatch, %bb3.i156, %bb58
68  br i1 undef, label %return, label %bb25
69
70rewrite:                                          ; preds = %bb60, %bb51
71  br i1 undef, label %bb94, label %bb119.preheader
72
73bb94:                                             ; preds = %rewrite
74  unreachable
75
76bb119.preheader:                                  ; preds = %rewrite
77  br i1 undef, label %read_mismatch, label %bb98
78
79bb98:                                             ; preds = %bb119.preheader
80  br label %read_mismatch
81
82return:                                           ; preds = %read_fatal, %entry
83  ret void
84
85bb49.1:                                           ; preds = %bb48, %bb25
86  br i1 undef, label %bb49.2, label %bb48.2
87
88bb49.2:                                           ; preds = %bb48.2, %bb49.1
89  br i1 undef, label %bb49.3, label %bb48.3
90
91bb48.2:                                           ; preds = %bb49.1
92  br label %bb49.2
93
94bb49.3:                                           ; preds = %bb48.3, %bb49.2
95  %c_ix.0.3 = phi i32 [ undef, %bb48.3 ], [ undef, %bb49.2 ] ; <i32> [#uses=1]
96  br i1 undef, label %bb51, label %bb48.4
97
98bb48.3:                                           ; preds = %bb49.2
99  store i64* undef, i64** undef, align 4
100  br label %bb49.3
101
102bb48.4:                                           ; preds = %bb49.3
103  %0 = getelementptr inbounds [5 x i64*], [5 x i64*]* undef, i32 0, i32 %c_ix.0.3 ; <i64**> [#uses=0]
104  br label %bb51
105}
106