1; Test vector addition.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test a v16i8 addition.
6define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
7; CHECK-LABEL: f1:
8; CHECK: vab %v24, %v26, %v28
9; CHECK: br %r14
10  %ret = add <16 x i8> %val1, %val2
11  ret <16 x i8> %ret
12}
13
14; Test a v8i16 addition.
15define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
16; CHECK-LABEL: f2:
17; CHECK: vah %v24, %v26, %v28
18; CHECK: br %r14
19  %ret = add <8 x i16> %val1, %val2
20  ret <8 x i16> %ret
21}
22
23; Test a v4i32 addition.
24define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
25; CHECK-LABEL: f3:
26; CHECK: vaf %v24, %v26, %v28
27; CHECK: br %r14
28  %ret = add <4 x i32> %val1, %val2
29  ret <4 x i32> %ret
30}
31
32; Test a v2i64 addition.
33define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
34; CHECK-LABEL: f4:
35; CHECK: vag %v24, %v26, %v28
36; CHECK: br %r14
37  %ret = add <2 x i64> %val1, %val2
38  ret <2 x i64> %ret
39}
40
41; Test a v2f64 addition.
42define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
43                        <2 x double> %val2) {
44; CHECK-LABEL: f5:
45; CHECK: vfadb %v24, %v26, %v28
46; CHECK: br %r14
47  %ret = fadd <2 x double> %val1, %val2
48  ret <2 x double> %ret
49}
50
51; Test an f64 addition that uses vector registers.
52define double @f6(<2 x double> %val1, <2 x double> %val2) {
53; CHECK-LABEL: f6:
54; CHECK: wfadb %f0, %v24, %v26
55; CHECK: br %r14
56  %scalar1 = extractelement <2 x double> %val1, i32 0
57  %scalar2 = extractelement <2 x double> %val2, i32 0
58  %ret = fadd double %scalar1, %scalar2
59  ret double %ret
60}
61