1; Test v4i32 comparisons.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test eq.
6define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
7; CHECK-LABEL: f1:
8; CHECK: vceqf %v24, %v26, %v28
9; CHECK-NEXT: br %r14
10  %cmp = icmp eq <4 x i32> %val1, %val2
11  %ret = sext <4 x i1> %cmp to <4 x i32>
12  ret <4 x i32> %ret
13}
14
15; Test ne.
16define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
17; CHECK-LABEL: f2:
18; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
19; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
20; CHECK-NEXT: br %r14
21  %cmp = icmp ne <4 x i32> %val1, %val2
22  %ret = sext <4 x i1> %cmp to <4 x i32>
23  ret <4 x i32> %ret
24}
25
26; Test sgt.
27define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
28; CHECK-LABEL: f3:
29; CHECK: vchf %v24, %v26, %v28
30; CHECK-NEXT: br %r14
31  %cmp = icmp sgt <4 x i32> %val1, %val2
32  %ret = sext <4 x i1> %cmp to <4 x i32>
33  ret <4 x i32> %ret
34}
35
36; Test sge.
37define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
38; CHECK-LABEL: f4:
39; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
40; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
41; CHECK-NEXT: br %r14
42  %cmp = icmp sge <4 x i32> %val1, %val2
43  %ret = sext <4 x i1> %cmp to <4 x i32>
44  ret <4 x i32> %ret
45}
46
47; Test sle.
48define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
49; CHECK-LABEL: f5:
50; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
51; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
52; CHECK-NEXT: br %r14
53  %cmp = icmp sle <4 x i32> %val1, %val2
54  %ret = sext <4 x i1> %cmp to <4 x i32>
55  ret <4 x i32> %ret
56}
57
58; Test slt.
59define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
60; CHECK-LABEL: f6:
61; CHECK: vchf %v24, %v28, %v26
62; CHECK-NEXT: br %r14
63  %cmp = icmp slt <4 x i32> %val1, %val2
64  %ret = sext <4 x i1> %cmp to <4 x i32>
65  ret <4 x i32> %ret
66}
67
68; Test ugt.
69define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
70; CHECK-LABEL: f7:
71; CHECK: vchlf %v24, %v26, %v28
72; CHECK-NEXT: br %r14
73  %cmp = icmp ugt <4 x i32> %val1, %val2
74  %ret = sext <4 x i1> %cmp to <4 x i32>
75  ret <4 x i32> %ret
76}
77
78; Test uge.
79define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
80; CHECK-LABEL: f8:
81; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
82; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
83; CHECK-NEXT: br %r14
84  %cmp = icmp uge <4 x i32> %val1, %val2
85  %ret = sext <4 x i1> %cmp to <4 x i32>
86  ret <4 x i32> %ret
87}
88
89; Test ule.
90define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
91; CHECK-LABEL: f9:
92; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
93; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
94; CHECK-NEXT: br %r14
95  %cmp = icmp ule <4 x i32> %val1, %val2
96  %ret = sext <4 x i1> %cmp to <4 x i32>
97  ret <4 x i32> %ret
98}
99
100; Test ult.
101define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
102; CHECK-LABEL: f10:
103; CHECK: vchlf %v24, %v28, %v26
104; CHECK-NEXT: br %r14
105  %cmp = icmp ult <4 x i32> %val1, %val2
106  %ret = sext <4 x i1> %cmp to <4 x i32>
107  ret <4 x i32> %ret
108}
109
110; Test eq selects.
111define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2,
112                      <4 x i32> %val3, <4 x i32> %val4) {
113; CHECK-LABEL: f11:
114; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
115; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
116; CHECK-NEXT: br %r14
117  %cmp = icmp eq <4 x i32> %val1, %val2
118  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
119  ret <4 x i32> %ret
120}
121
122; Test ne selects.
123define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2,
124                      <4 x i32> %val3, <4 x i32> %val4) {
125; CHECK-LABEL: f12:
126; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
127; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
128; CHECK-NEXT: br %r14
129  %cmp = icmp ne <4 x i32> %val1, %val2
130  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
131  ret <4 x i32> %ret
132}
133
134; Test sgt selects.
135define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2,
136                      <4 x i32> %val3, <4 x i32> %val4) {
137; CHECK-LABEL: f13:
138; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
139; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
140; CHECK-NEXT: br %r14
141  %cmp = icmp sgt <4 x i32> %val1, %val2
142  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
143  ret <4 x i32> %ret
144}
145
146; Test sge selects.
147define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2,
148                      <4 x i32> %val3, <4 x i32> %val4) {
149; CHECK-LABEL: f14:
150; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
151; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
152; CHECK-NEXT: br %r14
153  %cmp = icmp sge <4 x i32> %val1, %val2
154  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
155  ret <4 x i32> %ret
156}
157
158; Test sle selects.
159define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2,
160                      <4 x i32> %val3, <4 x i32> %val4) {
161; CHECK-LABEL: f15:
162; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
163; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
164; CHECK-NEXT: br %r14
165  %cmp = icmp sle <4 x i32> %val1, %val2
166  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
167  ret <4 x i32> %ret
168}
169
170; Test slt selects.
171define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2,
172                      <4 x i32> %val3, <4 x i32> %val4) {
173; CHECK-LABEL: f16:
174; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
175; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
176; CHECK-NEXT: br %r14
177  %cmp = icmp slt <4 x i32> %val1, %val2
178  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
179  ret <4 x i32> %ret
180}
181
182; Test ugt selects.
183define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2,
184                      <4 x i32> %val3, <4 x i32> %val4) {
185; CHECK-LABEL: f17:
186; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
187; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
188; CHECK-NEXT: br %r14
189  %cmp = icmp ugt <4 x i32> %val1, %val2
190  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
191  ret <4 x i32> %ret
192}
193
194; Test uge selects.
195define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2,
196                      <4 x i32> %val3, <4 x i32> %val4) {
197; CHECK-LABEL: f18:
198; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
199; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
200; CHECK-NEXT: br %r14
201  %cmp = icmp uge <4 x i32> %val1, %val2
202  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
203  ret <4 x i32> %ret
204}
205
206; Test ule selects.
207define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2,
208                      <4 x i32> %val3, <4 x i32> %val4) {
209; CHECK-LABEL: f19:
210; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
211; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
212; CHECK-NEXT: br %r14
213  %cmp = icmp ule <4 x i32> %val1, %val2
214  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
215  ret <4 x i32> %ret
216}
217
218; Test ult selects.
219define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2,
220                      <4 x i32> %val3, <4 x i32> %val4) {
221; CHECK-LABEL: f20:
222; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
223; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
224; CHECK-NEXT: br %r14
225  %cmp = icmp ult <4 x i32> %val1, %val2
226  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
227  ret <4 x i32> %ret
228}
229