1; Test vector division.  There is no native integer support for this,
2; so the integer cases are really a test of the operation legalization code.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5
6; Test a v16i8 division.
7define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
8; CHECK-LABEL: f1:
9; CHECK: vlvgp [[REG:%v[0-9]+]],
10; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
11; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
12; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
13; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
14; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
15; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
16; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
17; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
18; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
19; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10
20; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11
21; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12
22; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13
23; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14
24; CHECK: br %r14
25  %ret = sdiv <16 x i8> %val1, %val2
26  ret <16 x i8> %ret
27}
28
29; Test a v8i16 division.
30define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
31; CHECK-LABEL: f2:
32; CHECK: vlvgp [[REG:%v[0-9]+]],
33; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0
34; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1
35; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2
36; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4
37; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5
38; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6
39; CHECK: br %r14
40  %ret = sdiv <8 x i16> %val1, %val2
41  ret <8 x i16> %ret
42}
43
44; Test a v4i32 division.
45define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
46; CHECK-LABEL: f3:
47; CHECK: vlvgp [[REG:%v[0-9]+]],
48; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0
49; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2
50; CHECK: br %r14
51  %ret = sdiv <4 x i32> %val1, %val2
52  ret <4 x i32> %ret
53}
54
55; Test a v2i64 division.
56define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
57; CHECK-LABEL: f4:
58; CHECK: vlvgp %v24,
59; CHECK: br %r14
60  %ret = sdiv <2 x i64> %val1, %val2
61  ret <2 x i64> %ret
62}
63
64; Test a v2f64 division.
65define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
66                        <2 x double> %val2) {
67; CHECK-LABEL: f5:
68; CHECK: vfddb %v24, %v26, %v28
69; CHECK: br %r14
70  %ret = fdiv <2 x double> %val1, %val2
71  ret <2 x double> %ret
72}
73
74; Test an f64 division that uses vector registers.
75define double @f6(<2 x double> %val1, <2 x double> %val2) {
76; CHECK-LABEL: f6:
77; CHECK: wfddb %f0, %v24, %v26
78; CHECK: br %r14
79  %scalar1 = extractelement <2 x double> %val1, i32 0
80  %scalar2 = extractelement <2 x double> %val2, i32 0
81  %ret = fdiv double %scalar1, %scalar2
82  ret double %ret
83}
84