1; Test scalar_to_vector expansion.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test v16i8.
6define <16 x i8> @f1(i8 %val) {
7; CHECK-LABEL: f1:
8; CHECK: vlvgb %v24, %r2, 0
9; CHECK: br %r14
10  %ret = insertelement <16 x i8> undef, i8 %val, i32 0
11  ret <16 x i8> %ret
12}
13
14; Test v8i16.
15define <8 x i16> @f2(i16 %val) {
16; CHECK-LABEL: f2:
17; CHECK: vlvgh %v24, %r2, 0
18; CHECK: br %r14
19  %ret = insertelement <8 x i16> undef, i16 %val, i32 0
20  ret <8 x i16> %ret
21}
22
23; Test v4i32.
24define <4 x i32> @f3(i32 %val) {
25; CHECK-LABEL: f3:
26; CHECK: vlvgf %v24, %r2, 0
27; CHECK: br %r14
28  %ret = insertelement <4 x i32> undef, i32 %val, i32 0
29  ret <4 x i32> %ret
30}
31
32; Test v2i64.  Here we load %val into both halves.
33define <2 x i64> @f4(i64 %val) {
34; CHECK-LABEL: f4:
35; CHECK: vlvgp %v24, %r2, %r2
36; CHECK: br %r14
37  %ret = insertelement <2 x i64> undef, i64 %val, i32 0
38  ret <2 x i64> %ret
39}
40
41; Test v4f32, which is just a move.
42define <4 x float> @f5(float %val) {
43; CHECK-LABEL: f5:
44; CHECK: vlr %v24, %v0
45; CHECK: br %r14
46  %ret = insertelement <4 x float> undef, float %val, i32 0
47  ret <4 x float> %ret
48}
49
50; Likewise v2f64.
51define <2 x double> @f6(double %val) {
52; CHECK-LABEL: f6:
53; CHECK: vlr %v24, %v0
54; CHECK: br %r14
55  %ret = insertelement <2 x double> undef, double %val, i32 0
56  ret <2 x double> %ret
57}
58