1; Test vector sign extensions.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test a v16i1->v16i8 extension.
6define <16 x i8> @f1(<16 x i8> %val) {
7; CHECK-LABEL: f1:
8; CHECK: veslb [[REG:%v[0-9]+]], %v24, 7
9; CHECK: vesrab %v24, [[REG]], 7
10; CHECK: br %r14
11  %trunc = trunc <16 x i8> %val to <16 x i1>
12  %ret = sext <16 x i1> %trunc to <16 x i8>
13  ret <16 x i8> %ret
14}
15
16; Test a v8i1->v8i16 extension.
17define <8 x i16> @f2(<8 x i16> %val) {
18; CHECK-LABEL: f2:
19; CHECK: veslh [[REG:%v[0-9]+]], %v24, 15
20; CHECK: vesrah %v24, [[REG]], 15
21; CHECK: br %r14
22  %trunc = trunc <8 x i16> %val to <8 x i1>
23  %ret = sext <8 x i1> %trunc to <8 x i16>
24  ret <8 x i16> %ret
25}
26
27; Test a v8i8->v8i16 extension.
28define <8 x i16> @f3(<8 x i16> %val) {
29; CHECK-LABEL: f3:
30; CHECK: veslh [[REG:%v[0-9]+]], %v24, 8
31; CHECK: vesrah %v24, [[REG]], 8
32; CHECK: br %r14
33  %trunc = trunc <8 x i16> %val to <8 x i8>
34  %ret = sext <8 x i8> %trunc to <8 x i16>
35  ret <8 x i16> %ret
36}
37
38; Test a v4i1->v4i32 extension.
39define <4 x i32> @f4(<4 x i32> %val) {
40; CHECK-LABEL: f4:
41; CHECK: veslf [[REG:%v[0-9]+]], %v24, 31
42; CHECK: vesraf %v24, [[REG]], 31
43; CHECK: br %r14
44  %trunc = trunc <4 x i32> %val to <4 x i1>
45  %ret = sext <4 x i1> %trunc to <4 x i32>
46  ret <4 x i32> %ret
47}
48
49; Test a v4i8->v4i32 extension.
50define <4 x i32> @f5(<4 x i32> %val) {
51; CHECK-LABEL: f5:
52; CHECK: veslf [[REG:%v[0-9]+]], %v24, 24
53; CHECK: vesraf %v24, [[REG]], 24
54; CHECK: br %r14
55  %trunc = trunc <4 x i32> %val to <4 x i8>
56  %ret = sext <4 x i8> %trunc to <4 x i32>
57  ret <4 x i32> %ret
58}
59
60; Test a v4i16->v4i32 extension.
61define <4 x i32> @f6(<4 x i32> %val) {
62; CHECK-LABEL: f6:
63; CHECK: veslf [[REG:%v[0-9]+]], %v24, 16
64; CHECK: vesraf %v24, [[REG]], 16
65; CHECK: br %r14
66  %trunc = trunc <4 x i32> %val to <4 x i16>
67  %ret = sext <4 x i16> %trunc to <4 x i32>
68  ret <4 x i32> %ret
69}
70
71; Test a v2i1->v2i64 extension.
72define <2 x i64> @f7(<2 x i64> %val) {
73; CHECK-LABEL: f7:
74; CHECK: veslg [[REG:%v[0-9]+]], %v24, 63
75; CHECK: vesrag %v24, [[REG]], 63
76; CHECK: br %r14
77  %trunc = trunc <2 x i64> %val to <2 x i1>
78  %ret = sext <2 x i1> %trunc to <2 x i64>
79  ret <2 x i64> %ret
80}
81
82; Test a v2i8->v2i64 extension.
83define <2 x i64> @f8(<2 x i64> %val) {
84; CHECK-LABEL: f8:
85; CHECK: vsegb %v24, %v24
86; CHECK: br %r14
87  %trunc = trunc <2 x i64> %val to <2 x i8>
88  %ret = sext <2 x i8> %trunc to <2 x i64>
89  ret <2 x i64> %ret
90}
91
92; Test a v2i16->v2i64 extension.
93define <2 x i64> @f9(<2 x i64> %val) {
94; CHECK-LABEL: f9:
95; CHECK: vsegh %v24, %v24
96; CHECK: br %r14
97  %trunc = trunc <2 x i64> %val to <2 x i16>
98  %ret = sext <2 x i16> %trunc to <2 x i64>
99  ret <2 x i64> %ret
100}
101
102; Test a v2i32->v2i64 extension.
103define <2 x i64> @f10(<2 x i64> %val) {
104; CHECK-LABEL: f10:
105; CHECK: vsegf %v24, %v24
106; CHECK: br %r14
107  %trunc = trunc <2 x i64> %val to <2 x i32>
108  %ret = sext <2 x i32> %trunc to <2 x i64>
109  ret <2 x i64> %ret
110}
111
112; Test an alternative v2i8->v2i64 extension.
113define <2 x i64> @f11(<2 x i64> %val) {
114; CHECK-LABEL: f11:
115; CHECK: vsegb %v24, %v24
116; CHECK: br %r14
117  %shl = shl <2 x i64> %val, <i64 56, i64 56>
118  %ret = ashr <2 x i64> %shl, <i64 56, i64 56>
119  ret <2 x i64> %ret
120}
121
122; Test an alternative v2i16->v2i64 extension.
123define <2 x i64> @f12(<2 x i64> %val) {
124; CHECK-LABEL: f12:
125; CHECK: vsegh %v24, %v24
126; CHECK: br %r14
127  %shl = shl <2 x i64> %val, <i64 48, i64 48>
128  %ret = ashr <2 x i64> %shl, <i64 48, i64 48>
129  ret <2 x i64> %ret
130}
131
132; Test an alternative v2i32->v2i64 extension.
133define <2 x i64> @f13(<2 x i64> %val) {
134; CHECK-LABEL: f13:
135; CHECK: vsegf %v24, %v24
136; CHECK: br %r14
137  %shl = shl <2 x i64> %val, <i64 32, i64 32>
138  %ret = ashr <2 x i64> %shl, <i64 32, i64 32>
139  ret <2 x i64> %ret
140}
141
142; Test an extraction-based v2i8->v2i64 extension.
143define <2 x i64> @f14(<16 x i8> %val) {
144; CHECK-LABEL: f14:
145; CHECK: vsegb %v24, %v24
146; CHECK: br %r14
147  %elt0 = extractelement <16 x i8> %val, i32 7
148  %elt1 = extractelement <16 x i8> %val, i32 15
149  %ext0 = sext i8 %elt0 to i64
150  %ext1 = sext i8 %elt1 to i64
151  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
152  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
153  ret <2 x i64> %vec1
154}
155
156; Test an extraction-based v2i16->v2i64 extension.
157define <2 x i64> @f15(<16 x i16> %val) {
158; CHECK-LABEL: f15:
159; CHECK: vsegh %v24, %v24
160; CHECK: br %r14
161  %elt0 = extractelement <16 x i16> %val, i32 3
162  %elt1 = extractelement <16 x i16> %val, i32 7
163  %ext0 = sext i16 %elt0 to i64
164  %ext1 = sext i16 %elt1 to i64
165  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
166  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
167  ret <2 x i64> %vec1
168}
169
170; Test an extraction-based v2i32->v2i64 extension.
171define <2 x i64> @f16(<16 x i32> %val) {
172; CHECK-LABEL: f16:
173; CHECK: vsegf %v24, %v24
174; CHECK: br %r14
175  %elt0 = extractelement <16 x i32> %val, i32 1
176  %elt1 = extractelement <16 x i32> %val, i32 3
177  %ext0 = sext i32 %elt0 to i64
178  %ext1 = sext i32 %elt1 to i64
179  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
180  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
181  ret <2 x i64> %vec1
182}
183