1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64
3
4; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c
5
6;
7; AMD Intrinsics
8;
9
10define i64 @test__andn_u64(i64 %a0, i64 %a1) {
11; X64-LABEL: test__andn_u64:
12; X64:       # BB#0:
13; X64-NEXT:    xorq $-1, %rdi
14; X64-NEXT:    andq %rsi, %rdi
15; X64-NEXT:    movq %rdi, %rax
16; X64-NEXT:    retq
17  %xor = xor i64 %a0, -1
18  %res = and i64 %xor, %a1
19  ret i64 %res
20}
21
22define i64 @test__bextr_u64(i64 %a0, i64 %a1) {
23; X64-LABEL: test__bextr_u64:
24; X64:       # BB#0:
25; X64-NEXT:    bextrq %rsi, %rdi, %rax
26; X64-NEXT:    retq
27  %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %a1)
28  ret i64 %res
29}
30
31define i64 @test__blsi_u64(i64 %a0) {
32; X64-LABEL: test__blsi_u64:
33; X64:       # BB#0:
34; X64-NEXT:    xorl %eax, %eax
35; X64-NEXT:    subq %rdi, %rax
36; X64-NEXT:    andq %rdi, %rax
37; X64-NEXT:    retq
38  %neg = sub i64 0, %a0
39  %res = and i64 %a0, %neg
40  ret i64 %res
41}
42
43define i64 @test__blsmsk_u64(i64 %a0) {
44; X64-LABEL: test__blsmsk_u64:
45; X64:       # BB#0:
46; X64-NEXT:    movq %rdi, %rax
47; X64-NEXT:    subq $1, %rax
48; X64-NEXT:    xorq %rdi, %rax
49; X64-NEXT:    retq
50  %dec = sub i64 %a0, 1
51  %res = xor i64 %a0, %dec
52  ret i64 %res
53}
54
55define i64 @test__blsr_u64(i64 %a0) {
56; X64-LABEL: test__blsr_u64:
57; X64:       # BB#0:
58; X64-NEXT:    movq %rdi, %rax
59; X64-NEXT:    subq $1, %rax
60; X64-NEXT:    andq %rdi, %rax
61; X64-NEXT:    retq
62  %dec = sub i64 %a0, 1
63  %res = and i64 %a0, %dec
64  ret i64 %res
65}
66
67define i64 @test__tzcnt_u64(i64 %a0) {
68; X64-LABEL: test__tzcnt_u64:
69; X64:       # BB#0:
70; X64-NEXT:    movl $64, %ecx
71; X64-NEXT:    tzcntq %rdi, %rax
72; X64-NEXT:    cmovbq %rcx, %rax
73; X64-NEXT:    retq
74  %cmp = icmp ne i64 %a0, 0
75  %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
76  %res = select i1 %cmp, i64 %cttz, i64 64
77  ret i64 %res
78}
79
80;
81; Intel intrinsics
82;
83
84define i64 @test_andn_u64(i64 %a0, i64 %a1) {
85; X64-LABEL: test_andn_u64:
86; X64:       # BB#0:
87; X64-NEXT:    xorq $-1, %rdi
88; X64-NEXT:    andq %rsi, %rdi
89; X64-NEXT:    movq %rdi, %rax
90; X64-NEXT:    retq
91  %xor = xor i64 %a0, -1
92  %res = and i64 %xor, %a1
93  ret i64 %res
94}
95
96define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) {
97; X64-LABEL: test_bextr_u64:
98; X64:       # BB#0:
99; X64-NEXT:    andl $255, %esi
100; X64-NEXT:    andl $255, %edx
101; X64-NEXT:    shll $8, %edx
102; X64-NEXT:    orl %esi, %edx
103; X64-NEXT:    movl %edx, %eax
104; X64-NEXT:    bextrq %rax, %rdi, %rax
105; X64-NEXT:    retq
106  %and1 = and i32 %a1, 255
107  %and2 = and i32 %a2, 255
108  %shl = shl i32 %and2, 8
109  %or = or i32 %and1, %shl
110  %zext = zext i32 %or to i64
111  %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %zext)
112  ret i64 %res
113}
114
115define i64 @test_blsi_u64(i64 %a0) {
116; X64-LABEL: test_blsi_u64:
117; X64:       # BB#0:
118; X64-NEXT:    xorl %eax, %eax
119; X64-NEXT:    subq %rdi, %rax
120; X64-NEXT:    andq %rdi, %rax
121; X64-NEXT:    retq
122  %neg = sub i64 0, %a0
123  %res = and i64 %a0, %neg
124  ret i64 %res
125}
126
127define i64 @test_blsmsk_u64(i64 %a0) {
128; X64-LABEL: test_blsmsk_u64:
129; X64:       # BB#0:
130; X64-NEXT:    movq %rdi, %rax
131; X64-NEXT:    subq $1, %rax
132; X64-NEXT:    xorq %rdi, %rax
133; X64-NEXT:    retq
134  %dec = sub i64 %a0, 1
135  %res = xor i64 %a0, %dec
136  ret i64 %res
137}
138
139define i64 @test_blsr_u64(i64 %a0) {
140; X64-LABEL: test_blsr_u64:
141; X64:       # BB#0:
142; X64-NEXT:    movq %rdi, %rax
143; X64-NEXT:    subq $1, %rax
144; X64-NEXT:    andq %rdi, %rax
145; X64-NEXT:    retq
146  %dec = sub i64 %a0, 1
147  %res = and i64 %a0, %dec
148  ret i64 %res
149}
150
151define i64 @test_tzcnt_u64(i64 %a0) {
152; X64-LABEL: test_tzcnt_u64:
153; X64:       # BB#0:
154; X64-NEXT:    movl $64, %ecx
155; X64-NEXT:    tzcntq %rdi, %rax
156; X64-NEXT:    cmovbq %rcx, %rax
157; X64-NEXT:    retq
158  %cmp = icmp ne i64 %a0, 0
159  %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
160  %res = select i1 %cmp, i64 %cttz, i64 64
161  ret i64 %res
162}
163
164declare i64 @llvm.cttz.i64(i64, i1)
165declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
166