1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx -mattr=+avx | FileCheck %s
3
4; Verify that the backend correctly folds a sign/zero extend of a vector where
5; elements are all constant values or UNDEFs.
6; The backend should be able to optimize all the test functions below into
7; simple loads from constant pool of the result. That is because the resulting
8; vector should be known at static time.
9
10define <4 x i16> @test1() {
11; CHECK-LABEL: test1:
12; CHECK:       # BB#0:
13; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
14; CHECK-NEXT:    retq
15  %1 = insertelement <4 x i8> undef, i8 0, i32 0
16  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
17  %3 = insertelement <4 x i8> %2, i8 2, i32 2
18  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
19  %5 = sext <4 x i8> %4 to <4 x i16>
20  ret <4 x i16> %5
21}
22
23define <4 x i16> @test2() {
24; CHECK-LABEL: test2:
25; CHECK:       # BB#0:
26; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
27; CHECK-NEXT:    retq
28  %1 = insertelement <4 x i8> undef, i8 undef, i32 0
29  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
30  %3 = insertelement <4 x i8> %2, i8 undef, i32 2
31  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
32  %5 = sext <4 x i8> %4 to <4 x i16>
33  ret <4 x i16> %5
34}
35
36define <4 x i32> @test3() {
37; CHECK-LABEL: test3:
38; CHECK:       # BB#0:
39; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
40; CHECK-NEXT:    retq
41  %1 = insertelement <4 x i8> undef, i8 0, i32 0
42  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
43  %3 = insertelement <4 x i8> %2, i8 2, i32 2
44  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
45  %5 = sext <4 x i8> %4 to <4 x i32>
46  ret <4 x i32> %5
47}
48
49define <4 x i32> @test4() {
50; CHECK-LABEL: test4:
51; CHECK:       # BB#0:
52; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
53; CHECK-NEXT:    retq
54  %1 = insertelement <4 x i8> undef, i8 undef, i32 0
55  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
56  %3 = insertelement <4 x i8> %2, i8 undef, i32 2
57  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
58  %5 = sext <4 x i8> %4 to <4 x i32>
59  ret <4 x i32> %5
60}
61
62define <4 x i64> @test5() {
63; CHECK-LABEL: test5:
64; CHECK:       # BB#0:
65; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [0,18446744073709551615,2,18446744073709551613]
66; CHECK-NEXT:    retq
67  %1 = insertelement <4 x i8> undef, i8 0, i32 0
68  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
69  %3 = insertelement <4 x i8> %2, i8 2, i32 2
70  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
71  %5 = sext <4 x i8> %4 to <4 x i64>
72  ret <4 x i64> %5
73}
74
75define <4 x i64> @test6() {
76; CHECK-LABEL: test6:
77; CHECK:       # BB#0:
78; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = <u,18446744073709551615,u,18446744073709551613>
79; CHECK-NEXT:    retq
80  %1 = insertelement <4 x i8> undef, i8 undef, i32 0
81  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
82  %3 = insertelement <4 x i8> %2, i8 undef, i32 2
83  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
84  %5 = sext <4 x i8> %4 to <4 x i64>
85  ret <4 x i64> %5
86}
87
88define <8 x i16> @test7() {
89; CHECK-LABEL: test7:
90; CHECK:       # BB#0:
91; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <0,65535,2,65533,u,u,u,u>
92; CHECK-NEXT:    retq
93  %1 = insertelement <8 x i8> undef, i8 0, i32 0
94  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
95  %3 = insertelement <8 x i8> %2, i8 2, i32 2
96  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
97  %5 = insertelement <8 x i8> %4, i8 4, i32 4
98  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
99  %7 = insertelement <8 x i8> %6, i8 6, i32 6
100  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
101  %9 = sext <8 x i8> %4 to <8 x i16>
102  ret <8 x i16> %9
103}
104
105define <8 x i32> @test8() {
106; CHECK-LABEL: test8:
107; CHECK:       # BB#0:
108; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = <0,4294967295,2,4294967293,u,u,u,u>
109; CHECK-NEXT:    retq
110  %1 = insertelement <8 x i8> undef, i8 0, i32 0
111  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
112  %3 = insertelement <8 x i8> %2, i8 2, i32 2
113  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
114  %5 = insertelement <8 x i8> %4, i8 4, i32 4
115  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
116  %7 = insertelement <8 x i8> %6, i8 6, i32 6
117  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
118  %9 = sext <8 x i8> %4 to <8 x i32>
119  ret <8 x i32> %9
120}
121
122define <8 x i16> @test9() {
123; CHECK-LABEL: test9:
124; CHECK:       # BB#0:
125; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <u,65535,u,65533,u,u,u,u>
126; CHECK-NEXT:    retq
127  %1 = insertelement <8 x i8> undef, i8 undef, i32 0
128  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
129  %3 = insertelement <8 x i8> %2, i8 undef, i32 2
130  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
131  %5 = insertelement <8 x i8> %4, i8 undef, i32 4
132  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
133  %7 = insertelement <8 x i8> %6, i8 undef, i32 6
134  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
135  %9 = sext <8 x i8> %4 to <8 x i16>
136  ret <8 x i16> %9
137}
138
139define <8 x i32> @test10() {
140; CHECK-LABEL: test10:
141; CHECK:       # BB#0:
142; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = <0,u,2,u,u,u,u,u>
143; CHECK-NEXT:    retq
144  %1 = insertelement <8 x i8> undef, i8 0, i32 0
145  %2 = insertelement <8 x i8> %1, i8 undef, i32 1
146  %3 = insertelement <8 x i8> %2, i8 2, i32 2
147  %4 = insertelement <8 x i8> %3, i8 undef, i32 3
148  %5 = insertelement <8 x i8> %4, i8 4, i32 4
149  %6 = insertelement <8 x i8> %5, i8 undef, i32 5
150  %7 = insertelement <8 x i8> %6, i8 6, i32 6
151  %8 = insertelement <8 x i8> %7, i8 undef, i32 7
152  %9 = sext <8 x i8> %4 to <8 x i32>
153  ret <8 x i32> %9
154}
155
156define <4 x i16> @test11() {
157; CHECK-LABEL: test11:
158; CHECK:       # BB#0:
159; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,255,2,253]
160; CHECK-NEXT:    retq
161  %1 = insertelement <4 x i8> undef, i8 0, i32 0
162  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
163  %3 = insertelement <4 x i8> %2, i8 2, i32 2
164  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
165  %5 = zext <4 x i8> %4 to <4 x i16>
166  ret <4 x i16> %5
167}
168
169define <4 x i32> @test12() {
170; CHECK-LABEL: test12:
171; CHECK:       # BB#0:
172; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,255,2,253]
173; CHECK-NEXT:    retq
174  %1 = insertelement <4 x i8> undef, i8 0, i32 0
175  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
176  %3 = insertelement <4 x i8> %2, i8 2, i32 2
177  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
178  %5 = zext <4 x i8> %4 to <4 x i32>
179  ret <4 x i32> %5
180}
181
182define <4 x i64> @test13() {
183; CHECK-LABEL: test13:
184; CHECK:       # BB#0:
185; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [0,255,2,253]
186; CHECK-NEXT:    retq
187  %1 = insertelement <4 x i8> undef, i8 0, i32 0
188  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
189  %3 = insertelement <4 x i8> %2, i8 2, i32 2
190  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
191  %5 = zext <4 x i8> %4 to <4 x i64>
192  ret <4 x i64> %5
193}
194
195define <4 x i16> @test14() {
196; CHECK-LABEL: test14:
197; CHECK:       # BB#0:
198; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <u,255,u,253>
199; CHECK-NEXT:    retq
200  %1 = insertelement <4 x i8> undef, i8 undef, i32 0
201  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
202  %3 = insertelement <4 x i8> %2, i8 undef, i32 2
203  %4 = insertelement <4 x i8> %3, i8 -3, i32 3
204  %5 = zext <4 x i8> %4 to <4 x i16>
205  ret <4 x i16> %5
206}
207
208define <4 x i32> @test15() {
209; CHECK-LABEL: test15:
210; CHECK:       # BB#0:
211; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <0,u,2,u>
212; CHECK-NEXT:    retq
213  %1 = insertelement <4 x i8> undef, i8 0, i32 0
214  %2 = insertelement <4 x i8> %1, i8 undef, i32 1
215  %3 = insertelement <4 x i8> %2, i8 2, i32 2
216  %4 = insertelement <4 x i8> %3, i8 undef, i32 3
217  %5 = zext <4 x i8> %4 to <4 x i32>
218  ret <4 x i32> %5
219}
220
221define <4 x i64> @test16() {
222; CHECK-LABEL: test16:
223; CHECK:       # BB#0:
224; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = <u,255,2,u>
225; CHECK-NEXT:    retq
226  %1 = insertelement <4 x i8> undef, i8 undef, i32 0
227  %2 = insertelement <4 x i8> %1, i8 -1, i32 1
228  %3 = insertelement <4 x i8> %2, i8 2, i32 2
229  %4 = insertelement <4 x i8> %3, i8 undef, i32 3
230  %5 = zext <4 x i8> %4 to <4 x i64>
231  ret <4 x i64> %5
232}
233
234define <8 x i16> @test17() {
235; CHECK-LABEL: test17:
236; CHECK:       # BB#0:
237; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,255,2,253,4,251,6,249]
238; CHECK-NEXT:    retq
239  %1 = insertelement <8 x i8> undef, i8 0, i32 0
240  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
241  %3 = insertelement <8 x i8> %2, i8 2, i32 2
242  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
243  %5 = insertelement <8 x i8> %4, i8 4, i32 4
244  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
245  %7 = insertelement <8 x i8> %6, i8 6, i32 6
246  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
247  %9 = zext <8 x i8> %8 to <8 x i16>
248  ret <8 x i16> %9
249}
250
251define <8 x i32> @test18() {
252; CHECK-LABEL: test18:
253; CHECK:       # BB#0:
254; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [0,255,2,253,4,251,6,249]
255; CHECK-NEXT:    retq
256  %1 = insertelement <8 x i8> undef, i8 0, i32 0
257  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
258  %3 = insertelement <8 x i8> %2, i8 2, i32 2
259  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
260  %5 = insertelement <8 x i8> %4, i8 4, i32 4
261  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
262  %7 = insertelement <8 x i8> %6, i8 6, i32 6
263  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
264  %9 = zext <8 x i8> %8 to <8 x i32>
265  ret <8 x i32> %9
266}
267
268define <8 x i16> @test19() {
269; CHECK-LABEL: test19:
270; CHECK:       # BB#0:
271; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = <u,255,u,253,u,251,u,249>
272; CHECK-NEXT:    retq
273  %1 = insertelement <8 x i8> undef, i8 undef, i32 0
274  %2 = insertelement <8 x i8> %1, i8 -1, i32 1
275  %3 = insertelement <8 x i8> %2, i8 undef, i32 2
276  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
277  %5 = insertelement <8 x i8> %4, i8 undef, i32 4
278  %6 = insertelement <8 x i8> %5, i8 -5, i32 5
279  %7 = insertelement <8 x i8> %6, i8 undef, i32 6
280  %8 = insertelement <8 x i8> %7, i8 -7, i32 7
281  %9 = zext <8 x i8> %8 to <8 x i16>
282  ret <8 x i16> %9
283}
284
285define <8 x i32> @test20() {
286; CHECK-LABEL: test20:
287; CHECK:       # BB#0:
288; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = <0,u,2,253,4,u,6,u>
289; CHECK-NEXT:    retq
290  %1 = insertelement <8 x i8> undef, i8 0, i32 0
291  %2 = insertelement <8 x i8> %1, i8 undef, i32 1
292  %3 = insertelement <8 x i8> %2, i8 2, i32 2
293  %4 = insertelement <8 x i8> %3, i8 -3, i32 3
294  %5 = insertelement <8 x i8> %4, i8 4, i32 4
295  %6 = insertelement <8 x i8> %5, i8 undef, i32 5
296  %7 = insertelement <8 x i8> %6, i8 6, i32 6
297  %8 = insertelement <8 x i8> %7, i8 undef, i32 7
298  %9 = zext <8 x i8> %8 to <8 x i32>
299  ret <8 x i32> %9
300}
301