1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 ************************************************************************************************************************ 29 * @file gfx10addrlib.h 30 * @brief Contains the Gfx10Lib class definition. 31 ************************************************************************************************************************ 32 */ 33 34 #ifndef __GFX10_ADDR_LIB_H__ 35 #define __GFX10_ADDR_LIB_H__ 36 37 #include "addrlib2.h" 38 #include "coord.h" 39 #include "gfx10SwizzlePattern.h" 40 41 namespace Addr 42 { 43 namespace V2 44 { 45 46 /** 47 ************************************************************************************************************************ 48 * @brief GFX10 specific settings structure. 49 ************************************************************************************************************************ 50 */ 51 struct Gfx10ChipSettings 52 { 53 struct 54 { 55 UINT_32 reserved1 : 32; 56 57 // Misc configuration bits 58 UINT_32 isDcn20 : 1; 59 UINT_32 supportRbPlus : 1; 60 UINT_32 dsMipmapHtileFix : 1; 61 UINT_32 dccUnsup3DSwDis : 1; 62 UINT_32 : 2; 63 UINT_32 reserved2 : 26; 64 }; 65 }; 66 67 /** 68 ************************************************************************************************************************ 69 * @brief GFX10 data surface type. 70 ************************************************************************************************************************ 71 */ 72 enum Gfx10DataType 73 { 74 Gfx10DataColor, 75 Gfx10DataDepthStencil, 76 Gfx10DataFmask 77 }; 78 79 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR); 80 81 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 82 (1u << ADDR_SW_256B_D); 83 84 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 85 (1u << ADDR_SW_4KB_D) | 86 (1u << ADDR_SW_4KB_S_X) | 87 (1u << ADDR_SW_4KB_D_X); 88 89 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 90 (1u << ADDR_SW_64KB_D) | 91 (1u << ADDR_SW_64KB_S_T) | 92 (1u << ADDR_SW_64KB_D_T) | 93 (1u << ADDR_SW_64KB_Z_X) | 94 (1u << ADDR_SW_64KB_S_X) | 95 (1u << ADDR_SW_64KB_D_X) | 96 (1u << ADDR_SW_64KB_R_X); 97 98 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) | 99 (1u << ADDR_SW_VAR_R_X); 100 101 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 102 (1u << ADDR_SW_VAR_Z_X); 103 104 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) | 105 (1u << ADDR_SW_4KB_S) | 106 (1u << ADDR_SW_64KB_S) | 107 (1u << ADDR_SW_64KB_S_T) | 108 (1u << ADDR_SW_4KB_S_X) | 109 (1u << ADDR_SW_64KB_S_X); 110 111 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 112 (1u << ADDR_SW_4KB_D) | 113 (1u << ADDR_SW_64KB_D) | 114 (1u << ADDR_SW_64KB_D_T) | 115 (1u << ADDR_SW_4KB_D_X) | 116 (1u << ADDR_SW_64KB_D_X); 117 118 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 119 (1u << ADDR_SW_VAR_R_X); 120 121 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 122 (1u << ADDR_SW_4KB_D_X) | 123 (1u << ADDR_SW_64KB_Z_X) | 124 (1u << ADDR_SW_64KB_S_X) | 125 (1u << ADDR_SW_64KB_D_X) | 126 (1u << ADDR_SW_64KB_R_X) | 127 Gfx10BlkVarSwModeMask; 128 129 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 130 (1u << ADDR_SW_64KB_D_T); 131 132 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask | 133 Gfx10TSwModeMask; 134 135 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask | 136 Gfx10RenderSwModeMask | 137 Gfx10ZSwModeMask; 138 139 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask | 140 Gfx10Blk256BSwModeMask | 141 Gfx10Blk4KBSwModeMask | 142 Gfx10Blk64KBSwModeMask | 143 Gfx10BlkVarSwModeMask; 144 145 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) | 146 (1u << ADDR_SW_4KB_S) | 147 (1u << ADDR_SW_64KB_S) | 148 (1u << ADDR_SW_64KB_S_T) | 149 (1u << ADDR_SW_4KB_S_X) | 150 (1u << ADDR_SW_64KB_Z_X) | 151 (1u << ADDR_SW_64KB_S_X) | 152 (1u << ADDR_SW_64KB_D_X) | 153 (1u << ADDR_SW_64KB_R_X) | 154 Gfx10BlkVarSwModeMask; 155 156 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask; 157 158 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask; 159 160 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 161 (1u << ADDR_SW_64KB_R_X); 162 163 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | Gfx10BlkVarSwModeMask; 164 165 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask); 166 167 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask; 168 169 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask; 170 171 const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask | 172 Gfx10RenderSwModeMask; 173 174 const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 175 (1u << ADDR_SW_4KB_S) | 176 (1u << ADDR_SW_64KB_S) | 177 (1u << ADDR_SW_64KB_S_T) | 178 (1u << ADDR_SW_4KB_S_X) | 179 (1u << ADDR_SW_64KB_S_X) | 180 (1u << ADDR_SW_64KB_R_X); 181 182 const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 183 (1u << ADDR_SW_64KB_D) | 184 (1u << ADDR_SW_64KB_D_T) | 185 (1u << ADDR_SW_4KB_D_X) | 186 (1u << ADDR_SW_64KB_D_X) | 187 Dcn20NonBpp64SwModeMask; 188 189 const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 190 (1u << ADDR_SW_64KB_S) | 191 (1u << ADDR_SW_64KB_S_T) | 192 (1u << ADDR_SW_64KB_S_X) | 193 (1u << ADDR_SW_64KB_R_X); 194 195 const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 196 (1u << ADDR_SW_64KB_D_T) | 197 (1u << ADDR_SW_64KB_D_X) | 198 Dcn21NonBpp64SwModeMask; 199 200 /** 201 ************************************************************************************************************************ 202 * @brief This class is the GFX10 specific address library 203 * function set. 204 ************************************************************************************************************************ 205 */ 206 class Gfx10Lib : public Lib 207 { 208 public: 209 /// Creates Gfx10Lib object CreateObj(const Client * pClient)210 static Addr::Lib* CreateObj(const Client* pClient) 211 { 212 VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient); 213 return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL; 214 } 215 216 protected: 217 Gfx10Lib(const Client* pClient); 218 virtual ~Gfx10Lib(); 219 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)220 virtual BOOL_32 HwlIsStandardSwizzle( 221 AddrResourceType resourceType, 222 AddrSwizzleMode swizzleMode) const 223 { 224 return m_swizzleModeTable[swizzleMode].isStd; 225 } 226 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)227 virtual BOOL_32 HwlIsDisplaySwizzle( 228 AddrResourceType resourceType, 229 AddrSwizzleMode swizzleMode) const 230 { 231 return m_swizzleModeTable[swizzleMode].isDisp; 232 } 233 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)234 virtual BOOL_32 HwlIsThin( 235 AddrResourceType resourceType, 236 AddrSwizzleMode swizzleMode) const 237 { 238 return ((IsTex1d(resourceType) == TRUE) || 239 (IsTex2d(resourceType) == TRUE) || 240 ((IsTex3d(resourceType) == TRUE) && 241 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 242 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 243 } 244 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)245 virtual BOOL_32 HwlIsThick( 246 AddrResourceType resourceType, 247 AddrSwizzleMode swizzleMode) const 248 { 249 return ((IsTex3d(resourceType) == TRUE) && 250 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 251 } 252 253 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 254 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 255 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 256 257 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 258 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 259 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 260 261 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 262 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 263 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 264 265 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 266 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 267 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 268 269 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 270 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 271 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 272 273 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 274 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 275 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 276 277 virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord( 278 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 279 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 280 281 virtual UINT_32 HwlGetEquationIndex( 282 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 283 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 284 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)285 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 286 { 287 *ppEquationTable = m_equationTable; 288 289 return m_numEquations; 290 } 291 292 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 293 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 294 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 295 296 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 297 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 298 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 299 300 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 301 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 302 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 303 304 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 305 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 306 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 307 308 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 309 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 310 311 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 312 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 313 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 314 315 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 316 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 317 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 318 319 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 320 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 321 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 322 323 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 324 325 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 326 327 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 328 329 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 330 331 private: 332 // Initialize equation table 333 VOID InitEquationTable(); 334 335 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 336 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 337 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 338 339 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 340 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 341 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 342 343 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 344 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 345 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 346 347 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 348 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 349 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 350 351 352 UINT_32 ComputeOffsetFromSwizzlePattern( 353 const UINT_64* pPattern, 354 UINT_32 numBits, 355 UINT_32 x, 356 UINT_32 y, 357 UINT_32 z, 358 UINT_32 s) const; 359 360 UINT_32 ComputeOffsetFromEquation( 361 const ADDR_EQUATION* pEq, 362 UINT_32 x, 363 UINT_32 y, 364 UINT_32 z) const; 365 366 ADDR_E_RETURNCODE ComputeStereoInfo( 367 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 368 UINT_32 blkHeight, 369 UINT_32* pAlignY, 370 UINT_32* pRightXor) const; 371 372 static void GetMipSize( 373 UINT_32 mip0Width, 374 UINT_32 mip0Height, 375 UINT_32 mip0Depth, 376 UINT_32 mipId, 377 UINT_32* pMipWidth, 378 UINT_32* pMipHeight, 379 UINT_32* pMipDepth = NULL) 380 { 381 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 382 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 383 384 if (pMipDepth != NULL) 385 { 386 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 387 } 388 } 389 390 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 391 AddrSwizzleMode swizzleMode, 392 AddrResourceType resourceType, 393 UINT_32 log2Elem, 394 UINT_32 numFrag) const; 395 GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[20])396 VOID GetSwizzlePatternFromPatternInfo( 397 const ADDR_SW_PATINFO* pPatInfo, 398 ADDR_BIT_SETTING (&pSwizzle)[20]) const 399 { 400 memcpy(pSwizzle, 401 GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 402 sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 403 404 memcpy(&pSwizzle[8], 405 GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 406 sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 407 408 memcpy(&pSwizzle[12], 409 GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 410 sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 411 412 memcpy(&pSwizzle[16], 413 GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 414 sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 415 } 416 417 VOID ConvertSwizzlePatternToEquation( 418 UINT_32 elemLog2, 419 AddrResourceType rsrcType, 420 AddrSwizzleMode swMode, 421 const ADDR_SW_PATINFO* pPatInfo, 422 ADDR_EQUATION* pEquation) const; 423 424 static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType); 425 426 static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType); 427 428 void GetBlk256SizeLog2( 429 AddrResourceType resourceType, 430 AddrSwizzleMode swizzleMode, 431 UINT_32 elemLog2, 432 UINT_32 numSamplesLog2, 433 Dim3d* pBlock) const; 434 435 void GetCompressedBlockSizeLog2( 436 Gfx10DataType dataType, 437 AddrResourceType resourceType, 438 AddrSwizzleMode swizzleMode, 439 UINT_32 elemLog2, 440 UINT_32 numSamplesLog2, 441 Dim3d* pBlock) const; 442 443 INT_32 GetMetaOverlapLog2( 444 Gfx10DataType dataType, 445 AddrResourceType resourceType, 446 AddrSwizzleMode swizzleMode, 447 UINT_32 elemLog2, 448 UINT_32 numSamplesLog2) const; 449 450 INT_32 Get3DMetaOverlapLog2( 451 AddrResourceType resourceType, 452 AddrSwizzleMode swizzleMode, 453 UINT_32 elemLog2) const; 454 455 UINT_32 GetMetaBlkSize( 456 Gfx10DataType dataType, 457 AddrResourceType resourceType, 458 AddrSwizzleMode swizzleMode, 459 UINT_32 elemLog2, 460 UINT_32 numSamplesLog2, 461 BOOL_32 pipeAlign, 462 Dim3d* pBlock) const; 463 464 INT_32 GetPipeRotateAmount( 465 AddrResourceType resourceType, 466 AddrSwizzleMode swizzleMode) const; 467 GetEffectiveNumPipes()468 INT_32 GetEffectiveNumPipes() const 469 { 470 return ((m_settings.supportRbPlus == FALSE) || 471 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1; 472 } 473 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)474 BOOL_32 IsRbAligned( 475 AddrResourceType resourceType, 476 AddrSwizzleMode swizzleMode) const 477 { 478 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 479 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 480 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 481 482 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 483 (IsTex3d(resourceType) && isDisplay); 484 485 } 486 487 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 488 489 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 490 491 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 492 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)493 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 494 { 495 ADDR2_BLOCK_SET allowedBlockSet = {0}; 496 497 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE; 498 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE; 499 allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE; 500 501 if (rsrcType == ADDR_RSRC_TEX_3D) 502 { 503 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 504 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 505 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 506 } 507 else 508 { 509 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE; 510 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE; 511 } 512 513 return allowedBlockSet; 514 } 515 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)516 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 517 { 518 ADDR2_SWTYPE_SET allowedSwSet = {0}; 519 520 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE; 521 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE; 522 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE; 523 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE; 524 525 return allowedSwSet; 526 } 527 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)528 BOOL_32 IsInMipTail( 529 Dim3d mipTailDim, 530 UINT_32 maxNumMipsInTail, 531 UINT_32 mipWidth, 532 UINT_32 mipHeight, 533 UINT_32 numMipsToTheEnd) const 534 { 535 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 536 (mipHeight <= mipTailDim.h) && 537 (numMipsToTheEnd <= maxNumMipsInTail)); 538 539 return inTail; 540 } 541 GetBankXorBits(UINT_32 blockBits)542 UINT_32 GetBankXorBits(UINT_32 blockBits) const 543 { 544 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 545 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 546 } 547 548 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 549 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 550 551 static const UINT_32 ColumnBits = 2; 552 static const UINT_32 BankBits = 4; 553 static const UINT_32 UnalignedDccType = 3; 554 555 static const Dim3d Block256_3d[MaxNumOfBpp]; 556 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 557 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 558 559 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 560 561 // Number of packers log2 562 UINT_32 m_numPkrLog2; 563 // Number of shader array log2 564 UINT_32 m_numSaLog2; 565 566 Gfx10ChipSettings m_settings; 567 568 UINT_32 m_colorBaseIndex; 569 UINT_32 m_xmaskBaseIndex; 570 UINT_32 m_dccBaseIndex; 571 }; 572 573 } // V2 574 } // Addr 575 576 #endif 577 578