1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<domain name="A6XX" width="32"> 8 9 <bitset name="A6XX_GMU_GPU_IDLE_STATUS"> 10 <bitfield name="BUSY_IGN_AHB" pos="23"/> 11 <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/> 12 </bitset> 13 14 <bitset name="A6XX_GMU_OOB"> 15 <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/> 16 <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/> 17 <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/> 18 <bitfield name="DCVS_SET_MASK" pos="23"/> 19 <bitfield name="DCVS_CHECK_MASK" pos="31"/> 20 <bitfield name="DCVS_CLEAR_MASK" pos="31"/> 21 <bitfield name="GPU_SET_MASK" pos="18"/> 22 <bitfield name="GPU_CHECK_MASK" pos="26"/> 23 <bitfield name="GPU_CLEAR_MASK" pos="26"/> 24 <bitfield name="PERFCNTR_SET_MASK" pos="17"/> 25 <bitfield name="PERFCNTR_CHECK_MASK" pos="25"/> 26 <bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/> 27 </bitset> 28 29 <bitset name="A6XX_HFI_IRQ"> 30 <bitfield name="MSGQ_MASK" pos="0" /> 31 <bitfield name="DSGQ_MASK" pos="1"/> 32 <bitfield name="BLOCKED_MSG_MASK" pos="2"/> 33 <bitfield name="CM3_FAULT_MASK" pos="23"/> 34 <bitfield name="GMU_ERR_MASK" low="16" high="22"/> 35 <bitfield name="OOB_MASK" low="24" high="31"/> 36 </bitset> 37 38 <bitset name="A6XX_HFI_H2F"> 39 <bitfield name="IRQ_MASK_BIT" pos="0" /> 40 </bitset> 41 42 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/> 43 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/> 44 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/> 45 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/> 46 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/> 47 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/> 48 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/> 49 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/> 50 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/> 51 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/> 52 <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/> 53 <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/> 54 <reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/> 55 <reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/> 56 <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/> 57 <reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/> 58 <reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/> 59 <reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/> 60 <reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/> 61 <reg32 offset="0x502d" name="GMU_CM3_CFG"/> 62 <reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/> 63 <reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/> 64 <reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/> 65 <reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/> 66 <reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/> 67 <reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/> 68 <reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/> 69 <reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/> 70 <reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/> 71 <reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/> 72 <reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/> 73 <reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/> 74 <reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/> 75 <reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/> 76 <reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/> 77 <reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL"> 78 <bitfield name="IFPC_ENABLE" pos="0" type="boolean"/> 79 <bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/> 80 <bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/> 81 <bitfield name="NUM_PASS_SKIPS" low="10" high="13"/> 82 <bitfield name="MIN_PASS_LENGTH" low="14" high="31"/> 83 </reg32> 84 <reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/> 85 <reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/> 86 <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS"> 87 <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/> 88 <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/> 89 <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/> 90 <bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/> 91 <bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/> 92 <bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/> 93 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/> 94 <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/> 95 </reg32> 96 <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL"> 97 <bitfield name="HW_NAP_ENABLE" pos="0"/> 98 <bitfield name="SID" low="4" high="8"/> 99 </reg32> 100 <reg32 offset="0x50e8" name="GMU_RPMH_CTRL"> 101 <bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/> 102 <bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/> 103 <bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/> 104 <bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/> 105 <bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/> 106 <bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/> 107 <bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/> 108 <bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/> 109 <bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/> 110 <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/> 111 </reg32> 112 <reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/> 113 <reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/> 114 <reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/> 115 <reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/> 116 <reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/> 117 <reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/> 118 <reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/> 119 <reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/> 120 <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/> 121 <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/> 122 <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/> 123 <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/> 124 <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/> 125 <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/> 126 <reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/> 127 <reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/> 128 <reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/> 129 <reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/> 130 <reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/> 131 <reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/> 132 <reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO"> 133 <bitfield name="MSGQ" pos="0" type="boolean"/> 134 <bitfield name="CM3_FAULT" pos="23" type="boolean"/> 135 </reg32> 136 <reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/> 137 <reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/> 138 <reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/> 139 <reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/> 140 <reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/> 141 <reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/> 142 <reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/> 143 <reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/> 144 <reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/> 145 <reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/> 146 <reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/> 147 <reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/> 148 <reg32 offset="0x51c6" name="GMU_GENERAL_1"/> 149 <reg32 offset="0x51cc" name="GMU_GENERAL_7"/> 150 <reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/> 151 <reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/> 152 <reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/> 153 <reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/> 154 <reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/> 155 <reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/> 156 <reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/> 157 <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/> 158 <reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/> 159 <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/> 160 <reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/> 161 <reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/> 162 <reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/> 163 <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/> 164 <reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/> 165 <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/> 166 <reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/> 167 <reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/> 168 <reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/> 169 <reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS"> 170 <bitfield name="WDOG_BITE" pos="0" type="boolean"/> 171 <bitfield name="RSCC_COMP" pos="1" type="boolean"/> 172 <bitfield name="VDROOP" pos="2" type="boolean"/> 173 <bitfield name="FENCE_ERR" pos="3" type="boolean"/> 174 <bitfield name="DBD_WAKEUP" pos="4" type="boolean"/> 175 <bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/> 176 </reg32> 177 <reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/> 178 <reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/> 179 <reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/> 180 <reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/> 181 <reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS"> 182 <bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/> 183 </reg32> 184 <reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/> 185 <reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/> 186 <reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/> 187 <reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/> 188 <reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/> 189 <reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/> 190 <reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/> 191 <reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/> 192 <reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/> 193 <reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/> 194 <reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/> 195 <reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/> 196 197 <!-- starts at offset 0x8c00 on most gpus --> 198 <reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/> 199 <reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/> 200 <reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/> 201 <reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/> 202 <reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/> 203 <reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/> 204 <reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/> 205 <reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/> 206 <reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/> 207 <reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/> 208 <reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/> 209 <reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/> 210 <reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/> 211 <reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/> 212 <reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/> 213 <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/> 214 <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/> 215 <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/> 216</domain> 217 218</database> 219