1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="mdp/mdp_common.xml"/> 7 8<domain name="MDP4" width="32"> 9 <enum name="mdp4_pipe"> 10 <brief>pipe names, index into PIPE[]</brief> 11 <value name="VG1" value="0"/> 12 <value name="VG2" value="1"/> 13 <value name="RGB1" value="2"/> 14 <value name="RGB2" value="3"/> 15 <value name="RGB3" value="4"/> 16 <value name="VG3" value="5"/> 17 <value name="VG4" value="6"/> 18 </enum> 19 20 <enum name="mdp4_mixer"> 21 <value name="MIXER0" value="0"/> 22 <value name="MIXER1" value="1"/> 23 <value name="MIXER2" value="2"/> 24 </enum> 25 26 <enum name="mdp4_intf"> 27 <!-- 28 A bit confusing the enums for interface selection: 29 enum { 30 LCDC_RGB_INTF, /* 0 */ 31 DTV_INTF = LCDC_RGB_INTF, /* 0 */ 32 MDDI_LCDC_INTF, /* 1 */ 33 MDDI_INTF, /* 2 */ 34 EBI2_INTF, /* 3 */ 35 TV_INTF = EBI2_INTF, /* 3 */ 36 DSI_VIDEO_INTF, 37 DSI_CMD_INTF 38 }; 39 there is some overlap, and not all the values end up getting 40 written to hw (mdp4_display_intf_sel() remaps the last two 41 values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so 42 taking some liberties in guessing the actual meanings/names: 43 --> 44 <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) --> 45 <value name="INTF_DSI_VIDEO" value="1"/> 46 <value name="INTF_DSI_CMD" value="2"/> 47 <value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) --> 48 </enum> 49 <enum name="mdp4_cursor_format"> 50 <value name="CURSOR_ARGB" value="1"/> 51 <value name="CURSOR_XRGB" value="2"/> 52 </enum> 53 <enum name="mdp4_frame_format"> 54 <value name="FRAME_LINEAR" value="0"/> 55 <value name="FRAME_TILE_ARGB_4X4" value="1"/> 56 <value name="FRAME_TILE_YCBCR_420" value="2"/> 57 </enum> 58 <enum name="mdp4_scale_unit"> 59 <value name="SCALE_FIR" value="0"/> 60 <value name="SCALE_MN_PHASE" value="1"/> 61 <value name="SCALE_PIXEL_RPT" value="2"/> 62 </enum> 63 64 <bitset name="mdp4_layermixer_in_cfg" inline="yes"> 65 <brief>appears to map pipe to mixer stage</brief> 66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/> 67 <bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/> 68 <bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/> 69 <bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/> 70 <bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/> 71 <bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/> 72 <bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/> 73 <bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/> 74 <bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/> 75 <bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/> 76 <bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/> 77 <bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/> 78 <bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/> 79 <bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/> 80 <bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/> 81 <bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/> 82 </bitset> 83 84 <bitset name="MDP4_IRQ"> 85 <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/> 86 <bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/> 87 <bitfield name="DMA_S_DONE" pos="2" type="boolean"/> 88 <bitfield name="DMA_E_DONE" pos="3" type="boolean"/> 89 <bitfield name="DMA_P_DONE" pos="4" type="boolean"/> 90 <bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/> 91 <bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/> 92 <bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/> 93 <bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/> 94 <bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/> 95 <bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/> 96 <bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer --> 97 <bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/> 98 <bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/> 99 <bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/> 100 </bitset> 101 102 <group name="mdp4_csc"> 103 <array offset="0x400" name="MV" length="9" stride="4"> 104 <reg32 offset="0" name="VAL"/> 105 </array> 106 <array offset="0x500" name="PRE_BV" length="3" stride="4"> 107 <reg32 offset="0" name="VAL"/> 108 </array> 109 <array offset="0x580" name="POST_BV" length="3" stride="4"> 110 <reg32 offset="0" name="VAL"/> 111 </array> 112 <array offset="0x600" name="PRE_LV" length="6" stride="4"> 113 <reg32 offset="0" name="VAL"/> 114 </array> 115 <array offset="0x680" name="POST_LV" length="6" stride="4"> 116 <reg32 offset="0" name="VAL"/> 117 </array> 118 </group> 119 120 <reg32 offset="0x00000" name="VERSION"> 121 <!-- 122 from mdp_probe() we can see minor rev starts at 16.. assume 123 major is above that.. not sure the rest of bits but doesn't 124 really seem to matter 125 --> 126 <bitfield name="MINOR" low="16" high="23" type="uint"/> 127 <bitfield name="MAJOR" low="24" high="31" type="uint"/> 128 </reg32> 129 <reg32 offset="0x00004" name="OVLP0_KICK"/> 130 <reg32 offset="0x00008" name="OVLP1_KICK"/> 131 <reg32 offset="0x000d0" name="OVLP2_KICK"/> 132 <reg32 offset="0x0000c" name="DMA_P_KICK"/> 133 <reg32 offset="0x00010" name="DMA_S_KICK"/> 134 <reg32 offset="0x00014" name="DMA_E_KICK"/> 135 <reg32 offset="0x00018" name="DISP_STATUS"/> 136 137 <reg32 offset="0x00038" name="DISP_INTF_SEL"> 138 <bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/> 139 <bitfield name="SEC" low="2" high="3" type="mdp4_intf"/> 140 <bitfield name="EXT" low="4" high="5" type="mdp4_intf"/> 141 <bitfield name="DSI_VIDEO" pos="6" type="boolean"/> 142 <bitfield name="DSI_CMD" pos="7" type="boolean"/> 143 </reg32> 144 <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 --> 145 <reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. --> 146 <reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/> 147 <reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/> 148 <reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/> 149 <reg32 offset="0x00060" name="EBI2_LCD0"/> 150 <reg32 offset="0x00064" name="EBI2_LCD1"/> 151 <reg32 offset="0x00070" name="PORTMAP_MODE"/> 152 153 <!-- mdp chip-select controller: --> 154 <reg32 offset="0x000c0" name="CS_CONTROLLER0"/> 155 <reg32 offset="0x000c4" name="CS_CONTROLLER1"/> 156 157 <reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/> 158 <reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/> 159 <reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/> 160 161 <reg32 offset="0x30050" name="VG2_SRC_FORMAT"/> 162 <reg32 offset="0x31008" name="VG2_CONST_COLOR"/> 163 164 <reg32 offset="0x18000" name="OVERLAY_FLUSH"> 165 <bitfield name="OVLP0" pos="0" type="boolean"/> 166 <bitfield name="OVLP1" pos="1" type="boolean"/> 167 <bitfield name="VG1" pos="2" type="boolean"/> 168 <bitfield name="VG2" pos="3" type="boolean"/> 169 <bitfield name="RGB1" pos="4" type="boolean"/> 170 <bitfield name="RGB2" pos="5" type="boolean"/> 171 </reg32> 172 173 <array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000"> 174 <reg32 offset="0x0004" name="CFG"/> 175 <reg32 offset="0x0008" name="SIZE" type="reg_wh"/> 176 <reg32 offset="0x000c" name="BASE"/> 177 <reg32 offset="0x0010" name="STRIDE" type="uint"/> 178 <reg32 offset="0x0014" name="OPMODE"/> 179 180 <array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c"> 181 <reg32 offset="0x00" name="OP"> 182 <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/> 183 <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/> 184 <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/> 185 <bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/> 186 <bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/> 187 <bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/> 188 <bitfield name="FG_TRANSP" pos="8" type="boolean"/> 189 <bitfield name="BG_TRANSP" pos="9" type="boolean"/> 190 </reg32> 191 <reg32 offset="0x04" name="FG_ALPHA"/> 192 <reg32 offset="0x08" name="BG_ALPHA"/> 193 <reg32 offset="0x0c" name="TRANSP_LOW0"/> 194 <reg32 offset="0x10" name="TRANSP_LOW1"/> 195 <reg32 offset="0x14" name="TRANSP_HIGH0"/> 196 <reg32 offset="0x18" name="TRANSP_HIGH1"/> 197 </array> 198 199 <array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4"> 200 <reg32 offset="0" name="SEL"> 201 <bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha --> 202 </reg32> 203 </array> 204 205 <reg32 offset="0x0180" name="TRANSP_LOW0"/> 206 <reg32 offset="0x0184" name="TRANSP_LOW1"/> 207 <reg32 offset="0x0188" name="TRANSP_HIGH0"/> 208 <reg32 offset="0x018c" name="TRANSP_HIGH1"/> 209 210 <reg32 offset="0x0200" name="CSC_CONFIG"/> 211 212 <array offset="0x2000" name="CSC" length="1" stride="0x700"> 213 <use-group ref="mdp4_csc"/> 214 </array> 215 </array> 216 217 <enum name="mdp4_dma"> 218 <value name="DMA_P" value="0"/> 219 <value name="DMA_S" value="1"/> 220 <value name="DMA_E" value="2"/> 221 </enum> 222 <reg32 offset="0x90070" name="DMA_P_OP_MODE"/> 223 <array offset="0x94800" name="LUTN" length="2" stride="0x400"> 224 <array offset="0" name="LUT" length="0x100" stride="4"> 225 <reg32 offset="0" name="VAL"/> 226 </array> 227 </array> 228 <reg32 offset="0xa0028" name="DMA_S_OP_MODE"/> 229 <!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. --> 230 <reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/> 231 <array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma"> 232 <reg32 offset="0x0000" name="CONFIG"> 233 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/> 234 <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/> 235 <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/> 236 <bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/> 237 <bitfield name="PACK" low="8" high="15"/> 238 <!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E --> 239 <bitfield name="DEFLKR_EN" pos="24" type="boolean"/> 240 <bitfield name="DITHER_EN" pos="24" type="boolean"/> 241 </reg32> 242 <reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/> 243 <reg32 offset="0x0008" name="SRC_BASE"/> 244 <reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/> 245 <reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/> 246 247 <reg32 offset="0x0044" name="CURSOR_SIZE"> 248 <!-- seems the limit is 64x64: --> 249 <bitfield name="WIDTH" low="0" high="6" type="uint"/> 250 <bitfield name="HEIGHT" low="16" high="22" type="uint"/> 251 </reg32> 252 <reg32 offset="0x0048" name="CURSOR_BASE"/> 253 <reg32 offset="0x004c" name="CURSOR_POS"> 254 <bitfield name="X" low="0" high="15" type="uint"/> 255 <bitfield name="Y" low="16" high="31" type="uint"/> 256 </reg32> 257 <reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG"> 258 <bitfield name="CURSOR_EN" pos="0" type="boolean"/> 259 <bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/> 260 <bitfield name="TRANSP_EN" pos="3" type="boolean"/> 261 </reg32> 262 <reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/> 263 <reg32 offset="0x0068" name="BLEND_TRANS_LOW"/> 264 <reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/> 265 266 <reg32 offset="0x1004" name="FETCH_CONFIG"/> 267 <array offset="0x3000" name="CSC" length="1" stride="0x700"> 268 <use-group ref="mdp4_csc"/> 269 </array> 270 </array> 271 272 <!-- 273 TODO length should be 7, but that would collide w/ OVLP2..!?! 274 this register map is a bit strange.. 275 --> 276 <array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe"> 277 <reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/> 278 <reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/> 279 <reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/> 280 <reg32 offset="0x000c" name="DST_XY" type="reg_xy"/> 281 <reg32 offset="0x0010" name="SRCP0_BASE"/> 282 <reg32 offset="0x0014" name="SRCP1_BASE"/> 283 <reg32 offset="0x0018" name="SRCP2_BASE"/> 284 <reg32 offset="0x001c" name="SRCP3_BASE"/> 285 <reg32 offset="0x0040" name="SRC_STRIDE_A"> 286 <bitfield name="P0" low="0" high="15" type="uint"/> 287 <bitfield name="P1" low="16" high="31" type="uint"/> 288 </reg32> 289 <reg32 offset="0x0044" name="SRC_STRIDE_B"> 290 <bitfield name="P2" low="0" high="15" type="uint"/> 291 <bitfield name="P3" low="16" high="31" type="uint"/> 292 </reg32> 293 <reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/> 294 <reg32 offset="0x0050" name="SRC_FORMAT"> 295 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/> 296 <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/> 297 <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/> 298 <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/> 299 <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/> 300 <bitfield name="CPP" low="9" high="10" type="uint"> 301 <brief>8bit characters per pixel minus 1</brief> 302 </bitfield> 303 <bitfield name="ROTATED_90" pos="12" type="boolean"/> 304 <bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/> 305 <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/> 306 <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/> 307 <bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/> 308 <bitfield name="SOLID_FILL" pos="22" type="boolean"/> 309 <bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/> 310 <bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/> 311 </reg32> 312 <reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/> 313 <reg32 offset="0x0058" name="OP_MODE"> 314 <bitfield name="SCALEX_EN" pos="0" type="boolean"/> 315 <bitfield name="SCALEY_EN" pos="1" type="boolean"/> 316 <bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/> 317 <bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/> 318 <bitfield name="SRC_YCBCR" pos="9" type="boolean"/> 319 <bitfield name="DST_YCBCR" pos="10" type="boolean"/> 320 <bitfield name="CSC_EN" pos="11" type="boolean"/> 321 <bitfield name="FLIP_LR" pos="13" type="boolean"/> 322 <bitfield name="FLIP_UD" pos="14" type="boolean"/> 323 <bitfield name="DITHER_EN" pos="15" type="boolean"/> 324 <bitfield name="IGC_LUT_EN" pos="16" type="boolean"/> 325 <bitfield name="DEINT_EN" pos="18" type="boolean"/> 326 <bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/> 327 </reg32> 328 <reg32 offset="0x005c" name="PHASEX_STEP"/> 329 <reg32 offset="0x0060" name="PHASEY_STEP"/> 330 <reg32 offset="0x1004" name="FETCH_CONFIG"/> 331 <reg32 offset="0x1008" name="SOLID_COLOR"/> 332 333 <array offset="0x4000" name="CSC" length="1" stride="0x700"> 334 <use-group ref="mdp4_csc"/> 335 </array> 336 </array> 337 338 <!-- 339 ENCODERS 340 LCDC and DSI seem the same, DTV is just slightly different.. 341 --> 342 343 <bitset name="mdp4_ctrl_polarity" inline="yes"> 344 <!-- not entirely sure if these bits mean hi or low.. --> 345 <bitfield name="HSYNC_LOW" pos="0" type="boolean"/> 346 <bitfield name="VSYNC_LOW" pos="1" type="boolean"/> 347 <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/> 348 </bitset> 349 350 <bitset name="mdp4_active_hctl" inline="yes"> 351 <bitfield name="START" low="0" high="14" type="uint"/> 352 <bitfield name="END" low="16" high="30" type="uint"/> 353 <bitfield name="ACTIVE_START_X" pos="31" type="boolean"/> 354 </bitset> 355 356 <bitset name="mdp4_display_hctl" inline="yes"> 357 <bitfield name="START" low="0" high="15" type="uint"/> 358 <bitfield name="END" low="16" high="31" type="uint"/> 359 </bitset> 360 361 <bitset name="mdp4_hsync_ctrl" inline="yes"> 362 <bitfield name="PULSEW" low="0" high="15" type="uint"/> 363 <bitfield name="PERIOD" low="16" high="31" type="uint"/> 364 </bitset> 365 366 <bitset name="mdp4_underflow_clr" inline="yes"> 367 <bitfield name="COLOR" low="0" high="23"/> 368 <bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/> 369 </bitset> 370 371 <!-- offset is 0xe0000 on !mdp4.. --> 372 <array offset="0xc0000" name="LCDC" length="1" stride="0x1000"> 373 <reg32 offset="0x0000" name="ENABLE"/> 374 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 375 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 376 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 377 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 378 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/> 379 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/> 380 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 381 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/> 382 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/> 383 <reg32 offset="0x0028" name="BORDER_CLR"/> 384 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 385 <reg32 offset="0x0030" name="HSYNC_SKEW"/> 386 <reg32 offset="0x0034" name="TEST_CNTL"/> 387 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 388 </array> 389 390 <reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL"> 391 <bitfield name="MODE_SEL" pos="2" type="boolean"/> 392 <bitfield name="RGB_OUT" pos="3" type="boolean"/> 393 <bitfield name="CH_SWAP" pos="4" type="boolean"/> 394 <bitfield name="CH1_RES_BIT" pos="5" type="boolean"/> 395 <bitfield name="CH2_RES_BIT" pos="6" type="boolean"/> 396 <bitfield name="ENABLE" pos="7" type="boolean"/> 397 <bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/> 398 <bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/> 399 <bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/> 400 <bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/> 401 <bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/> 402 <bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/> 403 <bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/> 404 <bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/> 405 <bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/> 406 <bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/> 407 </reg32> 408 409 <array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8"> 410 <reg32 offset="0x0" name="3_TO_0"> 411 <bitfield name="BIT0" low="0" high="7"/> 412 <bitfield name="BIT1" low="8" high="15"/> 413 <bitfield name="BIT2" low="16" high="23"/> 414 <bitfield name="BIT3" low="24" high="31"/> 415 </reg32> 416 <reg32 offset="0x4" name="6_TO_4"> 417 <bitfield name="BIT4" low="0" high="7"/> 418 <bitfield name="BIT5" low="8" high="15"/> 419 <bitfield name="BIT6" low="16" high="23"/> 420 </reg32> 421 </array> 422 423 <reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/> 424 425 <reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/> 426 <reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/> 427 <reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/> 428 <reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/> 429 <reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/> 430 <reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/> 431 <reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/> 432 <reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/> 433 <reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/> 434 <reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/> 435 <reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/> 436 437 <reg32 offset="0xc3100" name="LVDS_PHY_CFG0"> 438 <bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/> 439 <bitfield name="CHANNEL0" pos="6" type="boolean"/> 440 <bitfield name="CHANNEL1" pos="7" type="boolean"/> 441 </reg32> 442 443 <array offset="0xd0000" name="DTV" length="1" stride="0x1000"> 444 <reg32 offset="0x0000" name="ENABLE"/> 445 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 446 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 447 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 448 <reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 449 <reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/> 450 <reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/> 451 <reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 452 <reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/> 453 <reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/> 454 <reg32 offset="0x0040" name="BORDER_CLR"/> 455 <reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 456 <reg32 offset="0x0048" name="HSYNC_SKEW"/> 457 <reg32 offset="0x004c" name="TEST_CNTL"/> 458 <reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 459 </array> 460 461 <array offset="0xe0000" name="DSI" length="1" stride="0x1000"> 462 <reg32 offset="0x0000" name="ENABLE"/> 463 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 464 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 465 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 466 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 467 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/> 468 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/> 469 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 470 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/> 471 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/> 472 <reg32 offset="0x0028" name="BORDER_CLR"/> 473 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 474 <reg32 offset="0x0030" name="HSYNC_SKEW"/> 475 <reg32 offset="0x0034" name="TEST_CNTL"/> 476 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 477 </array> 478</domain> 479 480</database> 481