1 /**************************************************************************
2  *
3  * Copyright 2017 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "si_pipe.h"
32 #include "util/u_video.h"
33 
34 #include <stdio.h>
35 
36 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
37 #define RENCODE_FW_INTERFACE_MINOR_VERSION 2
38 
39 #define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
40 #define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
41 #define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
42 #define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
43 #define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
44 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
45 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
46 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
47 #define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
48 #define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000a
49 #define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000b
50 #define RENCODE_IB_PARAM_INTRA_REFRESH             0x0000000c
51 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x0000000d
52 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x0000000e
53 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000010
54 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x00000020
55 
56 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
57 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
58 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER    0x00100003
59 
60 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
61 #define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
62 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
63 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
64 
radeon_enc_session_info(struct radeon_encoder * enc)65 static void radeon_enc_session_info(struct radeon_encoder *enc)
66 {
67    RADEON_ENC_BEGIN(enc->cmd.session_info);
68    RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
69    RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
70    RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
71    RADEON_ENC_END();
72 }
73 
radeon_enc_task_info(struct radeon_encoder * enc,bool need_feedback)74 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
75 {
76    enc->enc_pic.task_info.task_id++;
77 
78    if (need_feedback)
79       enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
80    else
81       enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
82 
83    RADEON_ENC_BEGIN(enc->cmd.task_info);
84    enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
85    RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
86    RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
87    RADEON_ENC_END();
88 }
89 
radeon_enc_session_init(struct radeon_encoder * enc)90 static void radeon_enc_session_init(struct radeon_encoder *enc)
91 {
92    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
93    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
94    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
95    enc->enc_pic.session_init.padding_width =
96       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
97    enc->enc_pic.session_init.padding_height =
98       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
99    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
100    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
101 
102    RADEON_ENC_BEGIN(enc->cmd.session_init);
103    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
104    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
105    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
106    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
107    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
108    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
109    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
110    RADEON_ENC_END();
111 }
112 
radeon_enc_session_init_hevc(struct radeon_encoder * enc)113 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
114 {
115    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
116    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
117    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
118    enc->enc_pic.session_init.padding_width =
119       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
120    enc->enc_pic.session_init.padding_height =
121       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
122    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
123    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
124 
125    RADEON_ENC_BEGIN(enc->cmd.session_init);
126    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
127    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
128    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
129    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
130    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
131    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
132    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
133    RADEON_ENC_END();
134 }
135 
radeon_enc_layer_control(struct radeon_encoder * enc)136 static void radeon_enc_layer_control(struct radeon_encoder *enc)
137 {
138    enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
139    enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
140 
141    RADEON_ENC_BEGIN(enc->cmd.layer_control);
142    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
143    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
144    RADEON_ENC_END();
145 }
146 
radeon_enc_layer_select(struct radeon_encoder * enc)147 static void radeon_enc_layer_select(struct radeon_encoder *enc)
148 {
149    enc->enc_pic.layer_sel.temporal_layer_index = 0;
150 
151    RADEON_ENC_BEGIN(enc->cmd.layer_select);
152    RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
153    RADEON_ENC_END();
154 }
155 
radeon_enc_slice_control(struct radeon_encoder * enc)156 static void radeon_enc_slice_control(struct radeon_encoder *enc)
157 {
158    enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
159    enc->enc_pic.slice_ctrl.num_mbs_per_slice =
160       align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
161 
162    RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
163    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
164    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
165    RADEON_ENC_END();
166 }
167 
radeon_enc_slice_control_hevc(struct radeon_encoder * enc)168 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
169 {
170    enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
171    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
172       align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
173    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
174       enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
175 
176    RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
177    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
178    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
179    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
180    RADEON_ENC_END();
181 }
182 
radeon_enc_spec_misc(struct radeon_encoder * enc)183 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
184 {
185    enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
186    enc->enc_pic.spec_misc.cabac_enable = 0;
187    enc->enc_pic.spec_misc.cabac_init_idc = 0;
188    enc->enc_pic.spec_misc.half_pel_enabled = 1;
189    enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
190    enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
191    enc->enc_pic.spec_misc.level_idc = enc->base.level;
192 
193    RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
194    RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
195    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
196    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
197    RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
198    RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
199    RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
200    RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
201    RADEON_ENC_END();
202 }
203 
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)204 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
205 {
206    RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
207    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
208    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
209    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
210    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
211    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
212    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
213    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
214    RADEON_ENC_END();
215 }
216 
radeon_enc_rc_session_init(struct radeon_encoder * enc)217 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
218 {
219    RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
220    RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
221    RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
222    RADEON_ENC_END();
223 }
224 
radeon_enc_rc_layer_init(struct radeon_encoder * enc)225 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
226 {
227    RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
228    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
229    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
230    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
231    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
232    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
233    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
234    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
235    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
236    RADEON_ENC_END();
237 }
238 
radeon_enc_deblocking_filter_h264(struct radeon_encoder * enc)239 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
240 {
241    enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
242    enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
243    enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
244    enc->enc_pic.h264_deblock.cb_qp_offset = 0;
245    enc->enc_pic.h264_deblock.cr_qp_offset = 0;
246 
247    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
248    RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
249    RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
250    RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
251    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
252    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
253    RADEON_ENC_END();
254 }
255 
radeon_enc_deblocking_filter_hevc(struct radeon_encoder * enc)256 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
257 {
258    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
259    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
260    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
261    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
262    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
263    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
264    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
265    RADEON_ENC_END();
266 }
267 
radeon_enc_quality_params(struct radeon_encoder * enc)268 static void radeon_enc_quality_params(struct radeon_encoder *enc)
269 {
270    enc->enc_pic.quality_params.vbaq_mode = 0;
271    enc->enc_pic.quality_params.scene_change_sensitivity = 0;
272    enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
273 
274    RADEON_ENC_BEGIN(enc->cmd.quality_params);
275    RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
276    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
277    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
278    RADEON_ENC_END();
279 }
280 
radeon_enc_nalu_sps(struct radeon_encoder * enc)281 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
282 {
283    RADEON_ENC_BEGIN(enc->cmd.nalu);
284    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
285    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
286    radeon_enc_reset(enc);
287    radeon_enc_set_emulation_prevention(enc, false);
288    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
289    radeon_enc_code_fixed_bits(enc, 0x67, 8);
290    radeon_enc_byte_align(enc);
291    radeon_enc_set_emulation_prevention(enc, true);
292    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
293    radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
294    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
295    radeon_enc_code_ue(enc, 0x0);
296 
297    if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
298        enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
299        enc->enc_pic.spec_misc.profile_idc == 44  || enc->enc_pic.spec_misc.profile_idc == 83 ||
300        enc->enc_pic.spec_misc.profile_idc == 86  || enc->enc_pic.spec_misc.profile_idc == 118 ||
301        enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
302       radeon_enc_code_ue(enc, 0x1);
303       radeon_enc_code_ue(enc, 0x0);
304       radeon_enc_code_ue(enc, 0x0);
305       radeon_enc_code_fixed_bits(enc, 0x0, 2);
306    }
307 
308    radeon_enc_code_ue(enc, 1);
309    radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
310 
311    if (enc->enc_pic.pic_order_cnt_type == 0)
312       radeon_enc_code_ue(enc, 1);
313 
314    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
315    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
316                               1);
317    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
318    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
319    bool progressive_only = true;
320    radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
321 
322    if (!progressive_only)
323       radeon_enc_code_fixed_bits(enc, 0x0, 1);
324 
325    radeon_enc_code_fixed_bits(enc, 0x1, 1);
326 
327    if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
328        (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
329       radeon_enc_code_fixed_bits(enc, 0x1, 1);
330       radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
331       radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
332       radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
333       radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
334    } else
335       radeon_enc_code_fixed_bits(enc, 0x0, 1);
336 
337    radeon_enc_code_fixed_bits(enc, 0x1, 1);
338    radeon_enc_code_fixed_bits(enc, 0x0, 1);
339    radeon_enc_code_fixed_bits(enc, 0x0, 1);
340    radeon_enc_code_fixed_bits(enc, 0x0, 1);
341    radeon_enc_code_fixed_bits(enc, 0x0, 1);
342    radeon_enc_code_fixed_bits(enc, 0x0, 1);
343    radeon_enc_code_fixed_bits(enc, 0x0, 1);
344    radeon_enc_code_fixed_bits(enc, 0x0, 1);
345    radeon_enc_code_fixed_bits(enc, 0x0, 1);
346    radeon_enc_code_fixed_bits(enc, 0x1, 1);
347    radeon_enc_code_fixed_bits(enc, 0x1, 1);
348    radeon_enc_code_ue(enc, 0x0);
349    radeon_enc_code_ue(enc, 0x0);
350    radeon_enc_code_ue(enc, 16);
351    radeon_enc_code_ue(enc, 16);
352    radeon_enc_code_ue(enc, 0x0);
353    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
354 
355    radeon_enc_code_fixed_bits(enc, 0x1, 1);
356 
357    radeon_enc_byte_align(enc);
358    radeon_enc_flush_headers(enc);
359    *size_in_bytes = (enc->bits_output + 7) / 8;
360    RADEON_ENC_END();
361 }
362 
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)363 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
364 {
365    RADEON_ENC_BEGIN(enc->cmd.nalu);
366    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
367    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
368    int i;
369 
370    radeon_enc_reset(enc);
371    radeon_enc_set_emulation_prevention(enc, false);
372    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
373    radeon_enc_code_fixed_bits(enc, 0x4201, 16);
374    radeon_enc_byte_align(enc);
375    radeon_enc_set_emulation_prevention(enc, true);
376    radeon_enc_code_fixed_bits(enc, 0x0, 4);
377    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
378    radeon_enc_code_fixed_bits(enc, 0x1, 1);
379    radeon_enc_code_fixed_bits(enc, 0x0, 2);
380    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
381    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
382    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
383    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
384    radeon_enc_code_fixed_bits(enc, 0x0, 16);
385    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
386 
387    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
388       radeon_enc_code_fixed_bits(enc, 0x0, 2);
389 
390    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
391       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
392          radeon_enc_code_fixed_bits(enc, 0x0, 2);
393    }
394 
395    radeon_enc_code_ue(enc, 0x0);
396    radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
397    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
398    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
399 
400 	if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
401 	    (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
402 		radeon_enc_code_fixed_bits(enc, 0x1, 1);
403 		radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
404 		radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
405 		radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
406 		radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
407 	} else
408 		radeon_enc_code_fixed_bits(enc, 0x0, 1);
409 
410    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
411    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
412    radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
413    radeon_enc_code_fixed_bits(enc, 0x0, 1);
414    radeon_enc_code_ue(enc, 1);
415    radeon_enc_code_ue(enc, 0x0);
416    radeon_enc_code_ue(enc, 0x0);
417    radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
418    // Only support CTBSize 64
419    radeon_enc_code_ue(enc,
420                       6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
421    radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
422    radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
423    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
424    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
425 
426    radeon_enc_code_fixed_bits(enc, 0x0, 1);
427    radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
428    radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
429    radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
430 
431    radeon_enc_code_ue(enc, 1);
432    radeon_enc_code_ue(enc, 1);
433    radeon_enc_code_ue(enc, 0);
434    radeon_enc_code_ue(enc, 0);
435    radeon_enc_code_fixed_bits(enc, 0x1, 1);
436 
437    radeon_enc_code_fixed_bits(enc, 0x0, 1);
438 
439    radeon_enc_code_fixed_bits(enc, 0, 1);
440    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
441 
442    radeon_enc_code_fixed_bits(enc, 0x0, 1);
443 
444    radeon_enc_code_fixed_bits(enc, 0x0, 1);
445 
446    radeon_enc_code_fixed_bits(enc, 0x1, 1);
447 
448    radeon_enc_byte_align(enc);
449    radeon_enc_flush_headers(enc);
450    *size_in_bytes = (enc->bits_output + 7) / 8;
451    RADEON_ENC_END();
452 }
453 
radeon_enc_nalu_pps(struct radeon_encoder * enc)454 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
455 {
456    RADEON_ENC_BEGIN(enc->cmd.nalu);
457    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
458    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
459    radeon_enc_reset(enc);
460    radeon_enc_set_emulation_prevention(enc, false);
461    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
462    radeon_enc_code_fixed_bits(enc, 0x68, 8);
463    radeon_enc_byte_align(enc);
464    radeon_enc_set_emulation_prevention(enc, true);
465    radeon_enc_code_ue(enc, 0x0);
466    radeon_enc_code_ue(enc, 0x0);
467    radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
468    radeon_enc_code_fixed_bits(enc, 0x0, 1);
469    radeon_enc_code_ue(enc, 0x0);
470    radeon_enc_code_ue(enc, 0x0);
471    radeon_enc_code_ue(enc, 0x0);
472    radeon_enc_code_fixed_bits(enc, 0x0, 1);
473    radeon_enc_code_fixed_bits(enc, 0x0, 2);
474    radeon_enc_code_se(enc, 0x0);
475    radeon_enc_code_se(enc, 0x0);
476    radeon_enc_code_se(enc, 0x0);
477    radeon_enc_code_fixed_bits(enc, 0x1, 1);
478    radeon_enc_code_fixed_bits(enc, 0x0, 1);
479    radeon_enc_code_fixed_bits(enc, 0x0, 1);
480 
481    radeon_enc_code_fixed_bits(enc, 0x1, 1);
482 
483    radeon_enc_byte_align(enc);
484    radeon_enc_flush_headers(enc);
485    *size_in_bytes = (enc->bits_output + 7) / 8;
486    RADEON_ENC_END();
487 }
488 
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)489 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
490 {
491    RADEON_ENC_BEGIN(enc->cmd.nalu);
492    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
493    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
494    radeon_enc_reset(enc);
495    radeon_enc_set_emulation_prevention(enc, false);
496    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
497    radeon_enc_code_fixed_bits(enc, 0x4401, 16);
498    radeon_enc_byte_align(enc);
499    radeon_enc_set_emulation_prevention(enc, true);
500    radeon_enc_code_ue(enc, 0x0);
501    radeon_enc_code_ue(enc, 0x0);
502    radeon_enc_code_fixed_bits(enc, 0x1, 1);
503    radeon_enc_code_fixed_bits(enc, 0x0, 4);
504    radeon_enc_code_fixed_bits(enc, 0x0, 1);
505    radeon_enc_code_fixed_bits(enc, 0x1, 1);
506    radeon_enc_code_ue(enc, 0x0);
507    radeon_enc_code_ue(enc, 0x0);
508    radeon_enc_code_se(enc, 0x0);
509    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
510    radeon_enc_code_fixed_bits(enc, 0x0, 1);
511    if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
512       radeon_enc_code_fixed_bits(enc, 0x0, 1);
513    else {
514       radeon_enc_code_fixed_bits(enc, 0x1, 1);
515       radeon_enc_code_ue(enc, 0x0);
516    }
517    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
518    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
519    radeon_enc_code_fixed_bits(enc, 0x0, 1);
520    radeon_enc_code_fixed_bits(enc, 0x0, 2);
521    radeon_enc_code_fixed_bits(enc, 0x0, 1);
522    radeon_enc_code_fixed_bits(enc, 0x0, 1);
523    radeon_enc_code_fixed_bits(enc, 0x0, 1);
524    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
525    radeon_enc_code_fixed_bits(enc, 0x1, 1);
526    radeon_enc_code_fixed_bits(enc, 0x0, 1);
527    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
528 
529    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
530       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
531       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
532    }
533 
534    radeon_enc_code_fixed_bits(enc, 0x0, 1);
535    radeon_enc_code_fixed_bits(enc, 0x0, 1);
536    radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
537    radeon_enc_code_fixed_bits(enc, 0x0, 2);
538 
539    radeon_enc_code_fixed_bits(enc, 0x1, 1);
540 
541    radeon_enc_byte_align(enc);
542    radeon_enc_flush_headers(enc);
543    *size_in_bytes = (enc->bits_output + 7) / 8;
544    RADEON_ENC_END();
545 }
546 
radeon_enc_nalu_vps(struct radeon_encoder * enc)547 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
548 {
549    RADEON_ENC_BEGIN(enc->cmd.nalu);
550    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
551    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
552    int i;
553 
554    radeon_enc_reset(enc);
555    radeon_enc_set_emulation_prevention(enc, false);
556    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
557    radeon_enc_code_fixed_bits(enc, 0x4001, 16);
558    radeon_enc_byte_align(enc);
559    radeon_enc_set_emulation_prevention(enc, true);
560 
561    radeon_enc_code_fixed_bits(enc, 0x0, 4);
562    radeon_enc_code_fixed_bits(enc, 0x3, 2);
563    radeon_enc_code_fixed_bits(enc, 0x0, 6);
564    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
565    radeon_enc_code_fixed_bits(enc, 0x1, 1);
566    radeon_enc_code_fixed_bits(enc, 0xffff, 16);
567    radeon_enc_code_fixed_bits(enc, 0x0, 2);
568    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
569    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
570    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
571    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
572    radeon_enc_code_fixed_bits(enc, 0x0, 16);
573    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
574 
575    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
576       radeon_enc_code_fixed_bits(enc, 0x0, 2);
577 
578    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
579       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
580          radeon_enc_code_fixed_bits(enc, 0x0, 2);
581    }
582 
583    radeon_enc_code_fixed_bits(enc, 0x0, 1);
584    radeon_enc_code_ue(enc, 0x1);
585    radeon_enc_code_ue(enc, 0x0);
586    radeon_enc_code_ue(enc, 0x0);
587 
588    radeon_enc_code_fixed_bits(enc, 0x0, 6);
589    radeon_enc_code_ue(enc, 0x0);
590    radeon_enc_code_fixed_bits(enc, 0x0, 1);
591    radeon_enc_code_fixed_bits(enc, 0x0, 1);
592 
593    radeon_enc_code_fixed_bits(enc, 0x1, 1);
594 
595    radeon_enc_byte_align(enc);
596    radeon_enc_flush_headers(enc);
597    *size_in_bytes = (enc->bits_output + 7) / 8;
598    RADEON_ENC_END();
599 }
600 
radeon_enc_nalu_aud_hevc(struct radeon_encoder * enc)601 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
602 {
603    RADEON_ENC_BEGIN(enc->cmd.nalu);
604    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
605    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
606    radeon_enc_reset(enc);
607    radeon_enc_set_emulation_prevention(enc, false);
608    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
609    radeon_enc_code_fixed_bits(enc, 0x0, 1);
610    radeon_enc_code_fixed_bits(enc, 35, 6);
611    radeon_enc_code_fixed_bits(enc, 0x0, 6);
612    radeon_enc_code_fixed_bits(enc, 0x1, 3);
613    radeon_enc_byte_align(enc);
614    radeon_enc_set_emulation_prevention(enc, true);
615    switch (enc->enc_pic.picture_type) {
616    case PIPE_H265_ENC_PICTURE_TYPE_I:
617    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
618       radeon_enc_code_fixed_bits(enc, 0x00, 3);
619       break;
620    case PIPE_H265_ENC_PICTURE_TYPE_P:
621       radeon_enc_code_fixed_bits(enc, 0x01, 3);
622       break;
623    case PIPE_H265_ENC_PICTURE_TYPE_B:
624       radeon_enc_code_fixed_bits(enc, 0x02, 3);
625       break;
626    default:
627       radeon_enc_code_fixed_bits(enc, 0x02, 3);
628    }
629 
630    radeon_enc_code_fixed_bits(enc, 0x1, 1);
631 
632    radeon_enc_byte_align(enc);
633    radeon_enc_flush_headers(enc);
634    *size_in_bytes = (enc->bits_output + 7) / 8;
635    RADEON_ENC_END();
636 }
637 
radeon_enc_slice_header(struct radeon_encoder * enc)638 static void radeon_enc_slice_header(struct radeon_encoder *enc)
639 {
640    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
641    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
642    unsigned int inst_index = 0;
643    unsigned int bit_index = 0;
644    unsigned int bits_copied = 0;
645    RADEON_ENC_BEGIN(enc->cmd.slice_header);
646    radeon_enc_reset(enc);
647    radeon_enc_set_emulation_prevention(enc, false);
648 
649    if (enc->enc_pic.is_idr)
650       radeon_enc_code_fixed_bits(enc, 0x65, 8);
651    else if (enc->enc_pic.not_referenced)
652       radeon_enc_code_fixed_bits(enc, 0x01, 8);
653    else
654       radeon_enc_code_fixed_bits(enc, 0x41, 8);
655 
656    radeon_enc_flush_headers(enc);
657    bit_index++;
658    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
659    num_bits[inst_index] = enc->bits_output - bits_copied;
660    bits_copied = enc->bits_output;
661    inst_index++;
662 
663    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
664    inst_index++;
665 
666    switch (enc->enc_pic.picture_type) {
667    case PIPE_H264_ENC_PICTURE_TYPE_I:
668    case PIPE_H264_ENC_PICTURE_TYPE_IDR:
669       radeon_enc_code_fixed_bits(enc, 0x08, 7);
670       break;
671    case PIPE_H264_ENC_PICTURE_TYPE_P:
672    case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
673       radeon_enc_code_fixed_bits(enc, 0x06, 5);
674       break;
675    case PIPE_H264_ENC_PICTURE_TYPE_B:
676       radeon_enc_code_fixed_bits(enc, 0x07, 5);
677       break;
678    default:
679       radeon_enc_code_fixed_bits(enc, 0x08, 7);
680    }
681 
682    radeon_enc_code_ue(enc, 0x0);
683    radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
684 
685    if (enc->enc_pic.h264_enc_params.input_picture_structure !=
686        RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
687       radeon_enc_code_fixed_bits(enc, 0x1, 1);
688       radeon_enc_code_fixed_bits(enc,
689                                  enc->enc_pic.h264_enc_params.input_picture_structure ==
690                                        RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
691                                     ? 1
692                                     : 0,
693                                  1);
694    }
695 
696    if (enc->enc_pic.is_idr)
697       radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
698 
699    enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
700 
701    if (enc->enc_pic.pic_order_cnt_type == 0)
702       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
703 
704    if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
705       radeon_enc_code_fixed_bits(enc, 0x0, 1);
706 
707       if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
708          radeon_enc_code_fixed_bits(enc, 0x1, 1);
709          radeon_enc_code_ue(enc, 0x0);
710          radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
711          radeon_enc_code_ue(enc, 0x3);
712       } else
713          radeon_enc_code_fixed_bits(enc, 0x0, 1);
714    }
715 
716    if (enc->enc_pic.is_idr) {
717       radeon_enc_code_fixed_bits(enc, 0x0, 1);
718       radeon_enc_code_fixed_bits(enc, 0x0, 1);
719    } else
720       radeon_enc_code_fixed_bits(enc, 0x0, 1);
721 
722    if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) &&
723        (enc->enc_pic.spec_misc.cabac_enable))
724       radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
725 
726    radeon_enc_flush_headers(enc);
727    bit_index++;
728    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
729    num_bits[inst_index] = enc->bits_output - bits_copied;
730    bits_copied = enc->bits_output;
731    inst_index++;
732 
733    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
734    inst_index++;
735 
736    radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
737 
738    if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
739       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
740       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
741    }
742 
743    radeon_enc_flush_headers(enc);
744    bit_index++;
745    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
746    num_bits[inst_index] = enc->bits_output - bits_copied;
747    bits_copied = enc->bits_output;
748    inst_index++;
749 
750    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
751 
752    for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
753       RADEON_ENC_CS(0x00000000);
754 
755    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
756       RADEON_ENC_CS(instruction[j]);
757       RADEON_ENC_CS(num_bits[j]);
758    }
759 
760    RADEON_ENC_END();
761 }
762 
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)763 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
764 {
765    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
766    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
767    unsigned int inst_index = 0;
768    unsigned int bit_index = 0;
769    unsigned int bits_copied = 0;
770    RADEON_ENC_BEGIN(enc->cmd.slice_header);
771    radeon_enc_reset(enc);
772    radeon_enc_set_emulation_prevention(enc, false);
773 
774    radeon_enc_code_fixed_bits(enc, 0x0, 1);
775    radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
776    radeon_enc_code_fixed_bits(enc, 0x0, 6);
777    radeon_enc_code_fixed_bits(enc, 0x1, 3);
778 
779    radeon_enc_flush_headers(enc);
780    bit_index++;
781    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
782    num_bits[inst_index] = enc->bits_output - bits_copied;
783    bits_copied = enc->bits_output;
784    inst_index++;
785 
786    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
787    inst_index++;
788 
789    if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
790       radeon_enc_code_fixed_bits(enc, 0x0, 1);
791 
792    radeon_enc_code_ue(enc, 0x0);
793 
794    radeon_enc_flush_headers(enc);
795    bit_index++;
796    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
797    num_bits[inst_index] = enc->bits_output - bits_copied;
798    bits_copied = enc->bits_output;
799    inst_index++;
800 
801    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
802    inst_index++;
803 
804    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
805    inst_index++;
806 
807    switch (enc->enc_pic.picture_type) {
808    case PIPE_H265_ENC_PICTURE_TYPE_I:
809    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
810       radeon_enc_code_ue(enc, 0x2);
811       break;
812    case PIPE_H265_ENC_PICTURE_TYPE_P:
813    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
814       radeon_enc_code_ue(enc, 0x1);
815       break;
816    case PIPE_H265_ENC_PICTURE_TYPE_B:
817       radeon_enc_code_ue(enc, 0x0);
818       break;
819    default:
820       radeon_enc_code_ue(enc, 0x1);
821    }
822 
823    if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
824       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
825       if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
826          radeon_enc_code_fixed_bits(enc, 0x1, 1);
827       else {
828          radeon_enc_code_fixed_bits(enc, 0x0, 1);
829          radeon_enc_code_fixed_bits(enc, 0x0, 1);
830          radeon_enc_code_ue(enc, 0x0);
831          radeon_enc_code_ue(enc, 0x0);
832       }
833    }
834 
835    if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
836        (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
837       radeon_enc_code_fixed_bits(enc, 0x0, 1);
838       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
839       radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
840    }
841 
842    radeon_enc_flush_headers(enc);
843    bit_index++;
844    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
845    num_bits[inst_index] = enc->bits_output - bits_copied;
846    bits_copied = enc->bits_output;
847    inst_index++;
848 
849    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
850    inst_index++;
851 
852    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
853        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
854       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
855                                  1);
856 
857       radeon_enc_flush_headers(enc);
858       bit_index++;
859       instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
860       num_bits[inst_index] = enc->bits_output - bits_copied;
861       bits_copied = enc->bits_output;
862       inst_index++;
863    }
864 
865    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
866 
867    for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
868       RADEON_ENC_CS(0x00000000);
869 
870    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
871       RADEON_ENC_CS(instruction[j]);
872       RADEON_ENC_CS(num_bits[j]);
873    }
874 
875    RADEON_ENC_END();
876 }
877 
radeon_enc_ctx(struct radeon_encoder * enc)878 static void radeon_enc_ctx(struct radeon_encoder *enc)
879 {
880    enc->enc_pic.ctx_buf.swizzle_mode = 0;
881    enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
882    enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
883    enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
884 
885    RADEON_ENC_BEGIN(enc->cmd.ctx);
886    RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
887    RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
888    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
889    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
890    RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
891    /* reconstructed_picture_1_luma_offset */
892    RADEON_ENC_CS(0x00000000);
893    /* reconstructed_picture_1_chroma_offset */
894    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
895    /* reconstructed_picture_2_luma_offset */
896    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
897    /* reconstructed_picture_2_chroma_offset */
898    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
899 
900    for (int i = 0; i < 136; i++)
901       RADEON_ENC_CS(0x00000000);
902 
903    RADEON_ENC_END();
904 }
905 
radeon_enc_bitstream(struct radeon_encoder * enc)906 static void radeon_enc_bitstream(struct radeon_encoder *enc)
907 {
908    enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
909    enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
910    enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
911 
912    RADEON_ENC_BEGIN(enc->cmd.bitstream);
913    RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
914    RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
915    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
916    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
917    RADEON_ENC_END();
918 }
919 
radeon_enc_feedback(struct radeon_encoder * enc)920 static void radeon_enc_feedback(struct radeon_encoder *enc)
921 {
922    enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
923    enc->enc_pic.fb_buf.feedback_buffer_size = 16;
924    enc->enc_pic.fb_buf.feedback_data_size = 40;
925 
926    RADEON_ENC_BEGIN(enc->cmd.feedback);
927    RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
928    RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
929    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
930    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
931    RADEON_ENC_END();
932 }
933 
radeon_enc_intra_refresh(struct radeon_encoder * enc)934 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
935 {
936    enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
937    enc->enc_pic.intra_ref.offset = 0;
938    enc->enc_pic.intra_ref.region_size = 0;
939 
940    RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
941    RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
942    RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
943    RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
944    RADEON_ENC_END();
945 }
946 
radeon_enc_rc_per_pic(struct radeon_encoder * enc)947 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
948 {
949    RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
950    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
951    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
952    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
953    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
954    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
955    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
956    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
957    RADEON_ENC_END();
958 }
959 
radeon_enc_encode_params(struct radeon_encoder * enc)960 static void radeon_enc_encode_params(struct radeon_encoder *enc)
961 {
962    switch (enc->enc_pic.picture_type) {
963    case PIPE_H264_ENC_PICTURE_TYPE_I:
964    case PIPE_H264_ENC_PICTURE_TYPE_IDR:
965       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
966       break;
967    case PIPE_H264_ENC_PICTURE_TYPE_P:
968       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
969       break;
970    case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
971       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
972       break;
973    case PIPE_H264_ENC_PICTURE_TYPE_B:
974       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
975       break;
976    default:
977       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
978    }
979 
980    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
981    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
982    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
983    enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
984 
985    if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
986       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
987    else
988       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
989 
990    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
991 
992    RADEON_ENC_BEGIN(enc->cmd.enc_params);
993    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
994    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
995    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
996    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
997    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
998    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
999    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1000    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1001    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1002    RADEON_ENC_END();
1003 }
1004 
radeon_enc_encode_params_hevc(struct radeon_encoder * enc)1005 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1006 {
1007    switch (enc->enc_pic.picture_type) {
1008    case PIPE_H265_ENC_PICTURE_TYPE_I:
1009    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
1010       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1011       break;
1012    case PIPE_H265_ENC_PICTURE_TYPE_P:
1013       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1014       break;
1015    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
1016       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1017       break;
1018    case PIPE_H265_ENC_PICTURE_TYPE_B:
1019       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1020       break;
1021    default:
1022       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1023    }
1024 
1025    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1026    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1027    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1028    enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1029 
1030    if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1031       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1032    else
1033       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1034 
1035    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1036 
1037    RADEON_ENC_BEGIN(enc->cmd.enc_params);
1038    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1039    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1040    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1041    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1042    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1043    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1044    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1045    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1046    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1047    RADEON_ENC_END();
1048 }
1049 
radeon_enc_encode_params_h264(struct radeon_encoder * enc)1050 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1051 {
1052    enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1053    enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1054    enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1055    enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1056 
1057    RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1058    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1059    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1060    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1061    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1062    RADEON_ENC_END();
1063 }
1064 
radeon_enc_op_init(struct radeon_encoder * enc)1065 static void radeon_enc_op_init(struct radeon_encoder *enc)
1066 {
1067    RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1068    RADEON_ENC_END();
1069 }
1070 
radeon_enc_op_close(struct radeon_encoder * enc)1071 static void radeon_enc_op_close(struct radeon_encoder *enc)
1072 {
1073    RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1074    RADEON_ENC_END();
1075 }
1076 
radeon_enc_op_enc(struct radeon_encoder * enc)1077 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1078 {
1079    RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1080    RADEON_ENC_END();
1081 }
1082 
radeon_enc_op_init_rc(struct radeon_encoder * enc)1083 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1084 {
1085    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1086    RADEON_ENC_END();
1087 }
1088 
radeon_enc_op_init_rc_vbv(struct radeon_encoder * enc)1089 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1090 {
1091    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1092    RADEON_ENC_END();
1093 }
1094 
radeon_enc_op_speed(struct radeon_encoder * enc)1095 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1096 {
1097    RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1098    RADEON_ENC_END();
1099 }
1100 
begin(struct radeon_encoder * enc)1101 static void begin(struct radeon_encoder *enc)
1102 {
1103    enc->session_info(enc);
1104    enc->total_task_size = 0;
1105    enc->task_info(enc, enc->need_feedback);
1106    enc->op_init(enc);
1107 
1108    enc->session_init(enc);
1109    enc->slice_control(enc);
1110    enc->spec_misc(enc);
1111    enc->deblocking_filter(enc);
1112 
1113    enc->layer_control(enc);
1114    enc->rc_session_init(enc);
1115    enc->quality_params(enc);
1116    enc->layer_select(enc);
1117    enc->rc_layer_init(enc);
1118    enc->layer_select(enc);
1119    enc->rc_per_pic(enc);
1120    enc->op_init_rc(enc);
1121    enc->op_init_rc_vbv(enc);
1122    *enc->p_task_size = (enc->total_task_size);
1123 }
1124 
radeon_enc_headers_h264(struct radeon_encoder * enc)1125 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1126 {
1127    if (enc->enc_pic.is_idr) {
1128       enc->nalu_sps(enc);
1129       enc->nalu_pps(enc);
1130    }
1131    enc->slice_header(enc);
1132    enc->encode_params(enc);
1133    enc->encode_params_codec_spec(enc);
1134 }
1135 
radeon_enc_headers_hevc(struct radeon_encoder * enc)1136 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1137 {
1138    enc->nalu_aud(enc);
1139    if (enc->enc_pic.is_idr) {
1140       enc->nalu_vps(enc);
1141       enc->nalu_pps(enc);
1142       enc->nalu_sps(enc);
1143    }
1144    enc->slice_header(enc);
1145    enc->encode_params(enc);
1146 }
1147 
encode(struct radeon_encoder * enc)1148 static void encode(struct radeon_encoder *enc)
1149 {
1150    enc->session_info(enc);
1151    enc->total_task_size = 0;
1152    enc->task_info(enc, enc->need_feedback);
1153 
1154    enc->encode_headers(enc);
1155    enc->ctx(enc);
1156    enc->bitstream(enc);
1157    enc->feedback(enc);
1158    enc->intra_refresh(enc);
1159 
1160    enc->op_speed(enc);
1161    enc->op_enc(enc);
1162    *enc->p_task_size = (enc->total_task_size);
1163 }
1164 
destroy(struct radeon_encoder * enc)1165 static void destroy(struct radeon_encoder *enc)
1166 {
1167    enc->session_info(enc);
1168    enc->total_task_size = 0;
1169    enc->task_info(enc, enc->need_feedback);
1170    enc->op_close(enc);
1171    *enc->p_task_size = (enc->total_task_size);
1172 }
1173 
radeon_enc_1_2_init(struct radeon_encoder * enc)1174 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1175 {
1176    enc->begin = begin;
1177    enc->encode = encode;
1178    enc->destroy = destroy;
1179    enc->session_info = radeon_enc_session_info;
1180    enc->task_info = radeon_enc_task_info;
1181    enc->layer_control = radeon_enc_layer_control;
1182    enc->layer_select = radeon_enc_layer_select;
1183    enc->rc_session_init = radeon_enc_rc_session_init;
1184    enc->rc_layer_init = radeon_enc_rc_layer_init;
1185    enc->quality_params = radeon_enc_quality_params;
1186    enc->ctx = radeon_enc_ctx;
1187    enc->bitstream = radeon_enc_bitstream;
1188    enc->feedback = radeon_enc_feedback;
1189    enc->intra_refresh = radeon_enc_intra_refresh;
1190    enc->rc_per_pic = radeon_enc_rc_per_pic;
1191    enc->encode_params = radeon_enc_encode_params;
1192    enc->op_init = radeon_enc_op_init;
1193    enc->op_close = radeon_enc_op_close;
1194    enc->op_enc = radeon_enc_op_enc;
1195    enc->op_init_rc = radeon_enc_op_init_rc;
1196    enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1197    enc->op_speed = radeon_enc_op_speed;
1198 
1199    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1200       enc->session_init = radeon_enc_session_init;
1201       enc->slice_control = radeon_enc_slice_control;
1202       enc->spec_misc = radeon_enc_spec_misc;
1203       enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1204       enc->nalu_sps = radeon_enc_nalu_sps;
1205       enc->nalu_pps = radeon_enc_nalu_pps;
1206       enc->slice_header = radeon_enc_slice_header;
1207       enc->encode_params = radeon_enc_encode_params;
1208       enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1209       enc->encode_headers = radeon_enc_headers_h264;
1210    } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1211       enc->session_init = radeon_enc_session_init_hevc;
1212       enc->slice_control = radeon_enc_slice_control_hevc;
1213       enc->spec_misc = radeon_enc_spec_misc_hevc;
1214       enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1215       enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1216       enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1217       enc->nalu_vps = radeon_enc_nalu_vps;
1218       enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1219       enc->slice_header = radeon_enc_slice_header_hevc;
1220       enc->encode_params = radeon_enc_encode_params_hevc;
1221       enc->encode_headers = radeon_enc_headers_hevc;
1222    }
1223 
1224    enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1225    enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1226    enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1227    enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1228    enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1229    enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1230    enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1231    enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1232    enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1233    enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1234    enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1235    enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1236    enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1237    enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1238    enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1239    enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1240    enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1241    enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1242    enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1243    enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1244    enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1245    enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1246    enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1247 
1248    enc->enc_pic.session_info.interface_version =
1249       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1250        (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1251 }
1252