1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Calling Convention Implementation Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, 10 MVT LocVT, CCValAssign::LocInfo LocInfo, 11 ISD::ArgFlagsTy ArgFlags, CCState &State); 12bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, 13 MVT LocVT, CCValAssign::LocInfo LocInfo, 14 ISD::ArgFlagsTy ArgFlags, CCState &State); 15bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, 16 MVT LocVT, CCValAssign::LocInfo LocInfo, 17 ISD::ArgFlagsTy ArgFlags, CCState &State); 18bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, 19 MVT LocVT, CCValAssign::LocInfo LocInfo, 20 ISD::ArgFlagsTy ArgFlags, CCState &State); 21bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT, 22 MVT LocVT, CCValAssign::LocInfo LocInfo, 23 ISD::ArgFlagsTy ArgFlags, CCState &State); 24bool llvm::CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, 25 MVT LocVT, CCValAssign::LocInfo LocInfo, 26 ISD::ArgFlagsTy ArgFlags, CCState &State); 27bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, 28 MVT LocVT, CCValAssign::LocInfo LocInfo, 29 ISD::ArgFlagsTy ArgFlags, CCState &State); 30bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, 31 MVT LocVT, CCValAssign::LocInfo LocInfo, 32 ISD::ArgFlagsTy ArgFlags, CCState &State); 33bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, 34 MVT LocVT, CCValAssign::LocInfo LocInfo, 35 ISD::ArgFlagsTy ArgFlags, CCState &State); 36bool llvm::RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, 37 MVT LocVT, CCValAssign::LocInfo LocInfo, 38 ISD::ArgFlagsTy ArgFlags, CCState &State); 39 40 41bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, 42 MVT LocVT, CCValAssign::LocInfo LocInfo, 43 ISD::ArgFlagsTy ArgFlags, CCState &State) { 44 45 if (LocVT == MVT::iPTR) { 46 LocVT = MVT::i64; 47 LocInfo = CCValAssign::BCvt; 48 } 49 50 if (LocVT == MVT::v2f32) { 51 LocVT = MVT::v2i32; 52 LocInfo = CCValAssign::BCvt; 53 } 54 55 if (LocVT == MVT::v2f64 || 56 LocVT == MVT::v4f32) { 57 LocVT = MVT::v2i64; 58 LocInfo = CCValAssign::BCvt; 59 } 60 61 if (State.getMachineFunction().getDataLayout().isBigEndian()) { 62 if (LocVT == MVT::v2i32 || 63 LocVT == MVT::v2f32 || 64 LocVT == MVT::v4i16 || 65 LocVT == MVT::v4f16 || 66 LocVT == MVT::v8i8) { 67 LocVT = MVT::f64; 68 LocInfo = CCValAssign::BCvt; 69 } 70 } 71 72 if (State.getMachineFunction().getDataLayout().isBigEndian()) { 73 if (LocVT == MVT::v2i64 || 74 LocVT == MVT::v2f64 || 75 LocVT == MVT::v4i32 || 76 LocVT == MVT::v4f32 || 77 LocVT == MVT::v8i16 || 78 LocVT == MVT::v8f16 || 79 LocVT == MVT::v16i8) { 80 LocVT = MVT::f128; 81 LocInfo = CCValAssign::BCvt; 82 } 83 } 84 85 if (ArgFlags.isInReg()) { 86 if (LocVT == MVT::i64) { 87 if (ArgFlags.isSRet()) { 88 if (LocVT == MVT::i64) { 89 static const MCPhysReg RegList1[] = { 90 AArch64::X0, AArch64::X1 91 }; 92 static const MCPhysReg RegList2[] = { 93 AArch64::W0, AArch64::W1 94 }; 95 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 96 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 97 return false; 98 } 99 } 100 } 101 } 102 } 103 104 if (ArgFlags.isSRet()) { 105 if (LocVT == MVT::i64) { 106 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) { 107 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 108 return false; 109 } 110 } 111 } 112 113 if (ArgFlags.isByVal()) { 114 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 115 return false; 116 } 117 118 if (ArgFlags.isNest()) { 119 if (unsigned Reg = State.AllocateReg(AArch64::X18)) { 120 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 121 return false; 122 } 123 } 124 125 if (ArgFlags.isSwiftSelf()) { 126 if (LocVT == MVT::i64) { 127 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) { 128 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 129 return false; 130 } 131 } 132 } 133 134 if (ArgFlags.isSwiftError()) { 135 if (LocVT == MVT::i64) { 136 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) { 137 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 138 return false; 139 } 140 } 141 } 142 143 if (ArgFlags.isInConsecutiveRegs()) { 144 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 145 return false; 146 } 147 148 if (LocVT == MVT::nxv16i8 || 149 LocVT == MVT::nxv8i16 || 150 LocVT == MVT::nxv4i32 || 151 LocVT == MVT::nxv2i64 || 152 LocVT == MVT::nxv2f16 || 153 LocVT == MVT::nxv4f16 || 154 LocVT == MVT::nxv8f16 || 155 LocVT == MVT::nxv2f32 || 156 LocVT == MVT::nxv4f32 || 157 LocVT == MVT::nxv2f64) { 158 static const MCPhysReg RegList3[] = { 159 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 160 }; 161 if (unsigned Reg = State.AllocateReg(RegList3)) { 162 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 163 return false; 164 } 165 } 166 167 if (LocVT == MVT::nxv16i8 || 168 LocVT == MVT::nxv8i16 || 169 LocVT == MVT::nxv4i32 || 170 LocVT == MVT::nxv2i64 || 171 LocVT == MVT::nxv2f16 || 172 LocVT == MVT::nxv4f16 || 173 LocVT == MVT::nxv8f16 || 174 LocVT == MVT::nxv2f32 || 175 LocVT == MVT::nxv4f32 || 176 LocVT == MVT::nxv2f64) { 177 LocVT = MVT::i64; 178 LocInfo = CCValAssign::Indirect; 179 } 180 181 if (LocVT == MVT::nxv2i1 || 182 LocVT == MVT::nxv4i1 || 183 LocVT == MVT::nxv8i1 || 184 LocVT == MVT::nxv16i1) { 185 static const MCPhysReg RegList4[] = { 186 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3 187 }; 188 if (unsigned Reg = State.AllocateReg(RegList4)) { 189 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 190 return false; 191 } 192 } 193 194 if (LocVT == MVT::nxv2i1 || 195 LocVT == MVT::nxv4i1 || 196 LocVT == MVT::nxv8i1 || 197 LocVT == MVT::nxv16i1) { 198 LocVT = MVT::i64; 199 LocInfo = CCValAssign::Indirect; 200 } 201 202 if (LocVT == MVT::i1 || 203 LocVT == MVT::i8 || 204 LocVT == MVT::i16) { 205 LocVT = MVT::i32; 206 if (ArgFlags.isSExt()) 207 LocInfo = CCValAssign::SExt; 208 else if (ArgFlags.isZExt()) 209 LocInfo = CCValAssign::ZExt; 210 else 211 LocInfo = CCValAssign::AExt; 212 } 213 214 if (LocVT == MVT::i32) { 215 static const MCPhysReg RegList5[] = { 216 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 217 }; 218 static const MCPhysReg RegList6[] = { 219 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 220 }; 221 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { 222 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 223 return false; 224 } 225 } 226 227 if (LocVT == MVT::i64) { 228 if (ArgFlags.isSplit()) { 229 static const MCPhysReg RegList7[] = { 230 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 231 }; 232 static const MCPhysReg RegList8[] = { 233 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 234 }; 235 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 236 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 237 return false; 238 } 239 } 240 } 241 242 if (LocVT == MVT::i64) { 243 if (ArgFlags.isSplit()) { 244 static const MCPhysReg ShadowRegList9[] = { 245 AArch64::X7 246 }; 247 unsigned Offset10 = State.AllocateStack(8, 16, ShadowRegList9); 248 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 249 return false; 250 } 251 } 252 253 if (LocVT == MVT::i64) { 254 static const MCPhysReg RegList11[] = { 255 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 256 }; 257 static const MCPhysReg RegList12[] = { 258 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 259 }; 260 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { 261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 262 return false; 263 } 264 } 265 266 if (LocVT == MVT::f16) { 267 static const MCPhysReg RegList13[] = { 268 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 269 }; 270 static const MCPhysReg RegList14[] = { 271 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 272 }; 273 if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) { 274 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 275 return false; 276 } 277 } 278 279 if (LocVT == MVT::f32) { 280 static const MCPhysReg RegList15[] = { 281 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 282 }; 283 static const MCPhysReg RegList16[] = { 284 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 285 }; 286 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) { 287 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 288 return false; 289 } 290 } 291 292 if (LocVT == MVT::f64) { 293 static const MCPhysReg RegList17[] = { 294 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 295 }; 296 static const MCPhysReg RegList18[] = { 297 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 298 }; 299 if (unsigned Reg = State.AllocateReg(RegList17, RegList18)) { 300 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 301 return false; 302 } 303 } 304 305 if (LocVT == MVT::v1i64 || 306 LocVT == MVT::v2i32 || 307 LocVT == MVT::v4i16 || 308 LocVT == MVT::v8i8 || 309 LocVT == MVT::v1f64 || 310 LocVT == MVT::v2f32 || 311 LocVT == MVT::v4f16) { 312 static const MCPhysReg RegList19[] = { 313 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 314 }; 315 static const MCPhysReg RegList20[] = { 316 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 317 }; 318 if (unsigned Reg = State.AllocateReg(RegList19, RegList20)) { 319 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 320 return false; 321 } 322 } 323 324 if (LocVT == MVT::f128 || 325 LocVT == MVT::v2i64 || 326 LocVT == MVT::v4i32 || 327 LocVT == MVT::v8i16 || 328 LocVT == MVT::v16i8 || 329 LocVT == MVT::v4f32 || 330 LocVT == MVT::v2f64 || 331 LocVT == MVT::v8f16) { 332 static const MCPhysReg RegList21[] = { 333 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 334 }; 335 if (unsigned Reg = State.AllocateReg(RegList21)) { 336 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 337 return false; 338 } 339 } 340 341 if (LocVT == MVT::i1 || 342 LocVT == MVT::i8 || 343 LocVT == MVT::i16 || 344 LocVT == MVT::f16) { 345 unsigned Offset22 = State.AllocateStack(8, 8); 346 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo)); 347 return false; 348 } 349 350 if (LocVT == MVT::i32 || 351 LocVT == MVT::f32) { 352 unsigned Offset23 = State.AllocateStack(8, 8); 353 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset23, LocVT, LocInfo)); 354 return false; 355 } 356 357 if (LocVT == MVT::i64 || 358 LocVT == MVT::f64 || 359 LocVT == MVT::v1f64 || 360 LocVT == MVT::v2f32 || 361 LocVT == MVT::v1i64 || 362 LocVT == MVT::v2i32 || 363 LocVT == MVT::v4i16 || 364 LocVT == MVT::v8i8 || 365 LocVT == MVT::v4f16) { 366 unsigned Offset24 = State.AllocateStack(8, 8); 367 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset24, LocVT, LocInfo)); 368 return false; 369 } 370 371 if (LocVT == MVT::f128 || 372 LocVT == MVT::v2i64 || 373 LocVT == MVT::v4i32 || 374 LocVT == MVT::v8i16 || 375 LocVT == MVT::v16i8 || 376 LocVT == MVT::v4f32 || 377 LocVT == MVT::v2f64 || 378 LocVT == MVT::v8f16) { 379 unsigned Offset25 = State.AllocateStack(16, 16); 380 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset25, LocVT, LocInfo)); 381 return false; 382 } 383 384 return true; // CC didn't match. 385} 386 387 388bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, 389 MVT LocVT, CCValAssign::LocInfo LocInfo, 390 ISD::ArgFlagsTy ArgFlags, CCState &State) { 391 392 if (LocVT == MVT::iPTR) { 393 LocVT = MVT::i64; 394 LocInfo = CCValAssign::BCvt; 395 } 396 397 if (LocVT == MVT::v2f32) { 398 LocVT = MVT::v2i32; 399 LocInfo = CCValAssign::BCvt; 400 } 401 402 if (LocVT == MVT::v2f64 || 403 LocVT == MVT::v4f32 || 404 LocVT == MVT::f128) { 405 LocVT = MVT::v2i64; 406 LocInfo = CCValAssign::BCvt; 407 } 408 409 if (ArgFlags.isSRet()) { 410 if (LocVT == MVT::i64) { 411 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) { 412 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 413 return false; 414 } 415 } 416 } 417 418 if (ArgFlags.isByVal()) { 419 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 420 return false; 421 } 422 423 if (ArgFlags.isSwiftSelf()) { 424 if (LocVT == MVT::i64) { 425 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) { 426 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 427 return false; 428 } 429 } 430 } 431 432 if (ArgFlags.isSwiftError()) { 433 if (LocVT == MVT::i64) { 434 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) { 435 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 436 return false; 437 } 438 } 439 } 440 441 if (ArgFlags.isInConsecutiveRegs()) { 442 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 443 return false; 444 } 445 446 if (LocVT == MVT::i1 || 447 LocVT == MVT::i8 || 448 LocVT == MVT::i16) { 449 LocVT = MVT::i32; 450 if (ArgFlags.isSExt()) 451 LocInfo = CCValAssign::SExt; 452 else if (ArgFlags.isZExt()) 453 LocInfo = CCValAssign::ZExt; 454 else 455 LocInfo = CCValAssign::AExt; 456 } 457 458 if (LocVT == MVT::i32) { 459 static const MCPhysReg RegList1[] = { 460 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 461 }; 462 static const MCPhysReg RegList2[] = { 463 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 464 }; 465 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 466 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 467 return false; 468 } 469 } 470 471 if (LocVT == MVT::i64) { 472 if (ArgFlags.isSplit()) { 473 static const MCPhysReg RegList3[] = { 474 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6 475 }; 476 static const MCPhysReg RegList4[] = { 477 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6 478 }; 479 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { 480 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 481 return false; 482 } 483 } 484 } 485 486 if (LocVT == MVT::i64) { 487 if (ArgFlags.isSplit()) { 488 static const MCPhysReg ShadowRegList5[] = { 489 AArch64::X7 490 }; 491 unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); 492 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 493 return false; 494 } 495 } 496 497 if (LocVT == MVT::i64) { 498 static const MCPhysReg RegList7[] = { 499 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 500 }; 501 static const MCPhysReg RegList8[] = { 502 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 503 }; 504 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 505 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 506 return false; 507 } 508 } 509 510 if (LocVT == MVT::f16) { 511 static const MCPhysReg RegList9[] = { 512 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 513 }; 514 static const MCPhysReg RegList10[] = { 515 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 516 }; 517 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) { 518 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 519 return false; 520 } 521 } 522 523 if (LocVT == MVT::f32) { 524 static const MCPhysReg RegList11[] = { 525 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 526 }; 527 static const MCPhysReg RegList12[] = { 528 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 529 }; 530 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { 531 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 532 return false; 533 } 534 } 535 536 if (LocVT == MVT::f64) { 537 static const MCPhysReg RegList13[] = { 538 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 539 }; 540 static const MCPhysReg RegList14[] = { 541 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 542 }; 543 if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) { 544 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 545 return false; 546 } 547 } 548 549 if (LocVT == MVT::v1i64 || 550 LocVT == MVT::v2i32 || 551 LocVT == MVT::v4i16 || 552 LocVT == MVT::v8i8 || 553 LocVT == MVT::v1f64 || 554 LocVT == MVT::v2f32 || 555 LocVT == MVT::v4f16) { 556 static const MCPhysReg RegList15[] = { 557 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 558 }; 559 static const MCPhysReg RegList16[] = { 560 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 561 }; 562 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) { 563 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 564 return false; 565 } 566 } 567 568 if (LocVT == MVT::v2i64 || 569 LocVT == MVT::v4i32 || 570 LocVT == MVT::v8i16 || 571 LocVT == MVT::v16i8 || 572 LocVT == MVT::v4f32 || 573 LocVT == MVT::v2f64 || 574 LocVT == MVT::v8f16) { 575 static const MCPhysReg RegList17[] = { 576 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 577 }; 578 if (unsigned Reg = State.AllocateReg(RegList17)) { 579 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 580 return false; 581 } 582 } 583 584 if (ValVT == MVT::i1 || ValVT == MVT::i8) { 585 unsigned Offset18 = State.AllocateStack(1, 1); 586 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); 587 return false; 588 } 589 590 if (ValVT == MVT::i16 || ValVT == MVT::f16) { 591 unsigned Offset19 = State.AllocateStack(2, 2); 592 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); 593 return false; 594 } 595 596 if (LocVT == MVT::i32 || 597 LocVT == MVT::f32) { 598 unsigned Offset20 = State.AllocateStack(4, 4); 599 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); 600 return false; 601 } 602 603 if (ArgFlags.isPointer()) { 604 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { 605 LocVT = MVT::i32; 606 LocInfo = CCValAssign::Trunc; 607 } 608 } 609 610 if (ArgFlags.isPointer()) { 611 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { 612 unsigned Offset21 = State.AllocateStack(4, 4); 613 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); 614 return false; 615 } 616 } 617 618 if (LocVT == MVT::i64 || 619 LocVT == MVT::f64 || 620 LocVT == MVT::v1f64 || 621 LocVT == MVT::v2f32 || 622 LocVT == MVT::v1i64 || 623 LocVT == MVT::v2i32 || 624 LocVT == MVT::v4i16 || 625 LocVT == MVT::v8i8 || 626 LocVT == MVT::v4f16) { 627 unsigned Offset22 = State.AllocateStack(8, 8); 628 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo)); 629 return false; 630 } 631 632 if (LocVT == MVT::v2i64 || 633 LocVT == MVT::v4i32 || 634 LocVT == MVT::v8i16 || 635 LocVT == MVT::v16i8 || 636 LocVT == MVT::v4f32 || 637 LocVT == MVT::v2f64 || 638 LocVT == MVT::v8f16) { 639 unsigned Offset23 = State.AllocateStack(16, 16); 640 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset23, LocVT, LocInfo)); 641 return false; 642 } 643 644 return true; // CC didn't match. 645} 646 647 648bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, 649 MVT LocVT, CCValAssign::LocInfo LocInfo, 650 ISD::ArgFlagsTy ArgFlags, CCState &State) { 651 652 if (LocVT == MVT::v2f32) { 653 LocVT = MVT::v2i32; 654 LocInfo = CCValAssign::BCvt; 655 } 656 657 if (LocVT == MVT::v2f64 || 658 LocVT == MVT::v4f32 || 659 LocVT == MVT::f128) { 660 LocVT = MVT::v2i64; 661 LocInfo = CCValAssign::BCvt; 662 } 663 664 if (LocVT == MVT::i8 || 665 LocVT == MVT::i16) { 666 LocVT = MVT::i32; 667 if (ArgFlags.isSExt()) 668 LocInfo = CCValAssign::SExt; 669 else if (ArgFlags.isZExt()) 670 LocInfo = CCValAssign::ZExt; 671 else 672 LocInfo = CCValAssign::AExt; 673 } 674 675 if (LocVT == MVT::f16) { 676 LocVT = MVT::f32; 677 LocInfo = CCValAssign::FPExt; 678 } 679 680 if (ArgFlags.isPointer()) { 681 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { 682 LocVT = MVT::i32; 683 LocInfo = CCValAssign::Trunc; 684 } 685 } 686 687 if (LocVT == MVT::i32 || 688 LocVT == MVT::f32) { 689 unsigned Offset1 = State.AllocateStack(4, 4); 690 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 691 return false; 692 } 693 694 if (LocVT == MVT::i64) { 695 if (ArgFlags.isSplit()) { 696 unsigned Offset2 = State.AllocateStack(8, 16); 697 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 698 return false; 699 } 700 } 701 702 if (LocVT == MVT::i64 || 703 LocVT == MVT::f64 || 704 LocVT == MVT::v1i64 || 705 LocVT == MVT::v2i32 || 706 LocVT == MVT::v4i16 || 707 LocVT == MVT::v8i8 || 708 LocVT == MVT::v1f64 || 709 LocVT == MVT::v2f32 || 710 LocVT == MVT::v4f16) { 711 unsigned Offset3 = State.AllocateStack(8, 8); 712 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 713 return false; 714 } 715 716 if (LocVT == MVT::v2i64 || 717 LocVT == MVT::v4i32 || 718 LocVT == MVT::v8i16 || 719 LocVT == MVT::v16i8 || 720 LocVT == MVT::v4f32 || 721 LocVT == MVT::v2f64 || 722 LocVT == MVT::v8f16) { 723 unsigned Offset4 = State.AllocateStack(16, 16); 724 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); 725 return false; 726 } 727 728 return true; // CC didn't match. 729} 730 731 732bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, 733 MVT LocVT, CCValAssign::LocInfo LocInfo, 734 ISD::ArgFlagsTy ArgFlags, CCState &State) { 735 736 if (LocVT == MVT::iPTR) { 737 LocVT = MVT::i64; 738 LocInfo = CCValAssign::BCvt; 739 } 740 741 if (LocVT == MVT::v2f32) { 742 LocVT = MVT::v2i32; 743 LocInfo = CCValAssign::BCvt; 744 } 745 746 if (LocVT == MVT::v2f64 || 747 LocVT == MVT::v4f32 || 748 LocVT == MVT::f128) { 749 LocVT = MVT::v2i64; 750 LocInfo = CCValAssign::BCvt; 751 } 752 753 if (ArgFlags.isInConsecutiveRegs()) { 754 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 755 return false; 756 } 757 758 if (LocVT == MVT::i8 || 759 LocVT == MVT::i16 || 760 LocVT == MVT::i32) { 761 LocVT = MVT::i64; 762 if (ArgFlags.isSExt()) 763 LocInfo = CCValAssign::SExt; 764 else if (ArgFlags.isZExt()) 765 LocInfo = CCValAssign::ZExt; 766 else 767 LocInfo = CCValAssign::AExt; 768 } 769 770 if (LocVT == MVT::f16 || 771 LocVT == MVT::f32) { 772 LocVT = MVT::f64; 773 LocInfo = CCValAssign::FPExt; 774 } 775 776 if (LocVT == MVT::i64) { 777 if (ArgFlags.isSplit()) { 778 unsigned Offset1 = State.AllocateStack(8, 16); 779 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 780 return false; 781 } 782 } 783 784 if (LocVT == MVT::i64 || 785 LocVT == MVT::f64 || 786 LocVT == MVT::v1i64 || 787 LocVT == MVT::v2i32 || 788 LocVT == MVT::v4i16 || 789 LocVT == MVT::v8i8 || 790 LocVT == MVT::v1f64 || 791 LocVT == MVT::v2f32 || 792 LocVT == MVT::v4f16) { 793 unsigned Offset2 = State.AllocateStack(8, 8); 794 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 795 return false; 796 } 797 798 if (LocVT == MVT::v2i64 || 799 LocVT == MVT::v4i32 || 800 LocVT == MVT::v8i16 || 801 LocVT == MVT::v16i8 || 802 LocVT == MVT::v4f32 || 803 LocVT == MVT::v2f64 || 804 LocVT == MVT::v8f16) { 805 unsigned Offset3 = State.AllocateStack(16, 16); 806 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 807 return false; 808 } 809 810 return true; // CC didn't match. 811} 812 813 814bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT, 815 MVT LocVT, CCValAssign::LocInfo LocInfo, 816 ISD::ArgFlagsTy ArgFlags, CCState &State) { 817 818 if (LocVT == MVT::iPTR) { 819 LocVT = MVT::i64; 820 LocInfo = CCValAssign::BCvt; 821 } 822 823 if (LocVT == MVT::v1i64 || 824 LocVT == MVT::v2i32 || 825 LocVT == MVT::v4i16 || 826 LocVT == MVT::v8i8 || 827 LocVT == MVT::v2f32) { 828 LocVT = MVT::f64; 829 LocInfo = CCValAssign::BCvt; 830 } 831 832 if (LocVT == MVT::v2i64 || 833 LocVT == MVT::v4i32 || 834 LocVT == MVT::v8i16 || 835 LocVT == MVT::v16i8 || 836 LocVT == MVT::v4f32 || 837 LocVT == MVT::f128) { 838 LocVT = MVT::v2f64; 839 LocInfo = CCValAssign::BCvt; 840 } 841 842 if (LocVT == MVT::v2f64) { 843 static const MCPhysReg RegList1[] = { 844 AArch64::Q4, AArch64::Q5 845 }; 846 if (unsigned Reg = State.AllocateReg(RegList1)) { 847 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 848 return false; 849 } 850 } 851 852 if (LocVT == MVT::f32) { 853 static const MCPhysReg RegList2[] = { 854 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11 855 }; 856 if (unsigned Reg = State.AllocateReg(RegList2)) { 857 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 858 return false; 859 } 860 } 861 862 if (LocVT == MVT::f64) { 863 static const MCPhysReg RegList3[] = { 864 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15 865 }; 866 if (unsigned Reg = State.AllocateReg(RegList3)) { 867 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 868 return false; 869 } 870 } 871 872 if (LocVT == MVT::i8 || 873 LocVT == MVT::i16 || 874 LocVT == MVT::i32) { 875 LocVT = MVT::i64; 876 if (ArgFlags.isSExt()) 877 LocInfo = CCValAssign::SExt; 878 else if (ArgFlags.isZExt()) 879 LocInfo = CCValAssign::ZExt; 880 else 881 LocInfo = CCValAssign::AExt; 882 } 883 884 if (LocVT == MVT::i64) { 885 static const MCPhysReg RegList4[] = { 886 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 887 }; 888 if (unsigned Reg = State.AllocateReg(RegList4)) { 889 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 890 return false; 891 } 892 } 893 894 return true; // CC didn't match. 895} 896 897 898bool llvm::CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, 899 MVT LocVT, CCValAssign::LocInfo LocInfo, 900 ISD::ArgFlagsTy ArgFlags, CCState &State) { 901 902 if (LocVT == MVT::i1 || 903 LocVT == MVT::i8 || 904 LocVT == MVT::i16) { 905 LocVT = MVT::i32; 906 if (ArgFlags.isSExt()) 907 LocInfo = CCValAssign::SExt; 908 else if (ArgFlags.isZExt()) 909 LocInfo = CCValAssign::ZExt; 910 else 911 LocInfo = CCValAssign::AExt; 912 } 913 914 if (LocVT == MVT::i32) { 915 if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) { 916 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 917 return false; 918 } 919 } 920 921 if (LocVT == MVT::i64) { 922 if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) { 923 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 924 return false; 925 } 926 } 927 928 if (LocVT == MVT::i32 || 929 LocVT == MVT::f32) { 930 unsigned Offset1 = State.AllocateStack(4, 4); 931 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 932 return false; 933 } 934 935 if (LocVT == MVT::i64 || 936 LocVT == MVT::f64) { 937 unsigned Offset2 = State.AllocateStack(8, 8); 938 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 939 return false; 940 } 941 942 return true; // CC didn't match. 943} 944 945 946bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, 947 MVT LocVT, CCValAssign::LocInfo LocInfo, 948 ISD::ArgFlagsTy ArgFlags, CCState &State) { 949 950 if (LocVT == MVT::i64) { 951 if (unsigned Reg = State.AllocateReg(AArch64::X15)) { 952 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 953 return false; 954 } 955 } 956 957 return true; // CC didn't match. 958} 959 960 961bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, 962 MVT LocVT, CCValAssign::LocInfo LocInfo, 963 ISD::ArgFlagsTy ArgFlags, CCState &State) { 964 965 if (LocVT == MVT::f16 || 966 LocVT == MVT::f32) { 967 LocVT = MVT::f64; 968 LocInfo = CCValAssign::FPExt; 969 } 970 971 if (LocVT == MVT::f64) { 972 LocVT = MVT::i64; 973 LocInfo = CCValAssign::BCvt; 974 } 975 976 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 977 return false; 978 979 return true; // CC didn't match. 980} 981 982 983bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, 984 MVT LocVT, CCValAssign::LocInfo LocInfo, 985 ISD::ArgFlagsTy ArgFlags, CCState &State) { 986 987 if (LocVT == MVT::iPTR) { 988 LocVT = MVT::i64; 989 LocInfo = CCValAssign::BCvt; 990 } 991 992 if (LocVT == MVT::v2f32) { 993 LocVT = MVT::v2i32; 994 LocInfo = CCValAssign::BCvt; 995 } 996 997 if (LocVT == MVT::v2f64 || 998 LocVT == MVT::v4f32) { 999 LocVT = MVT::v2i64; 1000 LocInfo = CCValAssign::BCvt; 1001 } 1002 1003 if (ArgFlags.isInConsecutiveRegs()) { 1004 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1005 return false; 1006 } 1007 1008 if (ArgFlags.isSwiftError()) { 1009 if (LocVT == MVT::i64) { 1010 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) { 1011 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1012 return false; 1013 } 1014 } 1015 } 1016 1017 if (State.getMachineFunction().getDataLayout().isBigEndian()) { 1018 if (LocVT == MVT::v2i32 || 1019 LocVT == MVT::v2f32 || 1020 LocVT == MVT::v4i16 || 1021 LocVT == MVT::v4f16 || 1022 LocVT == MVT::v8i8) { 1023 LocVT = MVT::f64; 1024 LocInfo = CCValAssign::BCvt; 1025 } 1026 } 1027 1028 if (State.getMachineFunction().getDataLayout().isBigEndian()) { 1029 if (LocVT == MVT::v2i64 || 1030 LocVT == MVT::v2f64 || 1031 LocVT == MVT::v4i32 || 1032 LocVT == MVT::v4f32 || 1033 LocVT == MVT::v8i16 || 1034 LocVT == MVT::v8f16 || 1035 LocVT == MVT::v16i8) { 1036 LocVT = MVT::f128; 1037 LocInfo = CCValAssign::BCvt; 1038 } 1039 } 1040 1041 if (LocVT == MVT::i1 || 1042 LocVT == MVT::i8 || 1043 LocVT == MVT::i16) { 1044 LocVT = MVT::i32; 1045 if (ArgFlags.isSExt()) 1046 LocInfo = CCValAssign::SExt; 1047 else if (ArgFlags.isZExt()) 1048 LocInfo = CCValAssign::ZExt; 1049 else 1050 LocInfo = CCValAssign::AExt; 1051 } 1052 1053 if (LocVT == MVT::i32) { 1054 static const MCPhysReg RegList1[] = { 1055 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 1056 }; 1057 static const MCPhysReg RegList2[] = { 1058 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 1059 }; 1060 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 1061 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1062 return false; 1063 } 1064 } 1065 1066 if (LocVT == MVT::i64) { 1067 static const MCPhysReg RegList3[] = { 1068 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 1069 }; 1070 static const MCPhysReg RegList4[] = { 1071 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 1072 }; 1073 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { 1074 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1075 return false; 1076 } 1077 } 1078 1079 if (LocVT == MVT::f16) { 1080 static const MCPhysReg RegList5[] = { 1081 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 1082 }; 1083 static const MCPhysReg RegList6[] = { 1084 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1085 }; 1086 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { 1087 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1088 return false; 1089 } 1090 } 1091 1092 if (LocVT == MVT::f32) { 1093 static const MCPhysReg RegList7[] = { 1094 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 1095 }; 1096 static const MCPhysReg RegList8[] = { 1097 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1098 }; 1099 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 1100 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1101 return false; 1102 } 1103 } 1104 1105 if (LocVT == MVT::f64) { 1106 static const MCPhysReg RegList9[] = { 1107 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 1108 }; 1109 static const MCPhysReg RegList10[] = { 1110 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1111 }; 1112 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) { 1113 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1114 return false; 1115 } 1116 } 1117 1118 if (LocVT == MVT::v1i64 || 1119 LocVT == MVT::v2i32 || 1120 LocVT == MVT::v4i16 || 1121 LocVT == MVT::v8i8 || 1122 LocVT == MVT::v1f64 || 1123 LocVT == MVT::v2f32 || 1124 LocVT == MVT::v4f16) { 1125 static const MCPhysReg RegList11[] = { 1126 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 1127 }; 1128 static const MCPhysReg RegList12[] = { 1129 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1130 }; 1131 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { 1132 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1133 return false; 1134 } 1135 } 1136 1137 if (LocVT == MVT::f128 || 1138 LocVT == MVT::v2i64 || 1139 LocVT == MVT::v4i32 || 1140 LocVT == MVT::v8i16 || 1141 LocVT == MVT::v16i8 || 1142 LocVT == MVT::v4f32 || 1143 LocVT == MVT::v2f64 || 1144 LocVT == MVT::v8f16) { 1145 static const MCPhysReg RegList13[] = { 1146 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1147 }; 1148 if (unsigned Reg = State.AllocateReg(RegList13)) { 1149 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1150 return false; 1151 } 1152 } 1153 1154 if (LocVT == MVT::nxv16i8 || 1155 LocVT == MVT::nxv8i16 || 1156 LocVT == MVT::nxv4i32 || 1157 LocVT == MVT::nxv2i64 || 1158 LocVT == MVT::nxv2f16 || 1159 LocVT == MVT::nxv4f16 || 1160 LocVT == MVT::nxv8f16 || 1161 LocVT == MVT::nxv2f32 || 1162 LocVT == MVT::nxv4f32 || 1163 LocVT == MVT::nxv2f64) { 1164 static const MCPhysReg RegList14[] = { 1165 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 1166 }; 1167 if (unsigned Reg = State.AllocateReg(RegList14)) { 1168 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1169 return false; 1170 } 1171 } 1172 1173 if (LocVT == MVT::nxv2i1 || 1174 LocVT == MVT::nxv4i1 || 1175 LocVT == MVT::nxv8i1 || 1176 LocVT == MVT::nxv16i1) { 1177 static const MCPhysReg RegList15[] = { 1178 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3 1179 }; 1180 if (unsigned Reg = State.AllocateReg(RegList15)) { 1181 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1182 return false; 1183 } 1184 } 1185 1186 return true; // CC didn't match. 1187} 1188 1189 1190bool llvm::RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, 1191 MVT LocVT, CCValAssign::LocInfo LocInfo, 1192 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1193 1194 if (LocVT == MVT::i32) { 1195 static const MCPhysReg RegList1[] = { 1196 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 1197 }; 1198 static const MCPhysReg RegList2[] = { 1199 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 1200 }; 1201 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 1202 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1203 return false; 1204 } 1205 } 1206 1207 if (LocVT == MVT::i64) { 1208 static const MCPhysReg RegList3[] = { 1209 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 1210 }; 1211 static const MCPhysReg RegList4[] = { 1212 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 1213 }; 1214 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { 1215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1216 return false; 1217 } 1218 } 1219 1220 if (LocVT == MVT::f32) { 1221 static const MCPhysReg RegList5[] = { 1222 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 1223 }; 1224 static const MCPhysReg RegList6[] = { 1225 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1226 }; 1227 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { 1228 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1229 return false; 1230 } 1231 } 1232 1233 if (LocVT == MVT::f64) { 1234 static const MCPhysReg RegList7[] = { 1235 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 1236 }; 1237 static const MCPhysReg RegList8[] = { 1238 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1239 }; 1240 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 1241 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1242 return false; 1243 } 1244 } 1245 1246 return true; // CC didn't match. 1247} 1248