1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Register Bank Source Fragments                                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace ARM {
13enum {
14  FPRRegBankID,
15  GPRRegBankID,
16  NumRegisterBanks,
17};
18} // end namespace ARM
19} // end namespace llvm
20#endif // GET_REGBANK_DECLARATIONS
21
22#ifdef GET_TARGET_REGBANK_CLASS
23#undef GET_TARGET_REGBANK_CLASS
24private:
25  static RegisterBank *RegBanks[];
26
27protected:
28  ARMGenRegisterBankInfo();
29
30#endif // GET_TARGET_REGBANK_CLASS
31
32#ifdef GET_TARGET_REGBANK_IMPL
33#undef GET_TARGET_REGBANK_IMPL
34namespace llvm {
35namespace ARM {
36const uint32_t FPRRegBankCoverageData[] = {
37    // 0-31
38    (1u << (ARM::HPRRegClassID - 0)) |
39    (1u << (ARM::SPRRegClassID - 0)) |
40    (1u << (ARM::SPR_8RegClassID - 0)) |
41    (1u << (ARM::FPWithVPRRegClassID - 0)) |
42    (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
43    (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
44    0,
45    // 32-63
46    (1u << (ARM::DPRRegClassID - 32)) |
47    (1u << (ARM::DPR_VFP2RegClassID - 32)) |
48    (1u << (ARM::DPR_8RegClassID - 32)) |
49    (1u << (ARM::QPRRegClassID - 32)) |
50    (1u << (ARM::MQPRRegClassID - 32)) |
51    (1u << (ARM::QPR_VFP2RegClassID - 32)) |
52    (1u << (ARM::QPR_8RegClassID - 32)) |
53    0,
54    // 64-95
55    0,
56    // 96-127
57    0,
58};
59const uint32_t GPRRegBankCoverageData[] = {
60    // 0-31
61    (1u << (ARM::GPRRegClassID - 0)) |
62    (1u << (ARM::GPRnopcRegClassID - 0)) |
63    (1u << (ARM::rGPRRegClassID - 0)) |
64    (1u << (ARM::tGPRRegClassID - 0)) |
65    (1u << (ARM::tGPR_and_tGPREvenRegClassID - 0)) |
66    (1u << (ARM::tGPREven_and_tGPR_and_tcGPRRegClassID - 0)) |
67    (1u << (ARM::tGPR_and_tGPROddRegClassID - 0)) |
68    (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 0)) |
69    (1u << (ARM::tGPR_and_tcGPRRegClassID - 0)) |
70    (1u << (ARM::tGPREvenRegClassID - 0)) |
71    (1u << (ARM::hGPR_and_tGPREvenRegClassID - 0)) |
72    (1u << (ARM::GPRlrRegClassID - 0)) |
73    (1u << (ARM::tGPREven_and_tcGPRRegClassID - 0)) |
74    (1u << (ARM::GPRwithAPSRnosp_and_hGPRRegClassID - 0)) |
75    (1u << (ARM::hGPR_and_tGPROddRegClassID - 0)) |
76    (1u << (ARM::tGPROddRegClassID - 0)) |
77    (1u << (ARM::tcGPRRegClassID - 0)) |
78    (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
79    (1u << (ARM::GPRspRegClassID - 0)) |
80    (1u << (ARM::tGPRwithpcRegClassID - 0)) |
81    (1u << (ARM::hGPRRegClassID - 0)) |
82    (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
83    0,
84    // 32-63
85    (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
86    (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
87    0,
88    // 64-95
89    0,
90    // 96-127
91    0,
92};
93
94RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 122);
95RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 122);
96} // end namespace ARM
97
98RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
99    &ARM::FPRRegBank,
100    &ARM::GPRRegBank,
101};
102
103ARMGenRegisterBankInfo::ARMGenRegisterBankInfo()
104    : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks) {
105  // Assert that RegBank indices match their ID's
106#ifndef NDEBUG
107  unsigned Index = 0;
108  for (const auto &RB : RegBanks)
109    assert(Index++ == RB->getID() && "Index != ID");
110#endif // NDEBUG
111}
112} // end namespace llvm
113#endif // GET_TARGET_REGBANK_IMPL
114