1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Register Bank Source Fragments                                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace Mips {
13enum {
14  FPRBRegBankID,
15  GPRBRegBankID,
16  NumRegisterBanks,
17};
18} // end namespace Mips
19} // end namespace llvm
20#endif // GET_REGBANK_DECLARATIONS
21
22#ifdef GET_TARGET_REGBANK_CLASS
23#undef GET_TARGET_REGBANK_CLASS
24private:
25  static RegisterBank *RegBanks[];
26
27protected:
28  MipsGenRegisterBankInfo();
29
30#endif // GET_TARGET_REGBANK_CLASS
31
32#ifdef GET_TARGET_REGBANK_IMPL
33#undef GET_TARGET_REGBANK_IMPL
34namespace llvm {
35namespace Mips {
36const uint32_t FPRBRegBankCoverageData[] = {
37    // 0-31
38    (1u << (Mips::FGR32RegClassID - 0)) |
39    (1u << (Mips::FGRCCRegClassID - 0)) |
40    0,
41    // 32-63
42    (1u << (Mips::FGR64RegClassID - 32)) |
43    (1u << (Mips::AFGR64RegClassID - 32)) |
44    0,
45    // 64-95
46    (1u << (Mips::MSA128DRegClassID - 64)) |
47    (1u << (Mips::MSA128BRegClassID - 64)) |
48    (1u << (Mips::MSA128HRegClassID - 64)) |
49    (1u << (Mips::MSA128WRegClassID - 64)) |
50    (1u << (Mips::MSA128WEvensRegClassID - 64)) |
51    0,
52};
53const uint32_t GPRBRegBankCoverageData[] = {
54    // 0-31
55    (1u << (Mips::GPR32RegClassID - 0)) |
56    (1u << (Mips::GPR32NONZERORegClassID - 0)) |
57    (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
58    (1u << (Mips::CPU16RegsRegClassID - 0)) |
59    (1u << (Mips::GPRMM16RegClassID - 0)) |
60    (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
61    (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
62    (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
63    (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
64    (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
65    (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
66    (1u << (Mips::CPUSPRegRegClassID - 0)) |
67    (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
68    (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
69    (1u << (Mips::CPURARegRegClassID - 0)) |
70    (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
71    (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
72    (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
73    0,
74    // 32-63
75    (1u << (Mips::SP32RegClassID - 32)) |
76    (1u << (Mips::GP32RegClassID - 32)) |
77    (1u << (Mips::GPR32ZERORegClassID - 32)) |
78    0,
79    // 64-95
80    0,
81};
82
83RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
84RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
85} // end namespace Mips
86
87RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
88    &Mips::FPRBRegBank,
89    &Mips::GPRBRegBank,
90};
91
92MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
93    : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
94  // Assert that RegBank indices match their ID's
95#ifndef NDEBUG
96  unsigned Index = 0;
97  for (const auto &RB : RegBanks)
98    assert(Index++ == RB->getID() && "Index != ID");
99#endif // NDEBUG
100}
101} // end namespace llvm
102#endif // GET_TARGET_REGBANK_IMPL
103