1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Register Bank Source Fragments                                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace X86 {
13enum {
14  GPRRegBankID,
15  VECRRegBankID,
16  NumRegisterBanks,
17};
18} // end namespace X86
19} // end namespace llvm
20#endif // GET_REGBANK_DECLARATIONS
21
22#ifdef GET_TARGET_REGBANK_CLASS
23#undef GET_TARGET_REGBANK_CLASS
24private:
25  static RegisterBank *RegBanks[];
26
27protected:
28  X86GenRegisterBankInfo();
29
30#endif // GET_TARGET_REGBANK_CLASS
31
32#ifdef GET_TARGET_REGBANK_IMPL
33#undef GET_TARGET_REGBANK_IMPL
34namespace llvm {
35namespace X86 {
36const uint32_t GPRRegBankCoverageData[] = {
37    // 0-31
38    (1u << (X86::GR8RegClassID - 0)) |
39    (1u << (X86::GR16RegClassID - 0)) |
40    (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
41    (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
42    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
43    (1u << (X86::GR8_NOREXRegClassID - 0)) |
44    (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
45    (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
46    (1u << (X86::GR16_NOREXRegClassID - 0)) |
47    (1u << (X86::GR16_ABCDRegClassID - 0)) |
48    0,
49    // 32-63
50    (1u << (X86::GR32RegClassID - 32)) |
51    (1u << (X86::GR32_NOSPRegClassID - 32)) |
52    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
53    (1u << (X86::GR32_NOREXRegClassID - 32)) |
54    (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
55    (1u << (X86::GR32_ABCDRegClassID - 32)) |
56    (1u << (X86::GR32_TCRegClassID - 32)) |
57    (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
58    (1u << (X86::GR32_ADRegClassID - 32)) |
59    (1u << (X86::GR32_DCRegClassID - 32)) |
60    (1u << (X86::GR32_AD_and_GR32_DCRegClassID - 32)) |
61    (1u << (X86::GR32_CBRegClassID - 32)) |
62    (1u << (X86::GR32_CB_and_GR32_DCRegClassID - 32)) |
63    (1u << (X86::GR32_SIDIRegClassID - 32)) |
64    (1u << (X86::GR32_BSIRegClassID - 32)) |
65    (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 32)) |
66    (1u << (X86::GR32_DIBPRegClassID - 32)) |
67    (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 32)) |
68    (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
69    (1u << (X86::GR32_BPSPRegClassID - 32)) |
70    (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 32)) |
71    (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 32)) |
72    0,
73    // 64-95
74    (1u << (X86::GR64RegClassID - 64)) |
75    (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
76    (1u << (X86::GR64_NOSPRegClassID - 64)) |
77    (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 64)) |
78    (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
79    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 64)) |
80    (1u << (X86::GR64_ADRegClassID - 64)) |
81    (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 64)) |
82    (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
83    (1u << (X86::GR64_ABCDRegClassID - 64)) |
84    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 64)) |
85    (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
86    (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
87    (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 64)) |
88    (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) |
89    (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
90    (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
91    (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
92    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 64)) |
93    (1u << (X86::GR64_TCRegClassID - 64)) |
94    (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
95    (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) |
96    (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
97    (1u << (X86::GR64_NOREXRegClassID - 64)) |
98    (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
99    (1u << (X86::GR64_TCW64RegClassID - 64)) |
100    0,
101    // 96-127
102    (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID - 96)) |
103    (1u << (X86::GR64_with_sub_32bit_in_GR32_DCRegClassID - 96)) |
104    (1u << (X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID - 96)) |
105    (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
106    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
107    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
108    (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
109    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
110    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
111    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
112    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
113    (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
114    0,
115};
116const uint32_t VECRRegBankCoverageData[] = {
117    // 0-31
118    (1u << (X86::FR32XRegClassID - 0)) |
119    0,
120    // 32-63
121    (1u << (X86::FR32RegClassID - 32)) |
122    0,
123    // 64-95
124    (1u << (X86::FR64XRegClassID - 64)) |
125    (1u << (X86::FR64RegClassID - 64)) |
126    0,
127    // 96-127
128    (1u << (X86::VR512RegClassID - 96)) |
129    (1u << (X86::VR128XRegClassID - 96)) |
130    (1u << (X86::VR256XRegClassID - 96)) |
131    (1u << (X86::VR512_0_15RegClassID - 96)) |
132    (1u << (X86::VR128RegClassID - 96)) |
133    (1u << (X86::VR256RegClassID - 96)) |
134    0,
135};
136
137RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 118);
138RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 118);
139} // end namespace X86
140
141RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
142    &X86::GPRRegBank,
143    &X86::VECRRegBank,
144};
145
146X86GenRegisterBankInfo::X86GenRegisterBankInfo()
147    : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) {
148  // Assert that RegBank indices match their ID's
149#ifndef NDEBUG
150  unsigned Index = 0;
151  for (const auto &RB : RegBanks)
152    assert(Index++ == RB->getID() && "Index != ID");
153#endif // NDEBUG
154}
155} // end namespace llvm
156#endif // GET_TARGET_REGBANK_IMPL
157