1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12 13namespace llvm { 14 15class MCRegisterClass; 16extern const MCRegisterClass X86MCRegisterClasses[]; 17 18namespace X86 { 19enum { 20 NoRegister, 21 AH = 1, 22 AL = 2, 23 AX = 3, 24 BH = 4, 25 BL = 5, 26 BP = 6, 27 BPH = 7, 28 BPL = 8, 29 BX = 9, 30 CH = 10, 31 CL = 11, 32 CS = 12, 33 CX = 13, 34 DF = 14, 35 DH = 15, 36 DI = 16, 37 DIH = 17, 38 DIL = 18, 39 DL = 19, 40 DS = 20, 41 DX = 21, 42 EAX = 22, 43 EBP = 23, 44 EBX = 24, 45 ECX = 25, 46 EDI = 26, 47 EDX = 27, 48 EFLAGS = 28, 49 EIP = 29, 50 EIZ = 30, 51 ES = 31, 52 ESI = 32, 53 ESP = 33, 54 FPCW = 34, 55 FPSW = 35, 56 FS = 36, 57 GS = 37, 58 HAX = 38, 59 HBP = 39, 60 HBX = 40, 61 HCX = 41, 62 HDI = 42, 63 HDX = 43, 64 HIP = 44, 65 HSI = 45, 66 HSP = 46, 67 IP = 47, 68 MXCSR = 48, 69 RAX = 49, 70 RBP = 50, 71 RBX = 51, 72 RCX = 52, 73 RDI = 53, 74 RDX = 54, 75 RIP = 55, 76 RIZ = 56, 77 RSI = 57, 78 RSP = 58, 79 SI = 59, 80 SIH = 60, 81 SIL = 61, 82 SP = 62, 83 SPH = 63, 84 SPL = 64, 85 SS = 65, 86 SSP = 66, 87 BND0 = 67, 88 BND1 = 68, 89 BND2 = 69, 90 BND3 = 70, 91 CR0 = 71, 92 CR1 = 72, 93 CR2 = 73, 94 CR3 = 74, 95 CR4 = 75, 96 CR5 = 76, 97 CR6 = 77, 98 CR7 = 78, 99 CR8 = 79, 100 CR9 = 80, 101 CR10 = 81, 102 CR11 = 82, 103 CR12 = 83, 104 CR13 = 84, 105 CR14 = 85, 106 CR15 = 86, 107 DR0 = 87, 108 DR1 = 88, 109 DR2 = 89, 110 DR3 = 90, 111 DR4 = 91, 112 DR5 = 92, 113 DR6 = 93, 114 DR7 = 94, 115 DR8 = 95, 116 DR9 = 96, 117 DR10 = 97, 118 DR11 = 98, 119 DR12 = 99, 120 DR13 = 100, 121 DR14 = 101, 122 DR15 = 102, 123 FP0 = 103, 124 FP1 = 104, 125 FP2 = 105, 126 FP3 = 106, 127 FP4 = 107, 128 FP5 = 108, 129 FP6 = 109, 130 FP7 = 110, 131 K0 = 111, 132 K1 = 112, 133 K2 = 113, 134 K3 = 114, 135 K4 = 115, 136 K5 = 116, 137 K6 = 117, 138 K7 = 118, 139 MM0 = 119, 140 MM1 = 120, 141 MM2 = 121, 142 MM3 = 122, 143 MM4 = 123, 144 MM5 = 124, 145 MM6 = 125, 146 MM7 = 126, 147 R8 = 127, 148 R9 = 128, 149 R10 = 129, 150 R11 = 130, 151 R12 = 131, 152 R13 = 132, 153 R14 = 133, 154 R15 = 134, 155 ST0 = 135, 156 ST1 = 136, 157 ST2 = 137, 158 ST3 = 138, 159 ST4 = 139, 160 ST5 = 140, 161 ST6 = 141, 162 ST7 = 142, 163 XMM0 = 143, 164 XMM1 = 144, 165 XMM2 = 145, 166 XMM3 = 146, 167 XMM4 = 147, 168 XMM5 = 148, 169 XMM6 = 149, 170 XMM7 = 150, 171 XMM8 = 151, 172 XMM9 = 152, 173 XMM10 = 153, 174 XMM11 = 154, 175 XMM12 = 155, 176 XMM13 = 156, 177 XMM14 = 157, 178 XMM15 = 158, 179 XMM16 = 159, 180 XMM17 = 160, 181 XMM18 = 161, 182 XMM19 = 162, 183 XMM20 = 163, 184 XMM21 = 164, 185 XMM22 = 165, 186 XMM23 = 166, 187 XMM24 = 167, 188 XMM25 = 168, 189 XMM26 = 169, 190 XMM27 = 170, 191 XMM28 = 171, 192 XMM29 = 172, 193 XMM30 = 173, 194 XMM31 = 174, 195 YMM0 = 175, 196 YMM1 = 176, 197 YMM2 = 177, 198 YMM3 = 178, 199 YMM4 = 179, 200 YMM5 = 180, 201 YMM6 = 181, 202 YMM7 = 182, 203 YMM8 = 183, 204 YMM9 = 184, 205 YMM10 = 185, 206 YMM11 = 186, 207 YMM12 = 187, 208 YMM13 = 188, 209 YMM14 = 189, 210 YMM15 = 190, 211 YMM16 = 191, 212 YMM17 = 192, 213 YMM18 = 193, 214 YMM19 = 194, 215 YMM20 = 195, 216 YMM21 = 196, 217 YMM22 = 197, 218 YMM23 = 198, 219 YMM24 = 199, 220 YMM25 = 200, 221 YMM26 = 201, 222 YMM27 = 202, 223 YMM28 = 203, 224 YMM29 = 204, 225 YMM30 = 205, 226 YMM31 = 206, 227 ZMM0 = 207, 228 ZMM1 = 208, 229 ZMM2 = 209, 230 ZMM3 = 210, 231 ZMM4 = 211, 232 ZMM5 = 212, 233 ZMM6 = 213, 234 ZMM7 = 214, 235 ZMM8 = 215, 236 ZMM9 = 216, 237 ZMM10 = 217, 238 ZMM11 = 218, 239 ZMM12 = 219, 240 ZMM13 = 220, 241 ZMM14 = 221, 242 ZMM15 = 222, 243 ZMM16 = 223, 244 ZMM17 = 224, 245 ZMM18 = 225, 246 ZMM19 = 226, 247 ZMM20 = 227, 248 ZMM21 = 228, 249 ZMM22 = 229, 250 ZMM23 = 230, 251 ZMM24 = 231, 252 ZMM25 = 232, 253 ZMM26 = 233, 254 ZMM27 = 234, 255 ZMM28 = 235, 256 ZMM29 = 236, 257 ZMM30 = 237, 258 ZMM31 = 238, 259 R8B = 239, 260 R9B = 240, 261 R10B = 241, 262 R11B = 242, 263 R12B = 243, 264 R13B = 244, 265 R14B = 245, 266 R15B = 246, 267 R8BH = 247, 268 R9BH = 248, 269 R10BH = 249, 270 R11BH = 250, 271 R12BH = 251, 272 R13BH = 252, 273 R14BH = 253, 274 R15BH = 254, 275 R8D = 255, 276 R9D = 256, 277 R10D = 257, 278 R11D = 258, 279 R12D = 259, 280 R13D = 260, 281 R14D = 261, 282 R15D = 262, 283 R8W = 263, 284 R9W = 264, 285 R10W = 265, 286 R11W = 266, 287 R12W = 267, 288 R13W = 268, 289 R14W = 269, 290 R15W = 270, 291 R8WH = 271, 292 R9WH = 272, 293 R10WH = 273, 294 R11WH = 274, 295 R12WH = 275, 296 R13WH = 276, 297 R14WH = 277, 298 R15WH = 278, 299 K0_K1 = 279, 300 K2_K3 = 280, 301 K4_K5 = 281, 302 K6_K7 = 282, 303 NUM_TARGET_REGS // 283 304}; 305} // end namespace X86 306 307// Register classes 308 309namespace X86 { 310enum { 311 GR8RegClassID = 0, 312 GRH8RegClassID = 1, 313 GR8_NOREXRegClassID = 2, 314 GR8_ABCD_HRegClassID = 3, 315 GR8_ABCD_LRegClassID = 4, 316 GRH16RegClassID = 5, 317 GR16RegClassID = 6, 318 GR16_NOREXRegClassID = 7, 319 VK1RegClassID = 8, 320 VK16RegClassID = 9, 321 VK2RegClassID = 10, 322 VK4RegClassID = 11, 323 VK8RegClassID = 12, 324 VK16WMRegClassID = 13, 325 VK1WMRegClassID = 14, 326 VK2WMRegClassID = 15, 327 VK4WMRegClassID = 16, 328 VK8WMRegClassID = 17, 329 SEGMENT_REGRegClassID = 18, 330 GR16_ABCDRegClassID = 19, 331 FPCCRRegClassID = 20, 332 VK16PAIRRegClassID = 21, 333 VK1PAIRRegClassID = 22, 334 VK2PAIRRegClassID = 23, 335 VK4PAIRRegClassID = 24, 336 VK8PAIRRegClassID = 25, 337 VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID = 26, 338 FR32XRegClassID = 27, 339 LOW32_ADDR_ACCESS_RBPRegClassID = 28, 340 LOW32_ADDR_ACCESSRegClassID = 29, 341 LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 30, 342 DEBUG_REGRegClassID = 31, 343 FR32RegClassID = 32, 344 GR32RegClassID = 33, 345 GR32_NOSPRegClassID = 34, 346 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 35, 347 GR32_NOREXRegClassID = 36, 348 VK32RegClassID = 37, 349 GR32_NOREX_NOSPRegClassID = 38, 350 RFP32RegClassID = 39, 351 VK32WMRegClassID = 40, 352 GR32_ABCDRegClassID = 41, 353 GR32_TCRegClassID = 42, 354 GR32_ABCD_and_GR32_TCRegClassID = 43, 355 GR32_ADRegClassID = 44, 356 GR32_BPSPRegClassID = 45, 357 GR32_BSIRegClassID = 46, 358 GR32_CBRegClassID = 47, 359 GR32_DCRegClassID = 48, 360 GR32_DIBPRegClassID = 49, 361 GR32_SIDIRegClassID = 50, 362 LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 51, 363 CCRRegClassID = 52, 364 DFCCRRegClassID = 53, 365 GR32_ABCD_and_GR32_BSIRegClassID = 54, 366 GR32_AD_and_GR32_DCRegClassID = 55, 367 GR32_BPSP_and_GR32_DIBPRegClassID = 56, 368 GR32_BPSP_and_GR32_TCRegClassID = 57, 369 GR32_BSI_and_GR32_SIDIRegClassID = 58, 370 GR32_CB_and_GR32_DCRegClassID = 59, 371 GR32_DIBP_and_GR32_SIDIRegClassID = 60, 372 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 61, 373 LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 62, 374 RFP64RegClassID = 63, 375 FR64XRegClassID = 64, 376 GR64RegClassID = 65, 377 CONTROL_REGRegClassID = 66, 378 FR64RegClassID = 67, 379 GR64_with_sub_8bitRegClassID = 68, 380 GR64_NOSPRegClassID = 69, 381 GR64_TCRegClassID = 70, 382 GR64_NOREXRegClassID = 71, 383 GR64_TCW64RegClassID = 72, 384 GR64_TC_with_sub_8bitRegClassID = 73, 385 GR64_NOSP_and_GR64_TCRegClassID = 74, 386 GR64_TCW64_with_sub_8bitRegClassID = 75, 387 GR64_TC_and_GR64_TCW64RegClassID = 76, 388 GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 77, 389 VK64RegClassID = 78, 390 VR64RegClassID = 79, 391 GR64_NOREX_NOSPRegClassID = 80, 392 GR64_NOREX_and_GR64_TCRegClassID = 81, 393 GR64_NOSP_and_GR64_TCW64RegClassID = 82, 394 GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 83, 395 VK64WMRegClassID = 84, 396 GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 85, 397 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 86, 398 GR64_NOREX_NOSP_and_GR64_TCRegClassID = 87, 399 GR64_NOREX_and_GR64_TCW64RegClassID = 88, 400 GR64_ABCDRegClassID = 89, 401 GR64_with_sub_32bit_in_GR32_TCRegClassID = 90, 402 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 91, 403 GR64_ADRegClassID = 92, 404 GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 93, 405 GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 94, 406 GR64_with_sub_32bit_in_GR32_BSIRegClassID = 95, 407 GR64_with_sub_32bit_in_GR32_CBRegClassID = 96, 408 GR64_with_sub_32bit_in_GR32_DCRegClassID = 97, 409 GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 98, 410 GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 99, 411 GR64_and_LOW32_ADDR_ACCESSRegClassID = 100, 412 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 101, 413 GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 102, 414 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 103, 415 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 104, 416 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 105, 417 GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 106, 418 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 107, 419 RSTRegClassID = 108, 420 RFP80RegClassID = 109, 421 RFP80_7RegClassID = 110, 422 VR128XRegClassID = 111, 423 VR128RegClassID = 112, 424 BNDRRegClassID = 113, 425 VR256XRegClassID = 114, 426 VR256RegClassID = 115, 427 VR512RegClassID = 116, 428 VR512_0_15RegClassID = 117, 429 430 }; 431} // end namespace X86 432 433 434// Subregister indices 435 436namespace X86 { 437enum { 438 NoSubRegister, 439 sub_8bit, // 1 440 sub_8bit_hi, // 2 441 sub_8bit_hi_phony, // 3 442 sub_16bit, // 4 443 sub_16bit_hi, // 5 444 sub_32bit, // 6 445 sub_mask_0, // 7 446 sub_mask_1, // 8 447 sub_xmm, // 9 448 sub_ymm, // 10 449 NUM_TARGET_SUBREGS 450}; 451} // end namespace X86 452 453} // end namespace llvm 454 455#endif // GET_REGINFO_ENUM 456 457/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 458|* *| 459|* MC Register Information *| 460|* *| 461|* Automatically generated file, do not edit! *| 462|* *| 463\*===----------------------------------------------------------------------===*/ 464 465 466#ifdef GET_REGINFO_MC_DESC 467#undef GET_REGINFO_MC_DESC 468 469namespace llvm { 470 471extern const MCPhysReg X86RegDiffLists[] = { 472 /* 0 */ 0, 1, 0, 473 /* 3 */ 64871, 1, 1, 0, 474 /* 7 */ 65255, 1, 1, 0, 475 /* 11 */ 65391, 1, 1, 0, 476 /* 15 */ 65466, 1, 1, 0, 477 /* 19 */ 2, 1, 0, 478 /* 22 */ 4, 1, 0, 479 /* 25 */ 6, 1, 0, 480 /* 28 */ 11, 1, 0, 481 /* 31 */ 22, 1, 0, 482 /* 34 */ 26, 1, 0, 483 /* 37 */ 29, 1, 0, 484 /* 40 */ 64847, 1, 0, 485 /* 43 */ 65062, 1, 0, 486 /* 46 */ 65368, 1, 0, 487 /* 49 */ 65369, 1, 0, 488 /* 52 */ 65370, 1, 0, 489 /* 55 */ 65371, 1, 0, 490 /* 58 */ 10, 3, 0, 491 /* 61 */ 4, 0, 492 /* 63 */ 5, 0, 493 /* 65 */ 65282, 1, 7, 0, 494 /* 69 */ 65417, 1, 7, 0, 495 /* 73 */ 10, 3, 7, 0, 496 /* 77 */ 65512, 8, 0, 497 /* 80 */ 65334, 1, 11, 0, 498 /* 84 */ 65340, 1, 11, 0, 499 /* 88 */ 65442, 1, 11, 0, 500 /* 92 */ 65448, 1, 11, 0, 501 /* 96 */ 12, 0, 502 /* 98 */ 65334, 1, 14, 0, 503 /* 102 */ 65340, 1, 14, 0, 504 /* 106 */ 65442, 1, 14, 0, 505 /* 110 */ 65448, 1, 14, 0, 506 /* 114 */ 21, 0, 507 /* 116 */ 128, 8, 65512, 8, 24, 0, 508 /* 122 */ 65534, 65507, 25, 0, 509 /* 126 */ 65535, 65507, 25, 0, 510 /* 130 */ 65534, 65509, 25, 0, 511 /* 134 */ 65535, 65509, 25, 0, 512 /* 138 */ 65523, 25, 0, 513 /* 141 */ 65509, 65526, 2, 65535, 25, 0, 514 /* 147 */ 65518, 26, 0, 515 /* 150 */ 65521, 26, 0, 516 /* 153 */ 2, 6, 27, 0, 517 /* 157 */ 6, 6, 27, 0, 518 /* 161 */ 65534, 10, 27, 0, 519 /* 165 */ 65535, 10, 27, 0, 520 /* 169 */ 2, 12, 27, 0, 521 /* 173 */ 3, 12, 27, 0, 522 /* 177 */ 4, 15, 27, 0, 523 /* 181 */ 5, 15, 27, 0, 524 /* 185 */ 65534, 17, 27, 0, 525 /* 189 */ 65535, 17, 27, 0, 526 /* 193 */ 1, 19, 27, 0, 527 /* 197 */ 2, 19, 27, 0, 528 /* 201 */ 65520, 27, 0, 529 /* 204 */ 65509, 65530, 65534, 65532, 28, 0, 530 /* 210 */ 30, 0, 531 /* 212 */ 65509, 65524, 65534, 65535, 31, 0, 532 /* 218 */ 32, 32, 0, 533 /* 221 */ 65509, 65519, 2, 65535, 32, 0, 534 /* 227 */ 65509, 65521, 65532, 65535, 36, 0, 535 /* 233 */ 65509, 65517, 65535, 65535, 37, 0, 536 /* 239 */ 164, 0, 537 /* 241 */ 165, 0, 538 /* 243 */ 166, 0, 539 /* 245 */ 167, 0, 540 /* 247 */ 168, 0, 541 /* 249 */ 64825, 0, 542 /* 251 */ 64896, 0, 543 /* 253 */ 64900, 0, 544 /* 255 */ 64919, 0, 545 /* 257 */ 64989, 0, 546 /* 259 */ 65520, 65408, 0, 547 /* 262 */ 16, 65528, 65408, 0, 548 /* 266 */ 24, 65528, 65408, 0, 549 /* 270 */ 65427, 0, 550 /* 272 */ 65429, 0, 551 /* 274 */ 65461, 0, 552 /* 276 */ 65493, 0, 553 /* 278 */ 65504, 65504, 0, 554 /* 281 */ 65509, 0, 555 /* 283 */ 65511, 0, 556 /* 285 */ 65513, 0, 557 /* 287 */ 65511, 29, 2, 65535, 65519, 0, 558 /* 293 */ 65511, 27, 2, 65535, 65521, 0, 559 /* 299 */ 65525, 0, 560 /* 301 */ 65530, 0, 561 /* 303 */ 65531, 0, 562 /* 305 */ 65534, 65532, 0, 563 /* 308 */ 65510, 18, 65533, 0, 564 /* 312 */ 65534, 0, 565 /* 314 */ 2, 65535, 0, 566 /* 317 */ 65532, 65535, 0, 567 /* 320 */ 65534, 65535, 0, 568 /* 323 */ 65535, 65535, 0, 569}; 570 571extern const LaneBitmask X86LaneMaskLists[] = { 572 /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), 573 /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(), 574 /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(), 575 /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(), 576 /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(), 577 /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(), 578 /* 19 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(), 579 /* 22 */ LaneBitmask(0x00000040), LaneBitmask::getAll(), 580}; 581 582extern const uint16_t X86SubRegIdxLists[] = { 583 /* 0 */ 1, 2, 0, 584 /* 3 */ 1, 3, 0, 585 /* 6 */ 6, 4, 1, 2, 5, 0, 586 /* 12 */ 6, 4, 1, 3, 5, 0, 587 /* 18 */ 6, 4, 5, 0, 588 /* 22 */ 7, 8, 0, 589 /* 25 */ 10, 9, 0, 590}; 591 592extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = { 593 { 65535, 65535 }, 594 { 0, 8 }, // sub_8bit 595 { 8, 8 }, // sub_8bit_hi 596 { 8, 8 }, // sub_8bit_hi_phony 597 { 0, 16 }, // sub_16bit 598 { 16, 16 }, // sub_16bit_hi 599 { 0, 32 }, // sub_32bit 600 { 0, 65535 }, // sub_mask_0 601 { 65535, 65535 }, // sub_mask_1 602 { 0, 128 }, // sub_xmm 603 { 0, 256 }, // sub_ymm 604}; 605 606extern const char X86RegStrings[] = { 607 /* 0 */ 'X', 'M', 'M', '1', '0', 0, 608 /* 6 */ 'Y', 'M', 'M', '1', '0', 0, 609 /* 12 */ 'Z', 'M', 'M', '1', '0', 0, 610 /* 18 */ 'C', 'R', '1', '0', 0, 611 /* 23 */ 'D', 'R', '1', '0', 0, 612 /* 28 */ 'X', 'M', 'M', '2', '0', 0, 613 /* 34 */ 'Y', 'M', 'M', '2', '0', 0, 614 /* 40 */ 'Z', 'M', 'M', '2', '0', 0, 615 /* 46 */ 'X', 'M', 'M', '3', '0', 0, 616 /* 52 */ 'Y', 'M', 'M', '3', '0', 0, 617 /* 58 */ 'Z', 'M', 'M', '3', '0', 0, 618 /* 64 */ 'B', 'N', 'D', '0', 0, 619 /* 69 */ 'K', '0', 0, 620 /* 72 */ 'X', 'M', 'M', '0', 0, 621 /* 77 */ 'Y', 'M', 'M', '0', 0, 622 /* 82 */ 'Z', 'M', 'M', '0', 0, 623 /* 87 */ 'F', 'P', '0', 0, 624 /* 91 */ 'C', 'R', '0', 0, 625 /* 95 */ 'D', 'R', '0', 0, 626 /* 99 */ 'S', 'T', '0', 0, 627 /* 103 */ 'X', 'M', 'M', '1', '1', 0, 628 /* 109 */ 'Y', 'M', 'M', '1', '1', 0, 629 /* 115 */ 'Z', 'M', 'M', '1', '1', 0, 630 /* 121 */ 'C', 'R', '1', '1', 0, 631 /* 126 */ 'D', 'R', '1', '1', 0, 632 /* 131 */ 'X', 'M', 'M', '2', '1', 0, 633 /* 137 */ 'Y', 'M', 'M', '2', '1', 0, 634 /* 143 */ 'Z', 'M', 'M', '2', '1', 0, 635 /* 149 */ 'X', 'M', 'M', '3', '1', 0, 636 /* 155 */ 'Y', 'M', 'M', '3', '1', 0, 637 /* 161 */ 'Z', 'M', 'M', '3', '1', 0, 638 /* 167 */ 'B', 'N', 'D', '1', 0, 639 /* 172 */ 'K', '0', '_', 'K', '1', 0, 640 /* 178 */ 'X', 'M', 'M', '1', 0, 641 /* 183 */ 'Y', 'M', 'M', '1', 0, 642 /* 188 */ 'Z', 'M', 'M', '1', 0, 643 /* 193 */ 'F', 'P', '1', 0, 644 /* 197 */ 'C', 'R', '1', 0, 645 /* 201 */ 'D', 'R', '1', 0, 646 /* 205 */ 'S', 'T', '1', 0, 647 /* 209 */ 'X', 'M', 'M', '1', '2', 0, 648 /* 215 */ 'Y', 'M', 'M', '1', '2', 0, 649 /* 221 */ 'Z', 'M', 'M', '1', '2', 0, 650 /* 227 */ 'C', 'R', '1', '2', 0, 651 /* 232 */ 'D', 'R', '1', '2', 0, 652 /* 237 */ 'X', 'M', 'M', '2', '2', 0, 653 /* 243 */ 'Y', 'M', 'M', '2', '2', 0, 654 /* 249 */ 'Z', 'M', 'M', '2', '2', 0, 655 /* 255 */ 'B', 'N', 'D', '2', 0, 656 /* 260 */ 'K', '2', 0, 657 /* 263 */ 'X', 'M', 'M', '2', 0, 658 /* 268 */ 'Y', 'M', 'M', '2', 0, 659 /* 273 */ 'Z', 'M', 'M', '2', 0, 660 /* 278 */ 'F', 'P', '2', 0, 661 /* 282 */ 'C', 'R', '2', 0, 662 /* 286 */ 'D', 'R', '2', 0, 663 /* 290 */ 'S', 'T', '2', 0, 664 /* 294 */ 'X', 'M', 'M', '1', '3', 0, 665 /* 300 */ 'Y', 'M', 'M', '1', '3', 0, 666 /* 306 */ 'Z', 'M', 'M', '1', '3', 0, 667 /* 312 */ 'C', 'R', '1', '3', 0, 668 /* 317 */ 'D', 'R', '1', '3', 0, 669 /* 322 */ 'X', 'M', 'M', '2', '3', 0, 670 /* 328 */ 'Y', 'M', 'M', '2', '3', 0, 671 /* 334 */ 'Z', 'M', 'M', '2', '3', 0, 672 /* 340 */ 'B', 'N', 'D', '3', 0, 673 /* 345 */ 'K', '2', '_', 'K', '3', 0, 674 /* 351 */ 'X', 'M', 'M', '3', 0, 675 /* 356 */ 'Y', 'M', 'M', '3', 0, 676 /* 361 */ 'Z', 'M', 'M', '3', 0, 677 /* 366 */ 'F', 'P', '3', 0, 678 /* 370 */ 'C', 'R', '3', 0, 679 /* 374 */ 'D', 'R', '3', 0, 680 /* 378 */ 'S', 'T', '3', 0, 681 /* 382 */ 'X', 'M', 'M', '1', '4', 0, 682 /* 388 */ 'Y', 'M', 'M', '1', '4', 0, 683 /* 394 */ 'Z', 'M', 'M', '1', '4', 0, 684 /* 400 */ 'C', 'R', '1', '4', 0, 685 /* 405 */ 'D', 'R', '1', '4', 0, 686 /* 410 */ 'X', 'M', 'M', '2', '4', 0, 687 /* 416 */ 'Y', 'M', 'M', '2', '4', 0, 688 /* 422 */ 'Z', 'M', 'M', '2', '4', 0, 689 /* 428 */ 'K', '4', 0, 690 /* 431 */ 'X', 'M', 'M', '4', 0, 691 /* 436 */ 'Y', 'M', 'M', '4', 0, 692 /* 441 */ 'Z', 'M', 'M', '4', 0, 693 /* 446 */ 'F', 'P', '4', 0, 694 /* 450 */ 'C', 'R', '4', 0, 695 /* 454 */ 'D', 'R', '4', 0, 696 /* 458 */ 'S', 'T', '4', 0, 697 /* 462 */ 'X', 'M', 'M', '1', '5', 0, 698 /* 468 */ 'Y', 'M', 'M', '1', '5', 0, 699 /* 474 */ 'Z', 'M', 'M', '1', '5', 0, 700 /* 480 */ 'C', 'R', '1', '5', 0, 701 /* 485 */ 'D', 'R', '1', '5', 0, 702 /* 490 */ 'X', 'M', 'M', '2', '5', 0, 703 /* 496 */ 'Y', 'M', 'M', '2', '5', 0, 704 /* 502 */ 'Z', 'M', 'M', '2', '5', 0, 705 /* 508 */ 'K', '4', '_', 'K', '5', 0, 706 /* 514 */ 'X', 'M', 'M', '5', 0, 707 /* 519 */ 'Y', 'M', 'M', '5', 0, 708 /* 524 */ 'Z', 'M', 'M', '5', 0, 709 /* 529 */ 'F', 'P', '5', 0, 710 /* 533 */ 'C', 'R', '5', 0, 711 /* 537 */ 'D', 'R', '5', 0, 712 /* 541 */ 'S', 'T', '5', 0, 713 /* 545 */ 'X', 'M', 'M', '1', '6', 0, 714 /* 551 */ 'Y', 'M', 'M', '1', '6', 0, 715 /* 557 */ 'Z', 'M', 'M', '1', '6', 0, 716 /* 563 */ 'X', 'M', 'M', '2', '6', 0, 717 /* 569 */ 'Y', 'M', 'M', '2', '6', 0, 718 /* 575 */ 'Z', 'M', 'M', '2', '6', 0, 719 /* 581 */ 'K', '6', 0, 720 /* 584 */ 'X', 'M', 'M', '6', 0, 721 /* 589 */ 'Y', 'M', 'M', '6', 0, 722 /* 594 */ 'Z', 'M', 'M', '6', 0, 723 /* 599 */ 'F', 'P', '6', 0, 724 /* 603 */ 'C', 'R', '6', 0, 725 /* 607 */ 'D', 'R', '6', 0, 726 /* 611 */ 'S', 'T', '6', 0, 727 /* 615 */ 'X', 'M', 'M', '1', '7', 0, 728 /* 621 */ 'Y', 'M', 'M', '1', '7', 0, 729 /* 627 */ 'Z', 'M', 'M', '1', '7', 0, 730 /* 633 */ 'X', 'M', 'M', '2', '7', 0, 731 /* 639 */ 'Y', 'M', 'M', '2', '7', 0, 732 /* 645 */ 'Z', 'M', 'M', '2', '7', 0, 733 /* 651 */ 'K', '6', '_', 'K', '7', 0, 734 /* 657 */ 'X', 'M', 'M', '7', 0, 735 /* 662 */ 'Y', 'M', 'M', '7', 0, 736 /* 667 */ 'Z', 'M', 'M', '7', 0, 737 /* 672 */ 'F', 'P', '7', 0, 738 /* 676 */ 'C', 'R', '7', 0, 739 /* 680 */ 'D', 'R', '7', 0, 740 /* 684 */ 'S', 'T', '7', 0, 741 /* 688 */ 'X', 'M', 'M', '1', '8', 0, 742 /* 694 */ 'Y', 'M', 'M', '1', '8', 0, 743 /* 700 */ 'Z', 'M', 'M', '1', '8', 0, 744 /* 706 */ 'X', 'M', 'M', '2', '8', 0, 745 /* 712 */ 'Y', 'M', 'M', '2', '8', 0, 746 /* 718 */ 'Z', 'M', 'M', '2', '8', 0, 747 /* 724 */ 'X', 'M', 'M', '8', 0, 748 /* 729 */ 'Y', 'M', 'M', '8', 0, 749 /* 734 */ 'Z', 'M', 'M', '8', 0, 750 /* 739 */ 'C', 'R', '8', 0, 751 /* 743 */ 'D', 'R', '8', 0, 752 /* 747 */ 'X', 'M', 'M', '1', '9', 0, 753 /* 753 */ 'Y', 'M', 'M', '1', '9', 0, 754 /* 759 */ 'Z', 'M', 'M', '1', '9', 0, 755 /* 765 */ 'X', 'M', 'M', '2', '9', 0, 756 /* 771 */ 'Y', 'M', 'M', '2', '9', 0, 757 /* 777 */ 'Z', 'M', 'M', '2', '9', 0, 758 /* 783 */ 'X', 'M', 'M', '9', 0, 759 /* 788 */ 'Y', 'M', 'M', '9', 0, 760 /* 793 */ 'Z', 'M', 'M', '9', 0, 761 /* 798 */ 'C', 'R', '9', 0, 762 /* 802 */ 'D', 'R', '9', 0, 763 /* 806 */ 'R', '1', '0', 'B', 0, 764 /* 811 */ 'R', '1', '1', 'B', 0, 765 /* 816 */ 'R', '1', '2', 'B', 0, 766 /* 821 */ 'R', '1', '3', 'B', 0, 767 /* 826 */ 'R', '1', '4', 'B', 0, 768 /* 831 */ 'R', '1', '5', 'B', 0, 769 /* 836 */ 'R', '8', 'B', 0, 770 /* 840 */ 'R', '9', 'B', 0, 771 /* 844 */ 'R', '1', '0', 'D', 0, 772 /* 849 */ 'R', '1', '1', 'D', 0, 773 /* 854 */ 'R', '1', '2', 'D', 0, 774 /* 859 */ 'R', '1', '3', 'D', 0, 775 /* 864 */ 'R', '1', '4', 'D', 0, 776 /* 869 */ 'R', '1', '5', 'D', 0, 777 /* 874 */ 'R', '8', 'D', 0, 778 /* 878 */ 'R', '9', 'D', 0, 779 /* 882 */ 'D', 'F', 0, 780 /* 885 */ 'A', 'H', 0, 781 /* 888 */ 'R', '1', '0', 'B', 'H', 0, 782 /* 894 */ 'R', '1', '1', 'B', 'H', 0, 783 /* 900 */ 'R', '1', '2', 'B', 'H', 0, 784 /* 906 */ 'R', '1', '3', 'B', 'H', 0, 785 /* 912 */ 'R', '1', '4', 'B', 'H', 0, 786 /* 918 */ 'R', '1', '5', 'B', 'H', 0, 787 /* 924 */ 'R', '8', 'B', 'H', 0, 788 /* 929 */ 'R', '9', 'B', 'H', 0, 789 /* 934 */ 'C', 'H', 0, 790 /* 937 */ 'D', 'H', 0, 791 /* 940 */ 'D', 'I', 'H', 0, 792 /* 944 */ 'S', 'I', 'H', 0, 793 /* 948 */ 'B', 'P', 'H', 0, 794 /* 952 */ 'S', 'P', 'H', 0, 795 /* 956 */ 'R', '1', '0', 'W', 'H', 0, 796 /* 962 */ 'R', '1', '1', 'W', 'H', 0, 797 /* 968 */ 'R', '1', '2', 'W', 'H', 0, 798 /* 974 */ 'R', '1', '3', 'W', 'H', 0, 799 /* 980 */ 'R', '1', '4', 'W', 'H', 0, 800 /* 986 */ 'R', '1', '5', 'W', 'H', 0, 801 /* 992 */ 'R', '8', 'W', 'H', 0, 802 /* 997 */ 'R', '9', 'W', 'H', 0, 803 /* 1002 */ 'E', 'D', 'I', 0, 804 /* 1006 */ 'H', 'D', 'I', 0, 805 /* 1010 */ 'R', 'D', 'I', 0, 806 /* 1014 */ 'E', 'S', 'I', 0, 807 /* 1018 */ 'H', 'S', 'I', 0, 808 /* 1022 */ 'R', 'S', 'I', 0, 809 /* 1026 */ 'A', 'L', 0, 810 /* 1029 */ 'B', 'L', 0, 811 /* 1032 */ 'C', 'L', 0, 812 /* 1035 */ 'D', 'L', 0, 813 /* 1038 */ 'D', 'I', 'L', 0, 814 /* 1042 */ 'S', 'I', 'L', 0, 815 /* 1046 */ 'B', 'P', 'L', 0, 816 /* 1050 */ 'S', 'P', 'L', 0, 817 /* 1054 */ 'E', 'B', 'P', 0, 818 /* 1058 */ 'H', 'B', 'P', 0, 819 /* 1062 */ 'R', 'B', 'P', 0, 820 /* 1066 */ 'E', 'I', 'P', 0, 821 /* 1070 */ 'H', 'I', 'P', 0, 822 /* 1074 */ 'R', 'I', 'P', 0, 823 /* 1078 */ 'E', 'S', 'P', 0, 824 /* 1082 */ 'H', 'S', 'P', 0, 825 /* 1086 */ 'R', 'S', 'P', 0, 826 /* 1090 */ 'S', 'S', 'P', 0, 827 /* 1094 */ 'M', 'X', 'C', 'S', 'R', 0, 828 /* 1100 */ 'C', 'S', 0, 829 /* 1103 */ 'D', 'S', 0, 830 /* 1106 */ 'E', 'S', 0, 831 /* 1109 */ 'F', 'S', 0, 832 /* 1112 */ 'E', 'F', 'L', 'A', 'G', 'S', 0, 833 /* 1119 */ 'S', 'S', 0, 834 /* 1122 */ 'R', '1', '0', 'W', 0, 835 /* 1127 */ 'R', '1', '1', 'W', 0, 836 /* 1132 */ 'R', '1', '2', 'W', 0, 837 /* 1137 */ 'R', '1', '3', 'W', 0, 838 /* 1142 */ 'R', '1', '4', 'W', 0, 839 /* 1147 */ 'R', '1', '5', 'W', 0, 840 /* 1152 */ 'R', '8', 'W', 0, 841 /* 1156 */ 'R', '9', 'W', 0, 842 /* 1160 */ 'F', 'P', 'C', 'W', 0, 843 /* 1165 */ 'F', 'P', 'S', 'W', 0, 844 /* 1170 */ 'E', 'A', 'X', 0, 845 /* 1174 */ 'H', 'A', 'X', 0, 846 /* 1178 */ 'R', 'A', 'X', 0, 847 /* 1182 */ 'E', 'B', 'X', 0, 848 /* 1186 */ 'H', 'B', 'X', 0, 849 /* 1190 */ 'R', 'B', 'X', 0, 850 /* 1194 */ 'E', 'C', 'X', 0, 851 /* 1198 */ 'H', 'C', 'X', 0, 852 /* 1202 */ 'R', 'C', 'X', 0, 853 /* 1206 */ 'E', 'D', 'X', 0, 854 /* 1210 */ 'H', 'D', 'X', 0, 855 /* 1214 */ 'R', 'D', 'X', 0, 856 /* 1218 */ 'E', 'I', 'Z', 0, 857 /* 1222 */ 'R', 'I', 'Z', 0, 858}; 859 860extern const MCRegisterDesc X86RegDesc[] = { // Descriptors 861 { 5, 0, 0, 0, 0, 0 }, 862 { 885, 2, 197, 2, 5041, 0 }, 863 { 1026, 2, 193, 2, 5041, 0 }, 864 { 1171, 323, 194, 0, 0, 2 }, 865 { 891, 2, 181, 2, 4993, 0 }, 866 { 1029, 2, 177, 2, 4993, 0 }, 867 { 1055, 314, 186, 3, 352, 5 }, 868 { 948, 2, 189, 2, 1008, 0 }, 869 { 1046, 2, 185, 2, 976, 0 }, 870 { 1183, 317, 178, 0, 304, 2 }, 871 { 934, 2, 173, 2, 4897, 0 }, 872 { 1032, 2, 169, 2, 4897, 0 }, 873 { 1100, 2, 2, 2, 4897, 0 }, 874 { 1195, 320, 170, 0, 400, 2 }, 875 { 882, 2, 2, 2, 4849, 0 }, 876 { 937, 2, 157, 2, 4849, 0 }, 877 { 1003, 314, 162, 3, 448, 5 }, 878 { 940, 2, 165, 2, 1536, 0 }, 879 { 1038, 2, 161, 2, 4530, 0 }, 880 { 1035, 2, 153, 2, 4817, 0 }, 881 { 1103, 2, 2, 2, 4817, 0 }, 882 { 1207, 305, 154, 0, 928, 2 }, 883 { 1170, 234, 155, 7, 1764, 8 }, 884 { 1054, 222, 155, 13, 1476, 12 }, 885 { 1182, 228, 155, 7, 1700, 8 }, 886 { 1194, 213, 155, 7, 1412, 8 }, 887 { 1002, 142, 155, 13, 1109, 12 }, 888 { 1206, 205, 155, 7, 1168, 8 }, 889 { 1112, 2, 2, 2, 1824, 0 }, 890 { 1066, 309, 148, 19, 496, 16 }, 891 { 1218, 2, 2, 2, 4817, 0 }, 892 { 1106, 2, 2, 2, 4817, 0 }, 893 { 1014, 294, 124, 13, 243, 12 }, 894 { 1078, 288, 124, 13, 243, 12 }, 895 { 1160, 2, 2, 2, 4993, 0 }, 896 { 1165, 2, 2, 2, 4993, 0 }, 897 { 1109, 2, 2, 2, 4993, 0 }, 898 { 1116, 2, 2, 2, 4993, 0 }, 899 { 1174, 2, 201, 2, 4561, 0 }, 900 { 1058, 2, 201, 2, 4561, 0 }, 901 { 1186, 2, 201, 2, 4561, 0 }, 902 { 1198, 2, 201, 2, 4561, 0 }, 903 { 1006, 2, 201, 2, 4561, 0 }, 904 { 1210, 2, 201, 2, 4561, 0 }, 905 { 1070, 2, 150, 2, 4323, 0 }, 906 { 1018, 2, 138, 2, 4355, 0 }, 907 { 1082, 2, 138, 2, 4355, 0 }, 908 { 1067, 2, 147, 2, 4062, 0 }, 909 { 1094, 2, 2, 2, 4062, 0 }, 910 { 1178, 233, 2, 6, 1636, 8 }, 911 { 1062, 221, 2, 12, 1348, 12 }, 912 { 1190, 227, 2, 6, 1572, 8 }, 913 { 1202, 212, 2, 6, 1284, 8 }, 914 { 1010, 141, 2, 12, 1045, 12 }, 915 { 1214, 204, 2, 6, 1168, 8 }, 916 { 1074, 308, 2, 18, 496, 16 }, 917 { 1222, 2, 2, 2, 3792, 0 }, 918 { 1022, 293, 2, 12, 179, 12 }, 919 { 1086, 287, 2, 12, 179, 12 }, 920 { 1015, 314, 131, 3, 544, 5 }, 921 { 944, 2, 134, 2, 2480, 0 }, 922 { 1042, 2, 130, 2, 2368, 0 }, 923 { 1079, 314, 123, 3, 592, 5 }, 924 { 952, 2, 126, 2, 3360, 0 }, 925 { 1050, 2, 122, 2, 4121, 0 }, 926 { 1119, 2, 2, 2, 4497, 0 }, 927 { 1090, 2, 2, 2, 4497, 0 }, 928 { 64, 2, 2, 2, 4497, 0 }, 929 { 167, 2, 2, 2, 4497, 0 }, 930 { 255, 2, 2, 2, 4497, 0 }, 931 { 340, 2, 2, 2, 4497, 0 }, 932 { 91, 2, 2, 2, 4497, 0 }, 933 { 197, 2, 2, 2, 4497, 0 }, 934 { 282, 2, 2, 2, 4497, 0 }, 935 { 370, 2, 2, 2, 4497, 0 }, 936 { 450, 2, 2, 2, 4497, 0 }, 937 { 533, 2, 2, 2, 4497, 0 }, 938 { 603, 2, 2, 2, 4497, 0 }, 939 { 676, 2, 2, 2, 4497, 0 }, 940 { 739, 2, 2, 2, 4497, 0 }, 941 { 798, 2, 2, 2, 4497, 0 }, 942 { 18, 2, 2, 2, 4497, 0 }, 943 { 121, 2, 2, 2, 4497, 0 }, 944 { 227, 2, 2, 2, 4497, 0 }, 945 { 312, 2, 2, 2, 4497, 0 }, 946 { 400, 2, 2, 2, 4497, 0 }, 947 { 480, 2, 2, 2, 4497, 0 }, 948 { 95, 2, 2, 2, 4497, 0 }, 949 { 201, 2, 2, 2, 4497, 0 }, 950 { 286, 2, 2, 2, 4497, 0 }, 951 { 374, 2, 2, 2, 4497, 0 }, 952 { 454, 2, 2, 2, 4497, 0 }, 953 { 537, 2, 2, 2, 4497, 0 }, 954 { 607, 2, 2, 2, 4497, 0 }, 955 { 680, 2, 2, 2, 4497, 0 }, 956 { 743, 2, 2, 2, 4497, 0 }, 957 { 802, 2, 2, 2, 4497, 0 }, 958 { 23, 2, 2, 2, 4497, 0 }, 959 { 126, 2, 2, 2, 4497, 0 }, 960 { 232, 2, 2, 2, 4497, 0 }, 961 { 317, 2, 2, 2, 4497, 0 }, 962 { 405, 2, 2, 2, 4497, 0 }, 963 { 485, 2, 2, 2, 4497, 0 }, 964 { 87, 2, 2, 2, 4497, 0 }, 965 { 193, 2, 2, 2, 4497, 0 }, 966 { 278, 2, 2, 2, 4497, 0 }, 967 { 366, 2, 2, 2, 4497, 0 }, 968 { 446, 2, 2, 2, 4497, 0 }, 969 { 529, 2, 2, 2, 4497, 0 }, 970 { 599, 2, 2, 2, 4497, 0 }, 971 { 672, 2, 2, 2, 4497, 0 }, 972 { 69, 2, 247, 2, 4497, 0 }, 973 { 175, 2, 245, 2, 4497, 0 }, 974 { 260, 2, 245, 2, 4497, 0 }, 975 { 348, 2, 243, 2, 4497, 0 }, 976 { 428, 2, 243, 2, 4497, 0 }, 977 { 511, 2, 241, 2, 4497, 0 }, 978 { 581, 2, 241, 2, 4497, 0 }, 979 { 654, 2, 239, 2, 4497, 0 }, 980 { 73, 2, 2, 2, 4497, 0 }, 981 { 179, 2, 2, 2, 4497, 0 }, 982 { 264, 2, 2, 2, 4497, 0 }, 983 { 352, 2, 2, 2, 4497, 0 }, 984 { 432, 2, 2, 2, 4497, 0 }, 985 { 515, 2, 2, 2, 4497, 0 }, 986 { 585, 2, 2, 2, 4497, 0 }, 987 { 658, 2, 2, 2, 4497, 0 }, 988 { 740, 116, 2, 12, 115, 12 }, 989 { 799, 116, 2, 12, 115, 12 }, 990 { 19, 116, 2, 12, 115, 12 }, 991 { 122, 116, 2, 12, 115, 12 }, 992 { 228, 116, 2, 12, 115, 12 }, 993 { 313, 116, 2, 12, 115, 12 }, 994 { 401, 116, 2, 12, 115, 12 }, 995 { 481, 116, 2, 12, 115, 12 }, 996 { 99, 2, 2, 2, 4785, 0 }, 997 { 205, 2, 2, 2, 4785, 0 }, 998 { 290, 2, 2, 2, 4785, 0 }, 999 { 378, 2, 2, 2, 4785, 0 }, 1000 { 458, 2, 2, 2, 4785, 0 }, 1001 { 541, 2, 2, 2, 4785, 0 }, 1002 { 611, 2, 2, 2, 4785, 0 }, 1003 { 684, 2, 2, 2, 4785, 0 }, 1004 { 72, 2, 218, 2, 4785, 0 }, 1005 { 178, 2, 218, 2, 4785, 0 }, 1006 { 263, 2, 218, 2, 4785, 0 }, 1007 { 351, 2, 218, 2, 4785, 0 }, 1008 { 431, 2, 218, 2, 4785, 0 }, 1009 { 514, 2, 218, 2, 4785, 0 }, 1010 { 584, 2, 218, 2, 4785, 0 }, 1011 { 657, 2, 218, 2, 4785, 0 }, 1012 { 724, 2, 218, 2, 4785, 0 }, 1013 { 783, 2, 218, 2, 4785, 0 }, 1014 { 0, 2, 218, 2, 4785, 0 }, 1015 { 103, 2, 218, 2, 4785, 0 }, 1016 { 209, 2, 218, 2, 4785, 0 }, 1017 { 294, 2, 218, 2, 4785, 0 }, 1018 { 382, 2, 218, 2, 4785, 0 }, 1019 { 462, 2, 218, 2, 4785, 0 }, 1020 { 545, 2, 218, 2, 4785, 0 }, 1021 { 615, 2, 218, 2, 4785, 0 }, 1022 { 688, 2, 218, 2, 4785, 0 }, 1023 { 747, 2, 218, 2, 4785, 0 }, 1024 { 28, 2, 218, 2, 4785, 0 }, 1025 { 131, 2, 218, 2, 4785, 0 }, 1026 { 237, 2, 218, 2, 4785, 0 }, 1027 { 322, 2, 218, 2, 4785, 0 }, 1028 { 410, 2, 218, 2, 4785, 0 }, 1029 { 490, 2, 218, 2, 4785, 0 }, 1030 { 563, 2, 218, 2, 4785, 0 }, 1031 { 633, 2, 218, 2, 4785, 0 }, 1032 { 706, 2, 218, 2, 4785, 0 }, 1033 { 765, 2, 218, 2, 4785, 0 }, 1034 { 46, 2, 218, 2, 4785, 0 }, 1035 { 149, 2, 218, 2, 4785, 0 }, 1036 { 77, 279, 219, 26, 4417, 22 }, 1037 { 183, 279, 219, 26, 4417, 22 }, 1038 { 268, 279, 219, 26, 4417, 22 }, 1039 { 356, 279, 219, 26, 4417, 22 }, 1040 { 436, 279, 219, 26, 4417, 22 }, 1041 { 519, 279, 219, 26, 4417, 22 }, 1042 { 589, 279, 219, 26, 4417, 22 }, 1043 { 662, 279, 219, 26, 4417, 22 }, 1044 { 729, 279, 219, 26, 4417, 22 }, 1045 { 788, 279, 219, 26, 4417, 22 }, 1046 { 6, 279, 219, 26, 4417, 22 }, 1047 { 109, 279, 219, 26, 4417, 22 }, 1048 { 215, 279, 219, 26, 4417, 22 }, 1049 { 300, 279, 219, 26, 4417, 22 }, 1050 { 388, 279, 219, 26, 4417, 22 }, 1051 { 468, 279, 219, 26, 4417, 22 }, 1052 { 551, 279, 219, 26, 4417, 22 }, 1053 { 621, 279, 219, 26, 4417, 22 }, 1054 { 694, 279, 219, 26, 4417, 22 }, 1055 { 753, 279, 219, 26, 4417, 22 }, 1056 { 34, 279, 219, 26, 4417, 22 }, 1057 { 137, 279, 219, 26, 4417, 22 }, 1058 { 243, 279, 219, 26, 4417, 22 }, 1059 { 328, 279, 219, 26, 4417, 22 }, 1060 { 416, 279, 219, 26, 4417, 22 }, 1061 { 496, 279, 219, 26, 4417, 22 }, 1062 { 569, 279, 219, 26, 4417, 22 }, 1063 { 639, 279, 219, 26, 4417, 22 }, 1064 { 712, 279, 219, 26, 4417, 22 }, 1065 { 771, 279, 219, 26, 4417, 22 }, 1066 { 52, 279, 219, 26, 4417, 22 }, 1067 { 155, 279, 219, 26, 4417, 22 }, 1068 { 82, 278, 2, 25, 4385, 22 }, 1069 { 188, 278, 2, 25, 4385, 22 }, 1070 { 273, 278, 2, 25, 4385, 22 }, 1071 { 361, 278, 2, 25, 4385, 22 }, 1072 { 441, 278, 2, 25, 4385, 22 }, 1073 { 524, 278, 2, 25, 4385, 22 }, 1074 { 594, 278, 2, 25, 4385, 22 }, 1075 { 667, 278, 2, 25, 4385, 22 }, 1076 { 734, 278, 2, 25, 4385, 22 }, 1077 { 793, 278, 2, 25, 4385, 22 }, 1078 { 12, 278, 2, 25, 4385, 22 }, 1079 { 115, 278, 2, 25, 4385, 22 }, 1080 { 221, 278, 2, 25, 4385, 22 }, 1081 { 306, 278, 2, 25, 4385, 22 }, 1082 { 394, 278, 2, 25, 4385, 22 }, 1083 { 474, 278, 2, 25, 4385, 22 }, 1084 { 557, 278, 2, 25, 4385, 22 }, 1085 { 627, 278, 2, 25, 4385, 22 }, 1086 { 700, 278, 2, 25, 4385, 22 }, 1087 { 759, 278, 2, 25, 4385, 22 }, 1088 { 40, 278, 2, 25, 4385, 22 }, 1089 { 143, 278, 2, 25, 4385, 22 }, 1090 { 249, 278, 2, 25, 4385, 22 }, 1091 { 334, 278, 2, 25, 4385, 22 }, 1092 { 422, 278, 2, 25, 4385, 22 }, 1093 { 502, 278, 2, 25, 4385, 22 }, 1094 { 575, 278, 2, 25, 4385, 22 }, 1095 { 645, 278, 2, 25, 4385, 22 }, 1096 { 718, 278, 2, 25, 4385, 22 }, 1097 { 777, 278, 2, 25, 4385, 22 }, 1098 { 58, 278, 2, 25, 4385, 22 }, 1099 { 161, 278, 2, 25, 4385, 22 }, 1100 { 836, 2, 266, 2, 4083, 0 }, 1101 { 840, 2, 266, 2, 4083, 0 }, 1102 { 806, 2, 266, 2, 4083, 0 }, 1103 { 811, 2, 266, 2, 4083, 0 }, 1104 { 816, 2, 266, 2, 4083, 0 }, 1105 { 821, 2, 266, 2, 4083, 0 }, 1106 { 826, 2, 266, 2, 4083, 0 }, 1107 { 831, 2, 266, 2, 4083, 0 }, 1108 { 924, 2, 262, 2, 4019, 0 }, 1109 { 929, 2, 262, 2, 4019, 0 }, 1110 { 888, 2, 262, 2, 4019, 0 }, 1111 { 894, 2, 262, 2, 4019, 0 }, 1112 { 900, 2, 262, 2, 4019, 0 }, 1113 { 906, 2, 262, 2, 4019, 0 }, 1114 { 912, 2, 262, 2, 4019, 0 }, 1115 { 918, 2, 262, 2, 4019, 0 }, 1116 { 874, 117, 260, 13, 51, 12 }, 1117 { 878, 117, 260, 13, 51, 12 }, 1118 { 844, 117, 260, 13, 51, 12 }, 1119 { 849, 117, 260, 13, 51, 12 }, 1120 { 854, 117, 260, 13, 51, 12 }, 1121 { 859, 117, 260, 13, 51, 12 }, 1122 { 864, 117, 260, 13, 51, 12 }, 1123 { 869, 117, 260, 13, 51, 12 }, 1124 { 1152, 77, 263, 3, 643, 5 }, 1125 { 1156, 77, 263, 3, 643, 5 }, 1126 { 1122, 77, 263, 3, 643, 5 }, 1127 { 1127, 77, 263, 3, 643, 5 }, 1128 { 1132, 77, 263, 3, 643, 5 }, 1129 { 1137, 77, 263, 3, 643, 5 }, 1130 { 1142, 77, 263, 3, 643, 5 }, 1131 { 1147, 77, 263, 3, 643, 5 }, 1132 { 992, 2, 259, 2, 3987, 0 }, 1133 { 997, 2, 259, 2, 3987, 0 }, 1134 { 956, 2, 259, 2, 3987, 0 }, 1135 { 962, 2, 259, 2, 3987, 0 }, 1136 { 968, 2, 259, 2, 3987, 0 }, 1137 { 974, 2, 259, 2, 3987, 0 }, 1138 { 980, 2, 259, 2, 3987, 0 }, 1139 { 986, 2, 259, 2, 3987, 0 }, 1140 { 172, 46, 2, 22, 690, 19 }, 1141 { 345, 49, 2, 22, 690, 19 }, 1142 { 508, 52, 2, 22, 690, 19 }, 1143 { 651, 55, 2, 22, 690, 19 }, 1144}; 1145 1146extern const MCPhysReg X86RegUnitRoots[][2] = { 1147 { X86::AH }, 1148 { X86::AL }, 1149 { X86::BH }, 1150 { X86::BL }, 1151 { X86::BPL }, 1152 { X86::BPH }, 1153 { X86::CH }, 1154 { X86::CL }, 1155 { X86::CS }, 1156 { X86::DF }, 1157 { X86::DH }, 1158 { X86::DIL }, 1159 { X86::DIH }, 1160 { X86::DL }, 1161 { X86::DS }, 1162 { X86::HAX }, 1163 { X86::HBP }, 1164 { X86::HBX }, 1165 { X86::HCX }, 1166 { X86::HDI }, 1167 { X86::HDX }, 1168 { X86::EFLAGS }, 1169 { X86::IP }, 1170 { X86::HIP }, 1171 { X86::EIZ }, 1172 { X86::ES }, 1173 { X86::SIL }, 1174 { X86::SIH }, 1175 { X86::HSI }, 1176 { X86::SPL }, 1177 { X86::SPH }, 1178 { X86::HSP }, 1179 { X86::FPCW }, 1180 { X86::FPSW }, 1181 { X86::FS }, 1182 { X86::GS }, 1183 { X86::MXCSR }, 1184 { X86::RIZ }, 1185 { X86::SS }, 1186 { X86::SSP }, 1187 { X86::BND0 }, 1188 { X86::BND1 }, 1189 { X86::BND2 }, 1190 { X86::BND3 }, 1191 { X86::CR0 }, 1192 { X86::CR1 }, 1193 { X86::CR2 }, 1194 { X86::CR3 }, 1195 { X86::CR4 }, 1196 { X86::CR5 }, 1197 { X86::CR6 }, 1198 { X86::CR7 }, 1199 { X86::CR8 }, 1200 { X86::CR9 }, 1201 { X86::CR10 }, 1202 { X86::CR11 }, 1203 { X86::CR12 }, 1204 { X86::CR13 }, 1205 { X86::CR14 }, 1206 { X86::CR15 }, 1207 { X86::DR0 }, 1208 { X86::DR1 }, 1209 { X86::DR2 }, 1210 { X86::DR3 }, 1211 { X86::DR4 }, 1212 { X86::DR5 }, 1213 { X86::DR6 }, 1214 { X86::DR7 }, 1215 { X86::DR8 }, 1216 { X86::DR9 }, 1217 { X86::DR10 }, 1218 { X86::DR11 }, 1219 { X86::DR12 }, 1220 { X86::DR13 }, 1221 { X86::DR14 }, 1222 { X86::DR15 }, 1223 { X86::FP0 }, 1224 { X86::FP1 }, 1225 { X86::FP2 }, 1226 { X86::FP3 }, 1227 { X86::FP4 }, 1228 { X86::FP5 }, 1229 { X86::FP6 }, 1230 { X86::FP7 }, 1231 { X86::K0 }, 1232 { X86::K1 }, 1233 { X86::K2 }, 1234 { X86::K3 }, 1235 { X86::K4 }, 1236 { X86::K5 }, 1237 { X86::K6 }, 1238 { X86::K7 }, 1239 { X86::MM0 }, 1240 { X86::MM1 }, 1241 { X86::MM2 }, 1242 { X86::MM3 }, 1243 { X86::MM4 }, 1244 { X86::MM5 }, 1245 { X86::MM6 }, 1246 { X86::MM7 }, 1247 { X86::R8B }, 1248 { X86::R8BH }, 1249 { X86::R8WH }, 1250 { X86::R9B }, 1251 { X86::R9BH }, 1252 { X86::R9WH }, 1253 { X86::R10B }, 1254 { X86::R10BH }, 1255 { X86::R10WH }, 1256 { X86::R11B }, 1257 { X86::R11BH }, 1258 { X86::R11WH }, 1259 { X86::R12B }, 1260 { X86::R12BH }, 1261 { X86::R12WH }, 1262 { X86::R13B }, 1263 { X86::R13BH }, 1264 { X86::R13WH }, 1265 { X86::R14B }, 1266 { X86::R14BH }, 1267 { X86::R14WH }, 1268 { X86::R15B }, 1269 { X86::R15BH }, 1270 { X86::R15WH }, 1271 { X86::ST0 }, 1272 { X86::ST1 }, 1273 { X86::ST2 }, 1274 { X86::ST3 }, 1275 { X86::ST4 }, 1276 { X86::ST5 }, 1277 { X86::ST6 }, 1278 { X86::ST7 }, 1279 { X86::XMM0 }, 1280 { X86::XMM1 }, 1281 { X86::XMM2 }, 1282 { X86::XMM3 }, 1283 { X86::XMM4 }, 1284 { X86::XMM5 }, 1285 { X86::XMM6 }, 1286 { X86::XMM7 }, 1287 { X86::XMM8 }, 1288 { X86::XMM9 }, 1289 { X86::XMM10 }, 1290 { X86::XMM11 }, 1291 { X86::XMM12 }, 1292 { X86::XMM13 }, 1293 { X86::XMM14 }, 1294 { X86::XMM15 }, 1295 { X86::XMM16 }, 1296 { X86::XMM17 }, 1297 { X86::XMM18 }, 1298 { X86::XMM19 }, 1299 { X86::XMM20 }, 1300 { X86::XMM21 }, 1301 { X86::XMM22 }, 1302 { X86::XMM23 }, 1303 { X86::XMM24 }, 1304 { X86::XMM25 }, 1305 { X86::XMM26 }, 1306 { X86::XMM27 }, 1307 { X86::XMM28 }, 1308 { X86::XMM29 }, 1309 { X86::XMM30 }, 1310 { X86::XMM31 }, 1311}; 1312 1313namespace { // Register classes... 1314 // GR8 Register Class... 1315 const MCPhysReg GR8[] = { 1316 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 1317 }; 1318 1319 // GR8 Bit set. 1320 const uint8_t GR8Bits[] = { 1321 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1322 }; 1323 1324 // GRH8 Register Class... 1325 const MCPhysReg GRH8[] = { 1326 X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 1327 }; 1328 1329 // GRH8 Bit set. 1330 const uint8_t GRH8Bits[] = { 1331 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1332 }; 1333 1334 // GR8_NOREX Register Class... 1335 const MCPhysReg GR8_NOREX[] = { 1336 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 1337 }; 1338 1339 // GR8_NOREX Bit set. 1340 const uint8_t GR8_NOREXBits[] = { 1341 0x36, 0x8c, 0x08, 1342 }; 1343 1344 // GR8_ABCD_H Register Class... 1345 const MCPhysReg GR8_ABCD_H[] = { 1346 X86::AH, X86::CH, X86::DH, X86::BH, 1347 }; 1348 1349 // GR8_ABCD_H Bit set. 1350 const uint8_t GR8_ABCD_HBits[] = { 1351 0x12, 0x84, 1352 }; 1353 1354 // GR8_ABCD_L Register Class... 1355 const MCPhysReg GR8_ABCD_L[] = { 1356 X86::AL, X86::CL, X86::DL, X86::BL, 1357 }; 1358 1359 // GR8_ABCD_L Bit set. 1360 const uint8_t GR8_ABCD_LBits[] = { 1361 0x24, 0x08, 0x08, 1362 }; 1363 1364 // GRH16 Register Class... 1365 const MCPhysReg GRH16[] = { 1366 X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 1367 }; 1368 1369 // GRH16 Bit set. 1370 const uint8_t GRH16Bits[] = { 1371 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1372 }; 1373 1374 // GR16 Register Class... 1375 const MCPhysReg GR16[] = { 1376 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 1377 }; 1378 1379 // GR16 Bit set. 1380 const uint8_t GR16Bits[] = { 1381 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1382 }; 1383 1384 // GR16_NOREX Register Class... 1385 const MCPhysReg GR16_NOREX[] = { 1386 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 1387 }; 1388 1389 // GR16_NOREX Bit set. 1390 const uint8_t GR16_NOREXBits[] = { 1391 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x48, 1392 }; 1393 1394 // VK1 Register Class... 1395 const MCPhysReg VK1[] = { 1396 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1397 }; 1398 1399 // VK1 Bit set. 1400 const uint8_t VK1Bits[] = { 1401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1402 }; 1403 1404 // VK16 Register Class... 1405 const MCPhysReg VK16[] = { 1406 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1407 }; 1408 1409 // VK16 Bit set. 1410 const uint8_t VK16Bits[] = { 1411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1412 }; 1413 1414 // VK2 Register Class... 1415 const MCPhysReg VK2[] = { 1416 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1417 }; 1418 1419 // VK2 Bit set. 1420 const uint8_t VK2Bits[] = { 1421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1422 }; 1423 1424 // VK4 Register Class... 1425 const MCPhysReg VK4[] = { 1426 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1427 }; 1428 1429 // VK4 Bit set. 1430 const uint8_t VK4Bits[] = { 1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1432 }; 1433 1434 // VK8 Register Class... 1435 const MCPhysReg VK8[] = { 1436 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1437 }; 1438 1439 // VK8 Bit set. 1440 const uint8_t VK8Bits[] = { 1441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1442 }; 1443 1444 // VK16WM Register Class... 1445 const MCPhysReg VK16WM[] = { 1446 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1447 }; 1448 1449 // VK16WM Bit set. 1450 const uint8_t VK16WMBits[] = { 1451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1452 }; 1453 1454 // VK1WM Register Class... 1455 const MCPhysReg VK1WM[] = { 1456 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1457 }; 1458 1459 // VK1WM Bit set. 1460 const uint8_t VK1WMBits[] = { 1461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1462 }; 1463 1464 // VK2WM Register Class... 1465 const MCPhysReg VK2WM[] = { 1466 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1467 }; 1468 1469 // VK2WM Bit set. 1470 const uint8_t VK2WMBits[] = { 1471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1472 }; 1473 1474 // VK4WM Register Class... 1475 const MCPhysReg VK4WM[] = { 1476 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1477 }; 1478 1479 // VK4WM Bit set. 1480 const uint8_t VK4WMBits[] = { 1481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1482 }; 1483 1484 // VK8WM Register Class... 1485 const MCPhysReg VK8WM[] = { 1486 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1487 }; 1488 1489 // VK8WM Bit set. 1490 const uint8_t VK8WMBits[] = { 1491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1492 }; 1493 1494 // SEGMENT_REG Register Class... 1495 const MCPhysReg SEGMENT_REG[] = { 1496 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 1497 }; 1498 1499 // SEGMENT_REG Bit set. 1500 const uint8_t SEGMENT_REGBits[] = { 1501 0x00, 0x10, 0x10, 0x80, 0x30, 0x00, 0x00, 0x00, 0x02, 1502 }; 1503 1504 // GR16_ABCD Register Class... 1505 const MCPhysReg GR16_ABCD[] = { 1506 X86::AX, X86::CX, X86::DX, X86::BX, 1507 }; 1508 1509 // GR16_ABCD Bit set. 1510 const uint8_t GR16_ABCDBits[] = { 1511 0x08, 0x22, 0x20, 1512 }; 1513 1514 // FPCCR Register Class... 1515 const MCPhysReg FPCCR[] = { 1516 X86::FPSW, 1517 }; 1518 1519 // FPCCR Bit set. 1520 const uint8_t FPCCRBits[] = { 1521 0x00, 0x00, 0x00, 0x00, 0x08, 1522 }; 1523 1524 // VK16PAIR Register Class... 1525 const MCPhysReg VK16PAIR[] = { 1526 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 1527 }; 1528 1529 // VK16PAIR Bit set. 1530 const uint8_t VK16PAIRBits[] = { 1531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1532 }; 1533 1534 // VK1PAIR Register Class... 1535 const MCPhysReg VK1PAIR[] = { 1536 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 1537 }; 1538 1539 // VK1PAIR Bit set. 1540 const uint8_t VK1PAIRBits[] = { 1541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1542 }; 1543 1544 // VK2PAIR Register Class... 1545 const MCPhysReg VK2PAIR[] = { 1546 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 1547 }; 1548 1549 // VK2PAIR Bit set. 1550 const uint8_t VK2PAIRBits[] = { 1551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1552 }; 1553 1554 // VK4PAIR Register Class... 1555 const MCPhysReg VK4PAIR[] = { 1556 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 1557 }; 1558 1559 // VK4PAIR Bit set. 1560 const uint8_t VK4PAIRBits[] = { 1561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1562 }; 1563 1564 // VK8PAIR Register Class... 1565 const MCPhysReg VK8PAIR[] = { 1566 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 1567 }; 1568 1569 // VK8PAIR Bit set. 1570 const uint8_t VK8PAIRBits[] = { 1571 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1572 }; 1573 1574 // VK16PAIR_with_sub_mask_0_in_VK16WM Register Class... 1575 const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = { 1576 X86::K2_K3, X86::K4_K5, X86::K6_K7, 1577 }; 1578 1579 // VK16PAIR_with_sub_mask_0_in_VK16WM Bit set. 1580 const uint8_t VK16PAIR_with_sub_mask_0_in_VK16WMBits[] = { 1581 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 1582 }; 1583 1584 // FR32X Register Class... 1585 const MCPhysReg FR32X[] = { 1586 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 1587 }; 1588 1589 // FR32X Bit set. 1590 const uint8_t FR32XBits[] = { 1591 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 1592 }; 1593 1594 // LOW32_ADDR_ACCESS_RBP Register Class... 1595 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = { 1596 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 1597 }; 1598 1599 // LOW32_ADDR_ACCESS_RBP Bit set. 1600 const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = { 1601 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1602 }; 1603 1604 // LOW32_ADDR_ACCESS Register Class... 1605 const MCPhysReg LOW32_ADDR_ACCESS[] = { 1606 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 1607 }; 1608 1609 // LOW32_ADDR_ACCESS Bit set. 1610 const uint8_t LOW32_ADDR_ACCESSBits[] = { 1611 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1612 }; 1613 1614 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class... 1615 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = { 1616 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 1617 }; 1618 1619 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set. 1620 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = { 1621 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1622 }; 1623 1624 // DEBUG_REG Register Class... 1625 const MCPhysReg DEBUG_REG[] = { 1626 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 1627 }; 1628 1629 // DEBUG_REG Bit set. 1630 const uint8_t DEBUG_REGBits[] = { 1631 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1632 }; 1633 1634 // FR32 Register Class... 1635 const MCPhysReg FR32[] = { 1636 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 1637 }; 1638 1639 // FR32 Bit set. 1640 const uint8_t FR32Bits[] = { 1641 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1642 }; 1643 1644 // GR32 Register Class... 1645 const MCPhysReg GR32[] = { 1646 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 1647 }; 1648 1649 // GR32 Bit set. 1650 const uint8_t GR32Bits[] = { 1651 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1652 }; 1653 1654 // GR32_NOSP Register Class... 1655 const MCPhysReg GR32_NOSP[] = { 1656 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 1657 }; 1658 1659 // GR32_NOSP Bit set. 1660 const uint8_t GR32_NOSPBits[] = { 1661 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1662 }; 1663 1664 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class... 1665 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = { 1666 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 1667 }; 1668 1669 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set. 1670 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = { 1671 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x04, 1672 }; 1673 1674 // GR32_NOREX Register Class... 1675 const MCPhysReg GR32_NOREX[] = { 1676 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 1677 }; 1678 1679 // GR32_NOREX Bit set. 1680 const uint8_t GR32_NOREXBits[] = { 1681 0x00, 0x00, 0xc0, 0x0f, 0x03, 1682 }; 1683 1684 // VK32 Register Class... 1685 const MCPhysReg VK32[] = { 1686 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1687 }; 1688 1689 // VK32 Bit set. 1690 const uint8_t VK32Bits[] = { 1691 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1692 }; 1693 1694 // GR32_NOREX_NOSP Register Class... 1695 const MCPhysReg GR32_NOREX_NOSP[] = { 1696 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 1697 }; 1698 1699 // GR32_NOREX_NOSP Bit set. 1700 const uint8_t GR32_NOREX_NOSPBits[] = { 1701 0x00, 0x00, 0xc0, 0x0f, 0x01, 1702 }; 1703 1704 // RFP32 Register Class... 1705 const MCPhysReg RFP32[] = { 1706 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 1707 }; 1708 1709 // RFP32 Bit set. 1710 const uint8_t RFP32Bits[] = { 1711 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 1712 }; 1713 1714 // VK32WM Register Class... 1715 const MCPhysReg VK32WM[] = { 1716 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 1717 }; 1718 1719 // VK32WM Bit set. 1720 const uint8_t VK32WMBits[] = { 1721 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1722 }; 1723 1724 // GR32_ABCD Register Class... 1725 const MCPhysReg GR32_ABCD[] = { 1726 X86::EAX, X86::ECX, X86::EDX, X86::EBX, 1727 }; 1728 1729 // GR32_ABCD Bit set. 1730 const uint8_t GR32_ABCDBits[] = { 1731 0x00, 0x00, 0x40, 0x0b, 1732 }; 1733 1734 // GR32_TC Register Class... 1735 const MCPhysReg GR32_TC[] = { 1736 X86::EAX, X86::ECX, X86::EDX, X86::ESP, 1737 }; 1738 1739 // GR32_TC Bit set. 1740 const uint8_t GR32_TCBits[] = { 1741 0x00, 0x00, 0x40, 0x0a, 0x02, 1742 }; 1743 1744 // GR32_ABCD_and_GR32_TC Register Class... 1745 const MCPhysReg GR32_ABCD_and_GR32_TC[] = { 1746 X86::EAX, X86::ECX, X86::EDX, 1747 }; 1748 1749 // GR32_ABCD_and_GR32_TC Bit set. 1750 const uint8_t GR32_ABCD_and_GR32_TCBits[] = { 1751 0x00, 0x00, 0x40, 0x0a, 1752 }; 1753 1754 // GR32_AD Register Class... 1755 const MCPhysReg GR32_AD[] = { 1756 X86::EAX, X86::EDX, 1757 }; 1758 1759 // GR32_AD Bit set. 1760 const uint8_t GR32_ADBits[] = { 1761 0x00, 0x00, 0x40, 0x08, 1762 }; 1763 1764 // GR32_BPSP Register Class... 1765 const MCPhysReg GR32_BPSP[] = { 1766 X86::EBP, X86::ESP, 1767 }; 1768 1769 // GR32_BPSP Bit set. 1770 const uint8_t GR32_BPSPBits[] = { 1771 0x00, 0x00, 0x80, 0x00, 0x02, 1772 }; 1773 1774 // GR32_BSI Register Class... 1775 const MCPhysReg GR32_BSI[] = { 1776 X86::EBX, X86::ESI, 1777 }; 1778 1779 // GR32_BSI Bit set. 1780 const uint8_t GR32_BSIBits[] = { 1781 0x00, 0x00, 0x00, 0x01, 0x01, 1782 }; 1783 1784 // GR32_CB Register Class... 1785 const MCPhysReg GR32_CB[] = { 1786 X86::ECX, X86::EBX, 1787 }; 1788 1789 // GR32_CB Bit set. 1790 const uint8_t GR32_CBBits[] = { 1791 0x00, 0x00, 0x00, 0x03, 1792 }; 1793 1794 // GR32_DC Register Class... 1795 const MCPhysReg GR32_DC[] = { 1796 X86::EDX, X86::ECX, 1797 }; 1798 1799 // GR32_DC Bit set. 1800 const uint8_t GR32_DCBits[] = { 1801 0x00, 0x00, 0x00, 0x0a, 1802 }; 1803 1804 // GR32_DIBP Register Class... 1805 const MCPhysReg GR32_DIBP[] = { 1806 X86::EDI, X86::EBP, 1807 }; 1808 1809 // GR32_DIBP Bit set. 1810 const uint8_t GR32_DIBPBits[] = { 1811 0x00, 0x00, 0x80, 0x04, 1812 }; 1813 1814 // GR32_SIDI Register Class... 1815 const MCPhysReg GR32_SIDI[] = { 1816 X86::ESI, X86::EDI, 1817 }; 1818 1819 // GR32_SIDI Bit set. 1820 const uint8_t GR32_SIDIBits[] = { 1821 0x00, 0x00, 0x00, 0x04, 0x01, 1822 }; 1823 1824 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class... 1825 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = { 1826 X86::RIP, X86::RBP, 1827 }; 1828 1829 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set. 1830 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = { 1831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 1832 }; 1833 1834 // CCR Register Class... 1835 const MCPhysReg CCR[] = { 1836 X86::EFLAGS, 1837 }; 1838 1839 // CCR Bit set. 1840 const uint8_t CCRBits[] = { 1841 0x00, 0x00, 0x00, 0x10, 1842 }; 1843 1844 // DFCCR Register Class... 1845 const MCPhysReg DFCCR[] = { 1846 X86::DF, 1847 }; 1848 1849 // DFCCR Bit set. 1850 const uint8_t DFCCRBits[] = { 1851 0x00, 0x40, 1852 }; 1853 1854 // GR32_ABCD_and_GR32_BSI Register Class... 1855 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = { 1856 X86::EBX, 1857 }; 1858 1859 // GR32_ABCD_and_GR32_BSI Bit set. 1860 const uint8_t GR32_ABCD_and_GR32_BSIBits[] = { 1861 0x00, 0x00, 0x00, 0x01, 1862 }; 1863 1864 // GR32_AD_and_GR32_DC Register Class... 1865 const MCPhysReg GR32_AD_and_GR32_DC[] = { 1866 X86::EDX, 1867 }; 1868 1869 // GR32_AD_and_GR32_DC Bit set. 1870 const uint8_t GR32_AD_and_GR32_DCBits[] = { 1871 0x00, 0x00, 0x00, 0x08, 1872 }; 1873 1874 // GR32_BPSP_and_GR32_DIBP Register Class... 1875 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = { 1876 X86::EBP, 1877 }; 1878 1879 // GR32_BPSP_and_GR32_DIBP Bit set. 1880 const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = { 1881 0x00, 0x00, 0x80, 1882 }; 1883 1884 // GR32_BPSP_and_GR32_TC Register Class... 1885 const MCPhysReg GR32_BPSP_and_GR32_TC[] = { 1886 X86::ESP, 1887 }; 1888 1889 // GR32_BPSP_and_GR32_TC Bit set. 1890 const uint8_t GR32_BPSP_and_GR32_TCBits[] = { 1891 0x00, 0x00, 0x00, 0x00, 0x02, 1892 }; 1893 1894 // GR32_BSI_and_GR32_SIDI Register Class... 1895 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = { 1896 X86::ESI, 1897 }; 1898 1899 // GR32_BSI_and_GR32_SIDI Bit set. 1900 const uint8_t GR32_BSI_and_GR32_SIDIBits[] = { 1901 0x00, 0x00, 0x00, 0x00, 0x01, 1902 }; 1903 1904 // GR32_CB_and_GR32_DC Register Class... 1905 const MCPhysReg GR32_CB_and_GR32_DC[] = { 1906 X86::ECX, 1907 }; 1908 1909 // GR32_CB_and_GR32_DC Bit set. 1910 const uint8_t GR32_CB_and_GR32_DCBits[] = { 1911 0x00, 0x00, 0x00, 0x02, 1912 }; 1913 1914 // GR32_DIBP_and_GR32_SIDI Register Class... 1915 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = { 1916 X86::EDI, 1917 }; 1918 1919 // GR32_DIBP_and_GR32_SIDI Bit set. 1920 const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = { 1921 0x00, 0x00, 0x00, 0x04, 1922 }; 1923 1924 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class... 1925 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = { 1926 X86::RBP, 1927 }; 1928 1929 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set. 1930 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = { 1931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 1932 }; 1933 1934 // LOW32_ADDR_ACCESS_with_sub_32bit Register Class... 1935 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = { 1936 X86::RIP, 1937 }; 1938 1939 // LOW32_ADDR_ACCESS_with_sub_32bit Bit set. 1940 const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = { 1941 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 1942 }; 1943 1944 // RFP64 Register Class... 1945 const MCPhysReg RFP64[] = { 1946 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 1947 }; 1948 1949 // RFP64 Bit set. 1950 const uint8_t RFP64Bits[] = { 1951 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 1952 }; 1953 1954 // FR64X Register Class... 1955 const MCPhysReg FR64X[] = { 1956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 1957 }; 1958 1959 // FR64X Bit set. 1960 const uint8_t FR64XBits[] = { 1961 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 1962 }; 1963 1964 // GR64 Register Class... 1965 const MCPhysReg GR64[] = { 1966 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 1967 }; 1968 1969 // GR64 Bit set. 1970 const uint8_t GR64Bits[] = { 1971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1972 }; 1973 1974 // CONTROL_REG Register Class... 1975 const MCPhysReg CONTROL_REG[] = { 1976 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 1977 }; 1978 1979 // CONTROL_REG Bit set. 1980 const uint8_t CONTROL_REGBits[] = { 1981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1982 }; 1983 1984 // FR64 Register Class... 1985 const MCPhysReg FR64[] = { 1986 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 1987 }; 1988 1989 // FR64 Bit set. 1990 const uint8_t FR64Bits[] = { 1991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1992 }; 1993 1994 // GR64_with_sub_8bit Register Class... 1995 const MCPhysReg GR64_with_sub_8bit[] = { 1996 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 1997 }; 1998 1999 // GR64_with_sub_8bit Bit set. 2000 const uint8_t GR64_with_sub_8bitBits[] = { 2001 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 2002 }; 2003 2004 // GR64_NOSP Register Class... 2005 const MCPhysReg GR64_NOSP[] = { 2006 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 2007 }; 2008 2009 // GR64_NOSP Bit set. 2010 const uint8_t GR64_NOSPBits[] = { 2011 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 2012 }; 2013 2014 // GR64_TC Register Class... 2015 const MCPhysReg GR64_TC[] = { 2016 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 2017 }; 2018 2019 // GR64_TC Bit set. 2020 const uint8_t GR64_TCBits[] = { 2021 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2022 }; 2023 2024 // GR64_NOREX Register Class... 2025 const MCPhysReg GR64_NOREX[] = { 2026 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 2027 }; 2028 2029 // GR64_NOREX Bit set. 2030 const uint8_t GR64_NOREXBits[] = { 2031 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 2032 }; 2033 2034 // GR64_TCW64 Register Class... 2035 const MCPhysReg GR64_TCW64[] = { 2036 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP, 2037 }; 2038 2039 // GR64_TCW64 Bit set. 2040 const uint8_t GR64_TCW64Bits[] = { 2041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 2042 }; 2043 2044 // GR64_TC_with_sub_8bit Register Class... 2045 const MCPhysReg GR64_TC_with_sub_8bit[] = { 2046 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP, 2047 }; 2048 2049 // GR64_TC_with_sub_8bit Bit set. 2050 const uint8_t GR64_TC_with_sub_8bitBits[] = { 2051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2052 }; 2053 2054 // GR64_NOSP_and_GR64_TC Register Class... 2055 const MCPhysReg GR64_NOSP_and_GR64_TC[] = { 2056 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 2057 }; 2058 2059 // GR64_NOSP_and_GR64_TC Bit set. 2060 const uint8_t GR64_NOSP_and_GR64_TCBits[] = { 2061 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2062 }; 2063 2064 // GR64_TCW64_with_sub_8bit Register Class... 2065 const MCPhysReg GR64_TCW64_with_sub_8bit[] = { 2066 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP, 2067 }; 2068 2069 // GR64_TCW64_with_sub_8bit Bit set. 2070 const uint8_t GR64_TCW64_with_sub_8bitBits[] = { 2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 2072 }; 2073 2074 // GR64_TC_and_GR64_TCW64 Register Class... 2075 const MCPhysReg GR64_TC_and_GR64_TCW64[] = { 2076 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 2077 }; 2078 2079 // GR64_TC_and_GR64_TCW64 Bit set. 2080 const uint8_t GR64_TC_and_GR64_TCW64Bits[] = { 2081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2082 }; 2083 2084 // GR64_with_sub_16bit_in_GR16_NOREX Register Class... 2085 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = { 2086 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 2087 }; 2088 2089 // GR64_with_sub_16bit_in_GR16_NOREX Bit set. 2090 const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = { 2091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x06, 2092 }; 2093 2094 // VK64 Register Class... 2095 const MCPhysReg VK64[] = { 2096 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 2097 }; 2098 2099 // VK64 Bit set. 2100 const uint8_t VK64Bits[] = { 2101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 2102 }; 2103 2104 // VR64 Register Class... 2105 const MCPhysReg VR64[] = { 2106 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 2107 }; 2108 2109 // VR64 Bit set. 2110 const uint8_t VR64Bits[] = { 2111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 2112 }; 2113 2114 // GR64_NOREX_NOSP Register Class... 2115 const MCPhysReg GR64_NOREX_NOSP[] = { 2116 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 2117 }; 2118 2119 // GR64_NOREX_NOSP Bit set. 2120 const uint8_t GR64_NOREX_NOSPBits[] = { 2121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x02, 2122 }; 2123 2124 // GR64_NOREX_and_GR64_TC Register Class... 2125 const MCPhysReg GR64_NOREX_and_GR64_TC[] = { 2126 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP, 2127 }; 2128 2129 // GR64_NOREX_and_GR64_TC Bit set. 2130 const uint8_t GR64_NOREX_and_GR64_TCBits[] = { 2131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x06, 2132 }; 2133 2134 // GR64_NOSP_and_GR64_TCW64 Register Class... 2135 const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = { 2136 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 2137 }; 2138 2139 // GR64_NOSP_and_GR64_TCW64 Bit set. 2140 const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = { 2141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 2142 }; 2143 2144 // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class... 2145 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = { 2146 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP, 2147 }; 2148 2149 // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set. 2150 const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = { 2151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2152 }; 2153 2154 // VK64WM Register Class... 2155 const MCPhysReg VK64WM[] = { 2156 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 2157 }; 2158 2159 // VK64WM Bit set. 2160 const uint8_t VK64WMBits[] = { 2161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 2162 }; 2163 2164 // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class... 2165 const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = { 2166 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 2167 }; 2168 2169 // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set. 2170 const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = { 2171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 2172 }; 2173 2174 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class... 2175 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = { 2176 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, 2177 }; 2178 2179 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set. 2180 const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = { 2181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x06, 2182 }; 2183 2184 // GR64_NOREX_NOSP_and_GR64_TC Register Class... 2185 const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = { 2186 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 2187 }; 2188 2189 // GR64_NOREX_NOSP_and_GR64_TC Bit set. 2190 const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = { 2191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 2192 }; 2193 2194 // GR64_NOREX_and_GR64_TCW64 Register Class... 2195 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = { 2196 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP, 2197 }; 2198 2199 // GR64_NOREX_and_GR64_TCW64 Bit set. 2200 const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = { 2201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 2202 }; 2203 2204 // GR64_ABCD Register Class... 2205 const MCPhysReg GR64_ABCD[] = { 2206 X86::RAX, X86::RCX, X86::RDX, X86::RBX, 2207 }; 2208 2209 // GR64_ABCD Bit set. 2210 const uint8_t GR64_ABCDBits[] = { 2211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 2212 }; 2213 2214 // GR64_with_sub_32bit_in_GR32_TC Register Class... 2215 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = { 2216 X86::RAX, X86::RCX, X86::RDX, X86::RSP, 2217 }; 2218 2219 // GR64_with_sub_32bit_in_GR32_TC Bit set. 2220 const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = { 2221 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 2222 }; 2223 2224 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class... 2225 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = { 2226 X86::RAX, X86::RCX, X86::RDX, 2227 }; 2228 2229 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set. 2230 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = { 2231 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 2232 }; 2233 2234 // GR64_AD Register Class... 2235 const MCPhysReg GR64_AD[] = { 2236 X86::RAX, X86::RDX, 2237 }; 2238 2239 // GR64_AD Bit set. 2240 const uint8_t GR64_ADBits[] = { 2241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 2242 }; 2243 2244 // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class... 2245 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = { 2246 X86::RBP, X86::RIP, 2247 }; 2248 2249 // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set. 2250 const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = { 2251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 2252 }; 2253 2254 // GR64_with_sub_32bit_in_GR32_BPSP Register Class... 2255 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = { 2256 X86::RBP, X86::RSP, 2257 }; 2258 2259 // GR64_with_sub_32bit_in_GR32_BPSP Bit set. 2260 const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = { 2261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 2262 }; 2263 2264 // GR64_with_sub_32bit_in_GR32_BSI Register Class... 2265 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = { 2266 X86::RSI, X86::RBX, 2267 }; 2268 2269 // GR64_with_sub_32bit_in_GR32_BSI Bit set. 2270 const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = { 2271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x02, 2272 }; 2273 2274 // GR64_with_sub_32bit_in_GR32_CB Register Class... 2275 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = { 2276 X86::RCX, X86::RBX, 2277 }; 2278 2279 // GR64_with_sub_32bit_in_GR32_CB Bit set. 2280 const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = { 2281 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 2282 }; 2283 2284 // GR64_with_sub_32bit_in_GR32_DC Register Class... 2285 const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = { 2286 X86::RCX, X86::RDX, 2287 }; 2288 2289 // GR64_with_sub_32bit_in_GR32_DC Bit set. 2290 const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = { 2291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 2292 }; 2293 2294 // GR64_with_sub_32bit_in_GR32_DIBP Register Class... 2295 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = { 2296 X86::RDI, X86::RBP, 2297 }; 2298 2299 // GR64_with_sub_32bit_in_GR32_DIBP Bit set. 2300 const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = { 2301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 2302 }; 2303 2304 // GR64_with_sub_32bit_in_GR32_SIDI Register Class... 2305 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = { 2306 X86::RSI, X86::RDI, 2307 }; 2308 2309 // GR64_with_sub_32bit_in_GR32_SIDI Bit set. 2310 const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = { 2311 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, 2312 }; 2313 2314 // GR64_and_LOW32_ADDR_ACCESS Register Class... 2315 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = { 2316 X86::RIP, 2317 }; 2318 2319 // GR64_and_LOW32_ADDR_ACCESS Bit set. 2320 const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = { 2321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 2322 }; 2323 2324 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class... 2325 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = { 2326 X86::RBX, 2327 }; 2328 2329 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set. 2330 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = { 2331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 2332 }; 2333 2334 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class... 2335 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = { 2336 X86::RDX, 2337 }; 2338 2339 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set. 2340 const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = { 2341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 2342 }; 2343 2344 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class... 2345 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = { 2346 X86::RBP, 2347 }; 2348 2349 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set. 2350 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = { 2351 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 2352 }; 2353 2354 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class... 2355 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = { 2356 X86::RSP, 2357 }; 2358 2359 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set. 2360 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = { 2361 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 2362 }; 2363 2364 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class... 2365 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = { 2366 X86::RSI, 2367 }; 2368 2369 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set. 2370 const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = { 2371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 2372 }; 2373 2374 // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class... 2375 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = { 2376 X86::RCX, 2377 }; 2378 2379 // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set. 2380 const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = { 2381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 2382 }; 2383 2384 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class... 2385 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = { 2386 X86::RDI, 2387 }; 2388 2389 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set. 2390 const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = { 2391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 2392 }; 2393 2394 // RST Register Class... 2395 const MCPhysReg RST[] = { 2396 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 2397 }; 2398 2399 // RST Bit set. 2400 const uint8_t RSTBits[] = { 2401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 2402 }; 2403 2404 // RFP80 Register Class... 2405 const MCPhysReg RFP80[] = { 2406 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 2407 }; 2408 2409 // RFP80 Bit set. 2410 const uint8_t RFP80Bits[] = { 2411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 2412 }; 2413 2414 // RFP80_7 Register Class... 2415 const MCPhysReg RFP80_7[] = { 2416 X86::FP7, 2417 }; 2418 2419 // RFP80_7 Bit set. 2420 const uint8_t RFP80_7Bits[] = { 2421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 2422 }; 2423 2424 // VR128X Register Class... 2425 const MCPhysReg VR128X[] = { 2426 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 2427 }; 2428 2429 // VR128X Bit set. 2430 const uint8_t VR128XBits[] = { 2431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 2432 }; 2433 2434 // VR128 Register Class... 2435 const MCPhysReg VR128[] = { 2436 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 2437 }; 2438 2439 // VR128 Bit set. 2440 const uint8_t VR128Bits[] = { 2441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 2442 }; 2443 2444 // BNDR Register Class... 2445 const MCPhysReg BNDR[] = { 2446 X86::BND0, X86::BND1, X86::BND2, X86::BND3, 2447 }; 2448 2449 // BNDR Bit set. 2450 const uint8_t BNDRBits[] = { 2451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 2452 }; 2453 2454 // VR256X Register Class... 2455 const MCPhysReg VR256X[] = { 2456 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 2457 }; 2458 2459 // VR256X Bit set. 2460 const uint8_t VR256XBits[] = { 2461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 2462 }; 2463 2464 // VR256 Register Class... 2465 const MCPhysReg VR256[] = { 2466 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 2467 }; 2468 2469 // VR256 Bit set. 2470 const uint8_t VR256Bits[] = { 2471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 2472 }; 2473 2474 // VR512 Register Class... 2475 const MCPhysReg VR512[] = { 2476 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 2477 }; 2478 2479 // VR512 Bit set. 2480 const uint8_t VR512Bits[] = { 2481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 2482 }; 2483 2484 // VR512_0_15 Register Class... 2485 const MCPhysReg VR512_0_15[] = { 2486 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 2487 }; 2488 2489 // VR512_0_15 Bit set. 2490 const uint8_t VR512_0_15Bits[] = { 2491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 2492 }; 2493 2494} // end anonymous namespace 2495 2496extern const char X86RegClassStrings[] = { 2497 /* 0 */ 'R', 'F', 'P', '8', '0', 0, 2498 /* 6 */ 'V', 'K', '1', 0, 2499 /* 10 */ 'V', 'R', '5', '1', '2', 0, 2500 /* 16 */ 'V', 'K', '3', '2', 0, 2501 /* 21 */ 'R', 'F', 'P', '3', '2', 0, 2502 /* 27 */ 'F', 'R', '3', '2', 0, 2503 /* 32 */ 'G', 'R', '3', '2', 0, 2504 /* 37 */ 'V', 'K', '2', 0, 2505 /* 41 */ 'V', 'K', '6', '4', 0, 2506 /* 46 */ 'R', 'F', 'P', '6', '4', 0, 2507 /* 52 */ 'F', 'R', '6', '4', 0, 2508 /* 57 */ 'G', 'R', '6', '4', 0, 2509 /* 62 */ 'V', 'R', '6', '4', 0, 2510 /* 67 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0, 2511 /* 90 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0, 2512 /* 127 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0, 2513 /* 153 */ 'V', 'K', '4', 0, 2514 /* 157 */ 'V', 'R', '5', '1', '2', '_', '0', '_', '1', '5', 0, 2515 /* 168 */ 'G', 'R', 'H', '1', '6', 0, 2516 /* 174 */ 'V', 'K', '1', '6', 0, 2517 /* 179 */ 'G', 'R', '1', '6', 0, 2518 /* 184 */ 'V', 'R', '2', '5', '6', 0, 2519 /* 190 */ 'R', 'F', 'P', '8', '0', '_', '7', 0, 2520 /* 198 */ 'V', 'R', '1', '2', '8', 0, 2521 /* 204 */ 'G', 'R', 'H', '8', 0, 2522 /* 209 */ 'V', 'K', '8', 0, 2523 /* 213 */ 'G', 'R', '8', 0, 2524 /* 217 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0, 2525 /* 248 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0, 2526 /* 291 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0, 2527 /* 334 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0, 2528 /* 365 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0, 2529 /* 410 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0, 2530 /* 455 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0, 2531 /* 486 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0, 2532 /* 508 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0, 2533 /* 536 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0, 2534 /* 559 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0, 2535 /* 567 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0, 2536 /* 575 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0, 2537 /* 585 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0, 2538 /* 595 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0, 2539 /* 605 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0, 2540 /* 615 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0, 2541 /* 627 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0, 2542 /* 639 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0, 2543 /* 650 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0, 2544 /* 696 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0, 2545 /* 743 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0, 2546 /* 776 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0, 2547 /* 822 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0, 2548 /* 854 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0, 2549 /* 865 */ 'V', 'K', '1', 'W', 'M', 0, 2550 /* 871 */ 'V', 'K', '3', '2', 'W', 'M', 0, 2551 /* 878 */ 'V', 'K', '2', 'W', 'M', 0, 2552 /* 884 */ 'V', 'K', '6', '4', 'W', 'M', 0, 2553 /* 891 */ 'V', 'K', '4', 'W', 'M', 0, 2554 /* 897 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'm', 'a', 's', 'k', '_', '0', '_', 'i', 'n', '_', 'V', 'K', '1', '6', 'W', 'M', 0, 2555 /* 932 */ 'V', 'K', '8', 'W', 'M', 0, 2556 /* 938 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0, 2557 /* 985 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0, 2558 /* 1018 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0, 2559 /* 1049 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0, 2560 /* 1059 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0, 2561 /* 1069 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0, 2562 /* 1085 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0, 2563 /* 1101 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0, 2564 /* 1134 */ 'D', 'F', 'C', 'C', 'R', 0, 2565 /* 1140 */ 'F', 'P', 'C', 'C', 'R', 0, 2566 /* 1146 */ 'B', 'N', 'D', 'R', 0, 2567 /* 1151 */ 'V', 'K', '1', 'P', 'A', 'I', 'R', 0, 2568 /* 1159 */ 'V', 'K', '2', 'P', 'A', 'I', 'R', 0, 2569 /* 1167 */ 'V', 'K', '4', 'P', 'A', 'I', 'R', 0, 2570 /* 1175 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', 0, 2571 /* 1184 */ 'V', 'K', '8', 'P', 'A', 'I', 'R', 0, 2572 /* 1192 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0, 2573 /* 1219 */ 'R', 'S', 'T', 0, 2574 /* 1223 */ 'F', 'R', '3', '2', 'X', 0, 2575 /* 1229 */ 'F', 'R', '6', '4', 'X', 0, 2576 /* 1235 */ 'V', 'R', '2', '5', '6', 'X', 0, 2577 /* 1242 */ 'V', 'R', '1', '2', '8', 'X', 0, 2578 /* 1249 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0, 2579 /* 1260 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0, 2580 /* 1271 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0, 2581 /* 1317 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0, 2582 /* 1368 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0, 2583 /* 1378 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0, 2584 /* 1415 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0, 2585 /* 1448 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0, 2586 /* 1499 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0, 2587 /* 1518 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0, 2588 /* 1543 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0, 2589 /* 1580 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0, 2590}; 2591 2592extern const MCRegisterClass X86MCRegisterClasses[] = { 2593 { GR8, GR8Bits, 213, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true }, 2594 { GRH8, GRH8Bits, 204, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, false }, 2595 { GR8_NOREX, GR8_NOREXBits, 1368, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, true }, 2596 { GR8_ABCD_H, GR8_ABCD_HBits, 639, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, true }, 2597 { GR8_ABCD_L, GR8_ABCD_LBits, 854, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, true }, 2598 { GRH16, GRH16Bits, 168, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 1, false }, 2599 { GR16, GR16Bits, 179, 16, sizeof(GR16Bits), X86::GR16RegClassID, 1, true }, 2600 { GR16_NOREX, GR16_NOREXBits, 1306, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 1, true }, 2601 { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 1, true }, 2602 { VK16, VK16Bits, 174, 8, sizeof(VK16Bits), X86::VK16RegClassID, 1, true }, 2603 { VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 1, true }, 2604 { VK4, VK4Bits, 153, 8, sizeof(VK4Bits), X86::VK4RegClassID, 1, true }, 2605 { VK8, VK8Bits, 209, 8, sizeof(VK8Bits), X86::VK8RegClassID, 1, true }, 2606 { VK16WM, VK16WMBits, 925, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 1, true }, 2607 { VK1WM, VK1WMBits, 865, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 1, true }, 2608 { VK2WM, VK2WMBits, 878, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 1, true }, 2609 { VK4WM, VK4WMBits, 891, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 1, true }, 2610 { VK8WM, VK8WMBits, 932, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 1, true }, 2611 { SEGMENT_REG, SEGMENT_REGBits, 627, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 1, true }, 2612 { GR16_ABCD, GR16_ABCDBits, 595, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 1, true }, 2613 { FPCCR, FPCCRBits, 1140, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, -1, false }, 2614 { VK16PAIR, VK16PAIRBits, 1175, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 1, true }, 2615 { VK1PAIR, VK1PAIRBits, 1151, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 1, true }, 2616 { VK2PAIR, VK2PAIRBits, 1159, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 1, true }, 2617 { VK4PAIR, VK4PAIRBits, 1167, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 1, true }, 2618 { VK8PAIR, VK8PAIRBits, 1184, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 1, true }, 2619 { VK16PAIR_with_sub_mask_0_in_VK16WM, VK16PAIR_with_sub_mask_0_in_VK16WMBits, 897, 3, sizeof(VK16PAIR_with_sub_mask_0_in_VK16WMBits), X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID, 1, true }, 2620 { FR32X, FR32XBits, 1223, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 1, true }, 2621 { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1027, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 1, true }, 2622 { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1201, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 1, true }, 2623 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1580, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 1, true }, 2624 { DEBUG_REG, DEBUG_REGBits, 605, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 1, true }, 2625 { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true }, 2626 { GR32, GR32Bits, 32, 16, sizeof(GR32Bits), X86::GR32RegClassID, 1, true }, 2627 { GR32_NOSP, GR32_NOSPBits, 1049, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 1, true }, 2628 { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1317, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true }, 2629 { GR32_NOREX, GR32_NOREXBits, 1249, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 1, true }, 2630 { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 1, true }, 2631 { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1069, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 1, true }, 2632 { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 1, true }, 2633 { VK32WM, VK32WMBits, 871, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 1, true }, 2634 { GR32_ABCD, GR32_ABCDBits, 575, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 1, true }, 2635 { GR32_TC, GR32_TCBits, 402, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 1, true }, 2636 { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 388, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 1, true }, 2637 { GR32_AD, GR32_ADBits, 559, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 1, true }, 2638 { GR32_BPSP, GR32_BPSPBits, 1124, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 1, true }, 2639 { GR32_BSI, GR32_BSIBits, 813, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 1, true }, 2640 { GR32_CB, GR32_CBBits, 240, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 1, true }, 2641 { GR32_DC, GR32_DCBits, 283, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 1, true }, 2642 { GR32_DIBP, GR32_DIBPBits, 975, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 1, true }, 2643 { GR32_SIDI, GR32_SIDIBits, 686, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 1, true }, 2644 { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1378, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 1, true }, 2645 { CCR, CCRBits, 1136, 1, sizeof(CCRBits), X86::CCRRegClassID, -1, false }, 2646 { DFCCR, DFCCRBits, 1134, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, -1, false }, 2647 { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 799, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 1, true }, 2648 { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 314, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 1, true }, 2649 { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 961, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 1, true }, 2650 { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 433, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 1, true }, 2651 { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 673, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 1, true }, 2652 { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 271, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 1, true }, 2653 { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 719, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 1, true }, 2654 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1448, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 1, true }, 2655 { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1415, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 1, true }, 2656 { RFP64, RFP64Bits, 46, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 1, true }, 2657 { FR64X, FR64XBits, 1229, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true }, 2658 { GR64, GR64Bits, 57, 17, sizeof(GR64Bits), X86::GR64RegClassID, 1, true }, 2659 { CONTROL_REG, CONTROL_REGBits, 615, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 1, true }, 2660 { FR64, FR64Bits, 52, 16, sizeof(FR64Bits), X86::FR64RegClassID, 1, true }, 2661 { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1499, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 1, true }, 2662 { GR64_NOSP, GR64_NOSPBits, 1059, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 1, true }, 2663 { GR64_TC, GR64_TCBits, 500, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 1, true }, 2664 { GR64_NOREX, GR64_NOREXBits, 1260, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 1, true }, 2665 { GR64_TCW64, GR64_TCW64Bits, 79, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 1, true }, 2666 { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1558, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 1, true }, 2667 { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 486, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 1, true }, 2668 { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1518, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 1, true }, 2669 { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 67, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 1, true }, 2670 { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1283, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true }, 2671 { VK64, VK64Bits, 41, 8, sizeof(VK64Bits), X86::VK64RegClassID, 1, true }, 2672 { VR64, VR64Bits, 62, 8, sizeof(VR64Bits), X86::VR64RegClassID, 1, true }, 2673 { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1085, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 1, true }, 2674 { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 536, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 1, true }, 2675 { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 102, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 1, true }, 2676 { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1543, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 1, true }, 2677 { VK64WM, VK64WMBits, 884, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 1, true }, 2678 { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 90, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 1, true }, 2679 { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1271, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true }, 2680 { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 508, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 1, true }, 2681 { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 127, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 1, true }, 2682 { GR64_ABCD, GR64_ABCDBits, 585, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 1, true }, 2683 { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 455, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 1, true }, 2684 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 365, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 1, true }, 2685 { GR64_AD, GR64_ADBits, 567, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 1, true }, 2686 { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1018, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 1, true }, 2687 { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1101, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 1, true }, 2688 { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 822, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 1, true }, 2689 { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 217, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 1, true }, 2690 { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 334, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 1, true }, 2691 { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 985, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 1, true }, 2692 { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 743, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 1, true }, 2693 { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1192, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 1, true }, 2694 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 776, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 1, true }, 2695 { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 291, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 1, true }, 2696 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 938, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 1, true }, 2697 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 410, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 1, true }, 2698 { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 650, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 1, true }, 2699 { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 248, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 1, true }, 2700 { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 696, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 1, true }, 2701 { RST, RSTBits, 1219, 8, sizeof(RSTBits), X86::RSTRegClassID, 1, false }, 2702 { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 1, true }, 2703 { RFP80_7, RFP80_7Bits, 190, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 1, false }, 2704 { VR128X, VR128XBits, 1242, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 1, true }, 2705 { VR128, VR128Bits, 198, 16, sizeof(VR128Bits), X86::VR128RegClassID, 1, true }, 2706 { BNDR, BNDRBits, 1146, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 1, true }, 2707 { VR256X, VR256XBits, 1235, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 1, true }, 2708 { VR256, VR256Bits, 184, 16, sizeof(VR256Bits), X86::VR256RegClassID, 1, true }, 2709 { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 1, true }, 2710 { VR512_0_15, VR512_0_15Bits, 157, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 1, true }, 2711}; 2712 2713// X86 Dwarf<->LLVM register mappings. 2714extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = { 2715 { 0U, X86::RAX }, 2716 { 1U, X86::RDX }, 2717 { 2U, X86::RCX }, 2718 { 3U, X86::RBX }, 2719 { 4U, X86::RSI }, 2720 { 5U, X86::RDI }, 2721 { 6U, X86::RBP }, 2722 { 7U, X86::RSP }, 2723 { 8U, X86::R8 }, 2724 { 9U, X86::R9 }, 2725 { 10U, X86::R10 }, 2726 { 11U, X86::R11 }, 2727 { 12U, X86::R12 }, 2728 { 13U, X86::R13 }, 2729 { 14U, X86::R14 }, 2730 { 15U, X86::R15 }, 2731 { 16U, X86::RIP }, 2732 { 17U, X86::XMM0 }, 2733 { 18U, X86::XMM1 }, 2734 { 19U, X86::XMM2 }, 2735 { 20U, X86::XMM3 }, 2736 { 21U, X86::XMM4 }, 2737 { 22U, X86::XMM5 }, 2738 { 23U, X86::XMM6 }, 2739 { 24U, X86::XMM7 }, 2740 { 25U, X86::XMM8 }, 2741 { 26U, X86::XMM9 }, 2742 { 27U, X86::XMM10 }, 2743 { 28U, X86::XMM11 }, 2744 { 29U, X86::XMM12 }, 2745 { 30U, X86::XMM13 }, 2746 { 31U, X86::XMM14 }, 2747 { 32U, X86::XMM15 }, 2748 { 33U, X86::ST0 }, 2749 { 34U, X86::ST1 }, 2750 { 35U, X86::ST2 }, 2751 { 36U, X86::ST3 }, 2752 { 37U, X86::ST4 }, 2753 { 38U, X86::ST5 }, 2754 { 39U, X86::ST6 }, 2755 { 40U, X86::ST7 }, 2756 { 41U, X86::MM0 }, 2757 { 42U, X86::MM1 }, 2758 { 43U, X86::MM2 }, 2759 { 44U, X86::MM3 }, 2760 { 45U, X86::MM4 }, 2761 { 46U, X86::MM5 }, 2762 { 47U, X86::MM6 }, 2763 { 48U, X86::MM7 }, 2764 { 67U, X86::XMM16 }, 2765 { 68U, X86::XMM17 }, 2766 { 69U, X86::XMM18 }, 2767 { 70U, X86::XMM19 }, 2768 { 71U, X86::XMM20 }, 2769 { 72U, X86::XMM21 }, 2770 { 73U, X86::XMM22 }, 2771 { 74U, X86::XMM23 }, 2772 { 75U, X86::XMM24 }, 2773 { 76U, X86::XMM25 }, 2774 { 77U, X86::XMM26 }, 2775 { 78U, X86::XMM27 }, 2776 { 79U, X86::XMM28 }, 2777 { 80U, X86::XMM29 }, 2778 { 81U, X86::XMM30 }, 2779 { 82U, X86::XMM31 }, 2780 { 118U, X86::K0 }, 2781 { 119U, X86::K1 }, 2782 { 120U, X86::K2 }, 2783 { 121U, X86::K3 }, 2784 { 122U, X86::K4 }, 2785 { 123U, X86::K5 }, 2786 { 124U, X86::K6 }, 2787 { 125U, X86::K7 }, 2788}; 2789extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L); 2790 2791extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = { 2792 { 0U, X86::EAX }, 2793 { 1U, X86::ECX }, 2794 { 2U, X86::EDX }, 2795 { 3U, X86::EBX }, 2796 { 4U, X86::EBP }, 2797 { 5U, X86::ESP }, 2798 { 6U, X86::ESI }, 2799 { 7U, X86::EDI }, 2800 { 8U, X86::EIP }, 2801 { 12U, X86::ST0 }, 2802 { 13U, X86::ST1 }, 2803 { 14U, X86::ST2 }, 2804 { 15U, X86::ST3 }, 2805 { 16U, X86::ST4 }, 2806 { 17U, X86::ST5 }, 2807 { 18U, X86::ST6 }, 2808 { 19U, X86::ST7 }, 2809 { 21U, X86::XMM0 }, 2810 { 22U, X86::XMM1 }, 2811 { 23U, X86::XMM2 }, 2812 { 24U, X86::XMM3 }, 2813 { 25U, X86::XMM4 }, 2814 { 26U, X86::XMM5 }, 2815 { 27U, X86::XMM6 }, 2816 { 28U, X86::XMM7 }, 2817 { 29U, X86::MM0 }, 2818 { 30U, X86::MM1 }, 2819 { 31U, X86::MM2 }, 2820 { 32U, X86::MM3 }, 2821 { 33U, X86::MM4 }, 2822 { 34U, X86::MM5 }, 2823 { 35U, X86::MM6 }, 2824 { 36U, X86::MM7 }, 2825 { 93U, X86::K0 }, 2826 { 94U, X86::K1 }, 2827 { 95U, X86::K2 }, 2828 { 96U, X86::K3 }, 2829 { 97U, X86::K4 }, 2830 { 98U, X86::K5 }, 2831 { 99U, X86::K6 }, 2832 { 100U, X86::K7 }, 2833}; 2834extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L); 2835 2836extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = { 2837 { 0U, X86::EAX }, 2838 { 1U, X86::ECX }, 2839 { 2U, X86::EDX }, 2840 { 3U, X86::EBX }, 2841 { 4U, X86::ESP }, 2842 { 5U, X86::EBP }, 2843 { 6U, X86::ESI }, 2844 { 7U, X86::EDI }, 2845 { 8U, X86::EIP }, 2846 { 11U, X86::ST0 }, 2847 { 12U, X86::ST1 }, 2848 { 13U, X86::ST2 }, 2849 { 14U, X86::ST3 }, 2850 { 15U, X86::ST4 }, 2851 { 16U, X86::ST5 }, 2852 { 17U, X86::ST6 }, 2853 { 18U, X86::ST7 }, 2854 { 21U, X86::XMM0 }, 2855 { 22U, X86::XMM1 }, 2856 { 23U, X86::XMM2 }, 2857 { 24U, X86::XMM3 }, 2858 { 25U, X86::XMM4 }, 2859 { 26U, X86::XMM5 }, 2860 { 27U, X86::XMM6 }, 2861 { 28U, X86::XMM7 }, 2862 { 29U, X86::MM0 }, 2863 { 30U, X86::MM1 }, 2864 { 31U, X86::MM2 }, 2865 { 32U, X86::MM3 }, 2866 { 33U, X86::MM4 }, 2867 { 34U, X86::MM5 }, 2868 { 35U, X86::MM6 }, 2869 { 36U, X86::MM7 }, 2870 { 93U, X86::K0 }, 2871 { 94U, X86::K1 }, 2872 { 95U, X86::K2 }, 2873 { 96U, X86::K3 }, 2874 { 97U, X86::K4 }, 2875 { 98U, X86::K5 }, 2876 { 99U, X86::K6 }, 2877 { 100U, X86::K7 }, 2878}; 2879extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L); 2880 2881extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = { 2882 { 0U, X86::RAX }, 2883 { 1U, X86::RDX }, 2884 { 2U, X86::RCX }, 2885 { 3U, X86::RBX }, 2886 { 4U, X86::RSI }, 2887 { 5U, X86::RDI }, 2888 { 6U, X86::RBP }, 2889 { 7U, X86::RSP }, 2890 { 8U, X86::R8 }, 2891 { 9U, X86::R9 }, 2892 { 10U, X86::R10 }, 2893 { 11U, X86::R11 }, 2894 { 12U, X86::R12 }, 2895 { 13U, X86::R13 }, 2896 { 14U, X86::R14 }, 2897 { 15U, X86::R15 }, 2898 { 16U, X86::RIP }, 2899 { 17U, X86::XMM0 }, 2900 { 18U, X86::XMM1 }, 2901 { 19U, X86::XMM2 }, 2902 { 20U, X86::XMM3 }, 2903 { 21U, X86::XMM4 }, 2904 { 22U, X86::XMM5 }, 2905 { 23U, X86::XMM6 }, 2906 { 24U, X86::XMM7 }, 2907 { 25U, X86::XMM8 }, 2908 { 26U, X86::XMM9 }, 2909 { 27U, X86::XMM10 }, 2910 { 28U, X86::XMM11 }, 2911 { 29U, X86::XMM12 }, 2912 { 30U, X86::XMM13 }, 2913 { 31U, X86::XMM14 }, 2914 { 32U, X86::XMM15 }, 2915 { 33U, X86::ST0 }, 2916 { 34U, X86::ST1 }, 2917 { 35U, X86::ST2 }, 2918 { 36U, X86::ST3 }, 2919 { 37U, X86::ST4 }, 2920 { 38U, X86::ST5 }, 2921 { 39U, X86::ST6 }, 2922 { 40U, X86::ST7 }, 2923 { 41U, X86::MM0 }, 2924 { 42U, X86::MM1 }, 2925 { 43U, X86::MM2 }, 2926 { 44U, X86::MM3 }, 2927 { 45U, X86::MM4 }, 2928 { 46U, X86::MM5 }, 2929 { 47U, X86::MM6 }, 2930 { 48U, X86::MM7 }, 2931 { 67U, X86::XMM16 }, 2932 { 68U, X86::XMM17 }, 2933 { 69U, X86::XMM18 }, 2934 { 70U, X86::XMM19 }, 2935 { 71U, X86::XMM20 }, 2936 { 72U, X86::XMM21 }, 2937 { 73U, X86::XMM22 }, 2938 { 74U, X86::XMM23 }, 2939 { 75U, X86::XMM24 }, 2940 { 76U, X86::XMM25 }, 2941 { 77U, X86::XMM26 }, 2942 { 78U, X86::XMM27 }, 2943 { 79U, X86::XMM28 }, 2944 { 80U, X86::XMM29 }, 2945 { 81U, X86::XMM30 }, 2946 { 82U, X86::XMM31 }, 2947 { 118U, X86::K0 }, 2948 { 119U, X86::K1 }, 2949 { 120U, X86::K2 }, 2950 { 121U, X86::K3 }, 2951 { 122U, X86::K4 }, 2952 { 123U, X86::K5 }, 2953 { 124U, X86::K6 }, 2954 { 125U, X86::K7 }, 2955}; 2956extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L); 2957 2958extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = { 2959 { 0U, X86::EAX }, 2960 { 1U, X86::ECX }, 2961 { 2U, X86::EDX }, 2962 { 3U, X86::EBX }, 2963 { 4U, X86::EBP }, 2964 { 5U, X86::ESP }, 2965 { 6U, X86::ESI }, 2966 { 7U, X86::EDI }, 2967 { 8U, X86::EIP }, 2968 { 12U, X86::ST0 }, 2969 { 13U, X86::ST1 }, 2970 { 14U, X86::ST2 }, 2971 { 15U, X86::ST3 }, 2972 { 16U, X86::ST4 }, 2973 { 17U, X86::ST5 }, 2974 { 18U, X86::ST6 }, 2975 { 19U, X86::ST7 }, 2976 { 21U, X86::XMM0 }, 2977 { 22U, X86::XMM1 }, 2978 { 23U, X86::XMM2 }, 2979 { 24U, X86::XMM3 }, 2980 { 25U, X86::XMM4 }, 2981 { 26U, X86::XMM5 }, 2982 { 27U, X86::XMM6 }, 2983 { 28U, X86::XMM7 }, 2984 { 29U, X86::MM0 }, 2985 { 30U, X86::MM1 }, 2986 { 31U, X86::MM2 }, 2987 { 32U, X86::MM3 }, 2988 { 33U, X86::MM4 }, 2989 { 34U, X86::MM5 }, 2990 { 35U, X86::MM6 }, 2991 { 36U, X86::MM7 }, 2992 { 93U, X86::K0 }, 2993 { 94U, X86::K1 }, 2994 { 95U, X86::K2 }, 2995 { 96U, X86::K3 }, 2996 { 97U, X86::K4 }, 2997 { 98U, X86::K5 }, 2998 { 99U, X86::K6 }, 2999 { 100U, X86::K7 }, 3000}; 3001extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L); 3002 3003extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = { 3004 { 0U, X86::EAX }, 3005 { 1U, X86::ECX }, 3006 { 2U, X86::EDX }, 3007 { 3U, X86::EBX }, 3008 { 4U, X86::ESP }, 3009 { 5U, X86::EBP }, 3010 { 6U, X86::ESI }, 3011 { 7U, X86::EDI }, 3012 { 8U, X86::EIP }, 3013 { 11U, X86::ST0 }, 3014 { 12U, X86::ST1 }, 3015 { 13U, X86::ST2 }, 3016 { 14U, X86::ST3 }, 3017 { 15U, X86::ST4 }, 3018 { 16U, X86::ST5 }, 3019 { 17U, X86::ST6 }, 3020 { 18U, X86::ST7 }, 3021 { 21U, X86::XMM0 }, 3022 { 22U, X86::XMM1 }, 3023 { 23U, X86::XMM2 }, 3024 { 24U, X86::XMM3 }, 3025 { 25U, X86::XMM4 }, 3026 { 26U, X86::XMM5 }, 3027 { 27U, X86::XMM6 }, 3028 { 28U, X86::XMM7 }, 3029 { 29U, X86::MM0 }, 3030 { 30U, X86::MM1 }, 3031 { 31U, X86::MM2 }, 3032 { 32U, X86::MM3 }, 3033 { 33U, X86::MM4 }, 3034 { 34U, X86::MM5 }, 3035 { 35U, X86::MM6 }, 3036 { 36U, X86::MM7 }, 3037 { 93U, X86::K0 }, 3038 { 94U, X86::K1 }, 3039 { 95U, X86::K2 }, 3040 { 96U, X86::K3 }, 3041 { 97U, X86::K4 }, 3042 { 98U, X86::K5 }, 3043 { 99U, X86::K6 }, 3044 { 100U, X86::K7 }, 3045}; 3046extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L); 3047 3048extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = { 3049 { X86::EAX, -2U }, 3050 { X86::EBP, -2U }, 3051 { X86::EBX, -2U }, 3052 { X86::ECX, -2U }, 3053 { X86::EDI, -2U }, 3054 { X86::EDX, -2U }, 3055 { X86::EIP, -2U }, 3056 { X86::ESI, -2U }, 3057 { X86::ESP, -2U }, 3058 { X86::RAX, 0U }, 3059 { X86::RBP, 6U }, 3060 { X86::RBX, 3U }, 3061 { X86::RCX, 2U }, 3062 { X86::RDI, 5U }, 3063 { X86::RDX, 1U }, 3064 { X86::RIP, 16U }, 3065 { X86::RSI, 4U }, 3066 { X86::RSP, 7U }, 3067 { X86::K0, 118U }, 3068 { X86::K1, 119U }, 3069 { X86::K2, 120U }, 3070 { X86::K3, 121U }, 3071 { X86::K4, 122U }, 3072 { X86::K5, 123U }, 3073 { X86::K6, 124U }, 3074 { X86::K7, 125U }, 3075 { X86::MM0, 41U }, 3076 { X86::MM1, 42U }, 3077 { X86::MM2, 43U }, 3078 { X86::MM3, 44U }, 3079 { X86::MM4, 45U }, 3080 { X86::MM5, 46U }, 3081 { X86::MM6, 47U }, 3082 { X86::MM7, 48U }, 3083 { X86::R8, 8U }, 3084 { X86::R9, 9U }, 3085 { X86::R10, 10U }, 3086 { X86::R11, 11U }, 3087 { X86::R12, 12U }, 3088 { X86::R13, 13U }, 3089 { X86::R14, 14U }, 3090 { X86::R15, 15U }, 3091 { X86::ST0, 33U }, 3092 { X86::ST1, 34U }, 3093 { X86::ST2, 35U }, 3094 { X86::ST3, 36U }, 3095 { X86::ST4, 37U }, 3096 { X86::ST5, 38U }, 3097 { X86::ST6, 39U }, 3098 { X86::ST7, 40U }, 3099 { X86::XMM0, 17U }, 3100 { X86::XMM1, 18U }, 3101 { X86::XMM2, 19U }, 3102 { X86::XMM3, 20U }, 3103 { X86::XMM4, 21U }, 3104 { X86::XMM5, 22U }, 3105 { X86::XMM6, 23U }, 3106 { X86::XMM7, 24U }, 3107 { X86::XMM8, 25U }, 3108 { X86::XMM9, 26U }, 3109 { X86::XMM10, 27U }, 3110 { X86::XMM11, 28U }, 3111 { X86::XMM12, 29U }, 3112 { X86::XMM13, 30U }, 3113 { X86::XMM14, 31U }, 3114 { X86::XMM15, 32U }, 3115 { X86::XMM16, 67U }, 3116 { X86::XMM17, 68U }, 3117 { X86::XMM18, 69U }, 3118 { X86::XMM19, 70U }, 3119 { X86::XMM20, 71U }, 3120 { X86::XMM21, 72U }, 3121 { X86::XMM22, 73U }, 3122 { X86::XMM23, 74U }, 3123 { X86::XMM24, 75U }, 3124 { X86::XMM25, 76U }, 3125 { X86::XMM26, 77U }, 3126 { X86::XMM27, 78U }, 3127 { X86::XMM28, 79U }, 3128 { X86::XMM29, 80U }, 3129 { X86::XMM30, 81U }, 3130 { X86::XMM31, 82U }, 3131 { X86::YMM0, 17U }, 3132 { X86::YMM1, 18U }, 3133 { X86::YMM2, 19U }, 3134 { X86::YMM3, 20U }, 3135 { X86::YMM4, 21U }, 3136 { X86::YMM5, 22U }, 3137 { X86::YMM6, 23U }, 3138 { X86::YMM7, 24U }, 3139 { X86::YMM8, 25U }, 3140 { X86::YMM9, 26U }, 3141 { X86::YMM10, 27U }, 3142 { X86::YMM11, 28U }, 3143 { X86::YMM12, 29U }, 3144 { X86::YMM13, 30U }, 3145 { X86::YMM14, 31U }, 3146 { X86::YMM15, 32U }, 3147 { X86::YMM16, 67U }, 3148 { X86::YMM17, 68U }, 3149 { X86::YMM18, 69U }, 3150 { X86::YMM19, 70U }, 3151 { X86::YMM20, 71U }, 3152 { X86::YMM21, 72U }, 3153 { X86::YMM22, 73U }, 3154 { X86::YMM23, 74U }, 3155 { X86::YMM24, 75U }, 3156 { X86::YMM25, 76U }, 3157 { X86::YMM26, 77U }, 3158 { X86::YMM27, 78U }, 3159 { X86::YMM28, 79U }, 3160 { X86::YMM29, 80U }, 3161 { X86::YMM30, 81U }, 3162 { X86::YMM31, 82U }, 3163 { X86::ZMM0, 17U }, 3164 { X86::ZMM1, 18U }, 3165 { X86::ZMM2, 19U }, 3166 { X86::ZMM3, 20U }, 3167 { X86::ZMM4, 21U }, 3168 { X86::ZMM5, 22U }, 3169 { X86::ZMM6, 23U }, 3170 { X86::ZMM7, 24U }, 3171 { X86::ZMM8, 25U }, 3172 { X86::ZMM9, 26U }, 3173 { X86::ZMM10, 27U }, 3174 { X86::ZMM11, 28U }, 3175 { X86::ZMM12, 29U }, 3176 { X86::ZMM13, 30U }, 3177 { X86::ZMM14, 31U }, 3178 { X86::ZMM15, 32U }, 3179 { X86::ZMM16, 67U }, 3180 { X86::ZMM17, 68U }, 3181 { X86::ZMM18, 69U }, 3182 { X86::ZMM19, 70U }, 3183 { X86::ZMM20, 71U }, 3184 { X86::ZMM21, 72U }, 3185 { X86::ZMM22, 73U }, 3186 { X86::ZMM23, 74U }, 3187 { X86::ZMM24, 75U }, 3188 { X86::ZMM25, 76U }, 3189 { X86::ZMM26, 77U }, 3190 { X86::ZMM27, 78U }, 3191 { X86::ZMM28, 79U }, 3192 { X86::ZMM29, 80U }, 3193 { X86::ZMM30, 81U }, 3194 { X86::ZMM31, 82U }, 3195}; 3196extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf); 3197 3198extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = { 3199 { X86::EAX, 0U }, 3200 { X86::EBP, 4U }, 3201 { X86::EBX, 3U }, 3202 { X86::ECX, 1U }, 3203 { X86::EDI, 7U }, 3204 { X86::EDX, 2U }, 3205 { X86::EIP, 8U }, 3206 { X86::ESI, 6U }, 3207 { X86::ESP, 5U }, 3208 { X86::RAX, -2U }, 3209 { X86::RBP, -2U }, 3210 { X86::RBX, -2U }, 3211 { X86::RCX, -2U }, 3212 { X86::RDI, -2U }, 3213 { X86::RDX, -2U }, 3214 { X86::RIP, -2U }, 3215 { X86::RSI, -2U }, 3216 { X86::RSP, -2U }, 3217 { X86::K0, 93U }, 3218 { X86::K1, 94U }, 3219 { X86::K2, 95U }, 3220 { X86::K3, 96U }, 3221 { X86::K4, 97U }, 3222 { X86::K5, 98U }, 3223 { X86::K6, 99U }, 3224 { X86::K7, 100U }, 3225 { X86::MM0, 29U }, 3226 { X86::MM1, 30U }, 3227 { X86::MM2, 31U }, 3228 { X86::MM3, 32U }, 3229 { X86::MM4, 33U }, 3230 { X86::MM5, 34U }, 3231 { X86::MM6, 35U }, 3232 { X86::MM7, 36U }, 3233 { X86::R8, -2U }, 3234 { X86::R9, -2U }, 3235 { X86::R10, -2U }, 3236 { X86::R11, -2U }, 3237 { X86::R12, -2U }, 3238 { X86::R13, -2U }, 3239 { X86::R14, -2U }, 3240 { X86::R15, -2U }, 3241 { X86::ST0, 12U }, 3242 { X86::ST1, 13U }, 3243 { X86::ST2, 14U }, 3244 { X86::ST3, 15U }, 3245 { X86::ST4, 16U }, 3246 { X86::ST5, 17U }, 3247 { X86::ST6, 18U }, 3248 { X86::ST7, 19U }, 3249 { X86::XMM0, 21U }, 3250 { X86::XMM1, 22U }, 3251 { X86::XMM2, 23U }, 3252 { X86::XMM3, 24U }, 3253 { X86::XMM4, 25U }, 3254 { X86::XMM5, 26U }, 3255 { X86::XMM6, 27U }, 3256 { X86::XMM7, 28U }, 3257 { X86::XMM8, -2U }, 3258 { X86::XMM9, -2U }, 3259 { X86::XMM10, -2U }, 3260 { X86::XMM11, -2U }, 3261 { X86::XMM12, -2U }, 3262 { X86::XMM13, -2U }, 3263 { X86::XMM14, -2U }, 3264 { X86::XMM15, -2U }, 3265 { X86::XMM16, -2U }, 3266 { X86::XMM17, -2U }, 3267 { X86::XMM18, -2U }, 3268 { X86::XMM19, -2U }, 3269 { X86::XMM20, -2U }, 3270 { X86::XMM21, -2U }, 3271 { X86::XMM22, -2U }, 3272 { X86::XMM23, -2U }, 3273 { X86::XMM24, -2U }, 3274 { X86::XMM25, -2U }, 3275 { X86::XMM26, -2U }, 3276 { X86::XMM27, -2U }, 3277 { X86::XMM28, -2U }, 3278 { X86::XMM29, -2U }, 3279 { X86::XMM30, -2U }, 3280 { X86::XMM31, -2U }, 3281 { X86::YMM0, 21U }, 3282 { X86::YMM1, 22U }, 3283 { X86::YMM2, 23U }, 3284 { X86::YMM3, 24U }, 3285 { X86::YMM4, 25U }, 3286 { X86::YMM5, 26U }, 3287 { X86::YMM6, 27U }, 3288 { X86::YMM7, 28U }, 3289 { X86::YMM8, -2U }, 3290 { X86::YMM9, -2U }, 3291 { X86::YMM10, -2U }, 3292 { X86::YMM11, -2U }, 3293 { X86::YMM12, -2U }, 3294 { X86::YMM13, -2U }, 3295 { X86::YMM14, -2U }, 3296 { X86::YMM15, -2U }, 3297 { X86::YMM16, -2U }, 3298 { X86::YMM17, -2U }, 3299 { X86::YMM18, -2U }, 3300 { X86::YMM19, -2U }, 3301 { X86::YMM20, -2U }, 3302 { X86::YMM21, -2U }, 3303 { X86::YMM22, -2U }, 3304 { X86::YMM23, -2U }, 3305 { X86::YMM24, -2U }, 3306 { X86::YMM25, -2U }, 3307 { X86::YMM26, -2U }, 3308 { X86::YMM27, -2U }, 3309 { X86::YMM28, -2U }, 3310 { X86::YMM29, -2U }, 3311 { X86::YMM30, -2U }, 3312 { X86::YMM31, -2U }, 3313 { X86::ZMM0, 21U }, 3314 { X86::ZMM1, 22U }, 3315 { X86::ZMM2, 23U }, 3316 { X86::ZMM3, 24U }, 3317 { X86::ZMM4, 25U }, 3318 { X86::ZMM5, 26U }, 3319 { X86::ZMM6, 27U }, 3320 { X86::ZMM7, 28U }, 3321 { X86::ZMM8, -2U }, 3322 { X86::ZMM9, -2U }, 3323 { X86::ZMM10, -2U }, 3324 { X86::ZMM11, -2U }, 3325 { X86::ZMM12, -2U }, 3326 { X86::ZMM13, -2U }, 3327 { X86::ZMM14, -2U }, 3328 { X86::ZMM15, -2U }, 3329 { X86::ZMM16, -2U }, 3330 { X86::ZMM17, -2U }, 3331 { X86::ZMM18, -2U }, 3332 { X86::ZMM19, -2U }, 3333 { X86::ZMM20, -2U }, 3334 { X86::ZMM21, -2U }, 3335 { X86::ZMM22, -2U }, 3336 { X86::ZMM23, -2U }, 3337 { X86::ZMM24, -2U }, 3338 { X86::ZMM25, -2U }, 3339 { X86::ZMM26, -2U }, 3340 { X86::ZMM27, -2U }, 3341 { X86::ZMM28, -2U }, 3342 { X86::ZMM29, -2U }, 3343 { X86::ZMM30, -2U }, 3344 { X86::ZMM31, -2U }, 3345}; 3346extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf); 3347 3348extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = { 3349 { X86::EAX, 0U }, 3350 { X86::EBP, 5U }, 3351 { X86::EBX, 3U }, 3352 { X86::ECX, 1U }, 3353 { X86::EDI, 7U }, 3354 { X86::EDX, 2U }, 3355 { X86::EIP, 8U }, 3356 { X86::ESI, 6U }, 3357 { X86::ESP, 4U }, 3358 { X86::RAX, -2U }, 3359 { X86::RBP, -2U }, 3360 { X86::RBX, -2U }, 3361 { X86::RCX, -2U }, 3362 { X86::RDI, -2U }, 3363 { X86::RDX, -2U }, 3364 { X86::RIP, -2U }, 3365 { X86::RSI, -2U }, 3366 { X86::RSP, -2U }, 3367 { X86::K0, 93U }, 3368 { X86::K1, 94U }, 3369 { X86::K2, 95U }, 3370 { X86::K3, 96U }, 3371 { X86::K4, 97U }, 3372 { X86::K5, 98U }, 3373 { X86::K6, 99U }, 3374 { X86::K7, 100U }, 3375 { X86::MM0, 29U }, 3376 { X86::MM1, 30U }, 3377 { X86::MM2, 31U }, 3378 { X86::MM3, 32U }, 3379 { X86::MM4, 33U }, 3380 { X86::MM5, 34U }, 3381 { X86::MM6, 35U }, 3382 { X86::MM7, 36U }, 3383 { X86::R8, -2U }, 3384 { X86::R9, -2U }, 3385 { X86::R10, -2U }, 3386 { X86::R11, -2U }, 3387 { X86::R12, -2U }, 3388 { X86::R13, -2U }, 3389 { X86::R14, -2U }, 3390 { X86::R15, -2U }, 3391 { X86::ST0, 11U }, 3392 { X86::ST1, 12U }, 3393 { X86::ST2, 13U }, 3394 { X86::ST3, 14U }, 3395 { X86::ST4, 15U }, 3396 { X86::ST5, 16U }, 3397 { X86::ST6, 17U }, 3398 { X86::ST7, 18U }, 3399 { X86::XMM0, 21U }, 3400 { X86::XMM1, 22U }, 3401 { X86::XMM2, 23U }, 3402 { X86::XMM3, 24U }, 3403 { X86::XMM4, 25U }, 3404 { X86::XMM5, 26U }, 3405 { X86::XMM6, 27U }, 3406 { X86::XMM7, 28U }, 3407 { X86::XMM8, -2U }, 3408 { X86::XMM9, -2U }, 3409 { X86::XMM10, -2U }, 3410 { X86::XMM11, -2U }, 3411 { X86::XMM12, -2U }, 3412 { X86::XMM13, -2U }, 3413 { X86::XMM14, -2U }, 3414 { X86::XMM15, -2U }, 3415 { X86::XMM16, -2U }, 3416 { X86::XMM17, -2U }, 3417 { X86::XMM18, -2U }, 3418 { X86::XMM19, -2U }, 3419 { X86::XMM20, -2U }, 3420 { X86::XMM21, -2U }, 3421 { X86::XMM22, -2U }, 3422 { X86::XMM23, -2U }, 3423 { X86::XMM24, -2U }, 3424 { X86::XMM25, -2U }, 3425 { X86::XMM26, -2U }, 3426 { X86::XMM27, -2U }, 3427 { X86::XMM28, -2U }, 3428 { X86::XMM29, -2U }, 3429 { X86::XMM30, -2U }, 3430 { X86::XMM31, -2U }, 3431 { X86::YMM0, 21U }, 3432 { X86::YMM1, 22U }, 3433 { X86::YMM2, 23U }, 3434 { X86::YMM3, 24U }, 3435 { X86::YMM4, 25U }, 3436 { X86::YMM5, 26U }, 3437 { X86::YMM6, 27U }, 3438 { X86::YMM7, 28U }, 3439 { X86::YMM8, -2U }, 3440 { X86::YMM9, -2U }, 3441 { X86::YMM10, -2U }, 3442 { X86::YMM11, -2U }, 3443 { X86::YMM12, -2U }, 3444 { X86::YMM13, -2U }, 3445 { X86::YMM14, -2U }, 3446 { X86::YMM15, -2U }, 3447 { X86::YMM16, -2U }, 3448 { X86::YMM17, -2U }, 3449 { X86::YMM18, -2U }, 3450 { X86::YMM19, -2U }, 3451 { X86::YMM20, -2U }, 3452 { X86::YMM21, -2U }, 3453 { X86::YMM22, -2U }, 3454 { X86::YMM23, -2U }, 3455 { X86::YMM24, -2U }, 3456 { X86::YMM25, -2U }, 3457 { X86::YMM26, -2U }, 3458 { X86::YMM27, -2U }, 3459 { X86::YMM28, -2U }, 3460 { X86::YMM29, -2U }, 3461 { X86::YMM30, -2U }, 3462 { X86::YMM31, -2U }, 3463 { X86::ZMM0, 21U }, 3464 { X86::ZMM1, 22U }, 3465 { X86::ZMM2, 23U }, 3466 { X86::ZMM3, 24U }, 3467 { X86::ZMM4, 25U }, 3468 { X86::ZMM5, 26U }, 3469 { X86::ZMM6, 27U }, 3470 { X86::ZMM7, 28U }, 3471 { X86::ZMM8, -2U }, 3472 { X86::ZMM9, -2U }, 3473 { X86::ZMM10, -2U }, 3474 { X86::ZMM11, -2U }, 3475 { X86::ZMM12, -2U }, 3476 { X86::ZMM13, -2U }, 3477 { X86::ZMM14, -2U }, 3478 { X86::ZMM15, -2U }, 3479 { X86::ZMM16, -2U }, 3480 { X86::ZMM17, -2U }, 3481 { X86::ZMM18, -2U }, 3482 { X86::ZMM19, -2U }, 3483 { X86::ZMM20, -2U }, 3484 { X86::ZMM21, -2U }, 3485 { X86::ZMM22, -2U }, 3486 { X86::ZMM23, -2U }, 3487 { X86::ZMM24, -2U }, 3488 { X86::ZMM25, -2U }, 3489 { X86::ZMM26, -2U }, 3490 { X86::ZMM27, -2U }, 3491 { X86::ZMM28, -2U }, 3492 { X86::ZMM29, -2U }, 3493 { X86::ZMM30, -2U }, 3494 { X86::ZMM31, -2U }, 3495}; 3496extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf); 3497 3498extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = { 3499 { X86::EAX, -2U }, 3500 { X86::EBP, -2U }, 3501 { X86::EBX, -2U }, 3502 { X86::ECX, -2U }, 3503 { X86::EDI, -2U }, 3504 { X86::EDX, -2U }, 3505 { X86::EIP, -2U }, 3506 { X86::ESI, -2U }, 3507 { X86::ESP, -2U }, 3508 { X86::RAX, 0U }, 3509 { X86::RBP, 6U }, 3510 { X86::RBX, 3U }, 3511 { X86::RCX, 2U }, 3512 { X86::RDI, 5U }, 3513 { X86::RDX, 1U }, 3514 { X86::RIP, 16U }, 3515 { X86::RSI, 4U }, 3516 { X86::RSP, 7U }, 3517 { X86::K0, 118U }, 3518 { X86::K1, 119U }, 3519 { X86::K2, 120U }, 3520 { X86::K3, 121U }, 3521 { X86::K4, 122U }, 3522 { X86::K5, 123U }, 3523 { X86::K6, 124U }, 3524 { X86::K7, 125U }, 3525 { X86::MM0, 41U }, 3526 { X86::MM1, 42U }, 3527 { X86::MM2, 43U }, 3528 { X86::MM3, 44U }, 3529 { X86::MM4, 45U }, 3530 { X86::MM5, 46U }, 3531 { X86::MM6, 47U }, 3532 { X86::MM7, 48U }, 3533 { X86::R8, 8U }, 3534 { X86::R9, 9U }, 3535 { X86::R10, 10U }, 3536 { X86::R11, 11U }, 3537 { X86::R12, 12U }, 3538 { X86::R13, 13U }, 3539 { X86::R14, 14U }, 3540 { X86::R15, 15U }, 3541 { X86::ST0, 33U }, 3542 { X86::ST1, 34U }, 3543 { X86::ST2, 35U }, 3544 { X86::ST3, 36U }, 3545 { X86::ST4, 37U }, 3546 { X86::ST5, 38U }, 3547 { X86::ST6, 39U }, 3548 { X86::ST7, 40U }, 3549 { X86::XMM0, 17U }, 3550 { X86::XMM1, 18U }, 3551 { X86::XMM2, 19U }, 3552 { X86::XMM3, 20U }, 3553 { X86::XMM4, 21U }, 3554 { X86::XMM5, 22U }, 3555 { X86::XMM6, 23U }, 3556 { X86::XMM7, 24U }, 3557 { X86::XMM8, 25U }, 3558 { X86::XMM9, 26U }, 3559 { X86::XMM10, 27U }, 3560 { X86::XMM11, 28U }, 3561 { X86::XMM12, 29U }, 3562 { X86::XMM13, 30U }, 3563 { X86::XMM14, 31U }, 3564 { X86::XMM15, 32U }, 3565 { X86::XMM16, 67U }, 3566 { X86::XMM17, 68U }, 3567 { X86::XMM18, 69U }, 3568 { X86::XMM19, 70U }, 3569 { X86::XMM20, 71U }, 3570 { X86::XMM21, 72U }, 3571 { X86::XMM22, 73U }, 3572 { X86::XMM23, 74U }, 3573 { X86::XMM24, 75U }, 3574 { X86::XMM25, 76U }, 3575 { X86::XMM26, 77U }, 3576 { X86::XMM27, 78U }, 3577 { X86::XMM28, 79U }, 3578 { X86::XMM29, 80U }, 3579 { X86::XMM30, 81U }, 3580 { X86::XMM31, 82U }, 3581 { X86::YMM0, 17U }, 3582 { X86::YMM1, 18U }, 3583 { X86::YMM2, 19U }, 3584 { X86::YMM3, 20U }, 3585 { X86::YMM4, 21U }, 3586 { X86::YMM5, 22U }, 3587 { X86::YMM6, 23U }, 3588 { X86::YMM7, 24U }, 3589 { X86::YMM8, 25U }, 3590 { X86::YMM9, 26U }, 3591 { X86::YMM10, 27U }, 3592 { X86::YMM11, 28U }, 3593 { X86::YMM12, 29U }, 3594 { X86::YMM13, 30U }, 3595 { X86::YMM14, 31U }, 3596 { X86::YMM15, 32U }, 3597 { X86::YMM16, 67U }, 3598 { X86::YMM17, 68U }, 3599 { X86::YMM18, 69U }, 3600 { X86::YMM19, 70U }, 3601 { X86::YMM20, 71U }, 3602 { X86::YMM21, 72U }, 3603 { X86::YMM22, 73U }, 3604 { X86::YMM23, 74U }, 3605 { X86::YMM24, 75U }, 3606 { X86::YMM25, 76U }, 3607 { X86::YMM26, 77U }, 3608 { X86::YMM27, 78U }, 3609 { X86::YMM28, 79U }, 3610 { X86::YMM29, 80U }, 3611 { X86::YMM30, 81U }, 3612 { X86::YMM31, 82U }, 3613 { X86::ZMM0, 17U }, 3614 { X86::ZMM1, 18U }, 3615 { X86::ZMM2, 19U }, 3616 { X86::ZMM3, 20U }, 3617 { X86::ZMM4, 21U }, 3618 { X86::ZMM5, 22U }, 3619 { X86::ZMM6, 23U }, 3620 { X86::ZMM7, 24U }, 3621 { X86::ZMM8, 25U }, 3622 { X86::ZMM9, 26U }, 3623 { X86::ZMM10, 27U }, 3624 { X86::ZMM11, 28U }, 3625 { X86::ZMM12, 29U }, 3626 { X86::ZMM13, 30U }, 3627 { X86::ZMM14, 31U }, 3628 { X86::ZMM15, 32U }, 3629 { X86::ZMM16, 67U }, 3630 { X86::ZMM17, 68U }, 3631 { X86::ZMM18, 69U }, 3632 { X86::ZMM19, 70U }, 3633 { X86::ZMM20, 71U }, 3634 { X86::ZMM21, 72U }, 3635 { X86::ZMM22, 73U }, 3636 { X86::ZMM23, 74U }, 3637 { X86::ZMM24, 75U }, 3638 { X86::ZMM25, 76U }, 3639 { X86::ZMM26, 77U }, 3640 { X86::ZMM27, 78U }, 3641 { X86::ZMM28, 79U }, 3642 { X86::ZMM29, 80U }, 3643 { X86::ZMM30, 81U }, 3644 { X86::ZMM31, 82U }, 3645}; 3646extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf); 3647 3648extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = { 3649 { X86::EAX, 0U }, 3650 { X86::EBP, 4U }, 3651 { X86::EBX, 3U }, 3652 { X86::ECX, 1U }, 3653 { X86::EDI, 7U }, 3654 { X86::EDX, 2U }, 3655 { X86::EIP, 8U }, 3656 { X86::ESI, 6U }, 3657 { X86::ESP, 5U }, 3658 { X86::RAX, -2U }, 3659 { X86::RBP, -2U }, 3660 { X86::RBX, -2U }, 3661 { X86::RCX, -2U }, 3662 { X86::RDI, -2U }, 3663 { X86::RDX, -2U }, 3664 { X86::RIP, -2U }, 3665 { X86::RSI, -2U }, 3666 { X86::RSP, -2U }, 3667 { X86::K0, 93U }, 3668 { X86::K1, 94U }, 3669 { X86::K2, 95U }, 3670 { X86::K3, 96U }, 3671 { X86::K4, 97U }, 3672 { X86::K5, 98U }, 3673 { X86::K6, 99U }, 3674 { X86::K7, 100U }, 3675 { X86::MM0, 29U }, 3676 { X86::MM1, 30U }, 3677 { X86::MM2, 31U }, 3678 { X86::MM3, 32U }, 3679 { X86::MM4, 33U }, 3680 { X86::MM5, 34U }, 3681 { X86::MM6, 35U }, 3682 { X86::MM7, 36U }, 3683 { X86::R8, -2U }, 3684 { X86::R9, -2U }, 3685 { X86::R10, -2U }, 3686 { X86::R11, -2U }, 3687 { X86::R12, -2U }, 3688 { X86::R13, -2U }, 3689 { X86::R14, -2U }, 3690 { X86::R15, -2U }, 3691 { X86::ST0, 12U }, 3692 { X86::ST1, 13U }, 3693 { X86::ST2, 14U }, 3694 { X86::ST3, 15U }, 3695 { X86::ST4, 16U }, 3696 { X86::ST5, 17U }, 3697 { X86::ST6, 18U }, 3698 { X86::ST7, 19U }, 3699 { X86::XMM0, 21U }, 3700 { X86::XMM1, 22U }, 3701 { X86::XMM2, 23U }, 3702 { X86::XMM3, 24U }, 3703 { X86::XMM4, 25U }, 3704 { X86::XMM5, 26U }, 3705 { X86::XMM6, 27U }, 3706 { X86::XMM7, 28U }, 3707 { X86::XMM8, -2U }, 3708 { X86::XMM9, -2U }, 3709 { X86::XMM10, -2U }, 3710 { X86::XMM11, -2U }, 3711 { X86::XMM12, -2U }, 3712 { X86::XMM13, -2U }, 3713 { X86::XMM14, -2U }, 3714 { X86::XMM15, -2U }, 3715 { X86::XMM16, -2U }, 3716 { X86::XMM17, -2U }, 3717 { X86::XMM18, -2U }, 3718 { X86::XMM19, -2U }, 3719 { X86::XMM20, -2U }, 3720 { X86::XMM21, -2U }, 3721 { X86::XMM22, -2U }, 3722 { X86::XMM23, -2U }, 3723 { X86::XMM24, -2U }, 3724 { X86::XMM25, -2U }, 3725 { X86::XMM26, -2U }, 3726 { X86::XMM27, -2U }, 3727 { X86::XMM28, -2U }, 3728 { X86::XMM29, -2U }, 3729 { X86::XMM30, -2U }, 3730 { X86::XMM31, -2U }, 3731 { X86::YMM0, 21U }, 3732 { X86::YMM1, 22U }, 3733 { X86::YMM2, 23U }, 3734 { X86::YMM3, 24U }, 3735 { X86::YMM4, 25U }, 3736 { X86::YMM5, 26U }, 3737 { X86::YMM6, 27U }, 3738 { X86::YMM7, 28U }, 3739 { X86::YMM8, -2U }, 3740 { X86::YMM9, -2U }, 3741 { X86::YMM10, -2U }, 3742 { X86::YMM11, -2U }, 3743 { X86::YMM12, -2U }, 3744 { X86::YMM13, -2U }, 3745 { X86::YMM14, -2U }, 3746 { X86::YMM15, -2U }, 3747 { X86::YMM16, -2U }, 3748 { X86::YMM17, -2U }, 3749 { X86::YMM18, -2U }, 3750 { X86::YMM19, -2U }, 3751 { X86::YMM20, -2U }, 3752 { X86::YMM21, -2U }, 3753 { X86::YMM22, -2U }, 3754 { X86::YMM23, -2U }, 3755 { X86::YMM24, -2U }, 3756 { X86::YMM25, -2U }, 3757 { X86::YMM26, -2U }, 3758 { X86::YMM27, -2U }, 3759 { X86::YMM28, -2U }, 3760 { X86::YMM29, -2U }, 3761 { X86::YMM30, -2U }, 3762 { X86::YMM31, -2U }, 3763 { X86::ZMM0, 21U }, 3764 { X86::ZMM1, 22U }, 3765 { X86::ZMM2, 23U }, 3766 { X86::ZMM3, 24U }, 3767 { X86::ZMM4, 25U }, 3768 { X86::ZMM5, 26U }, 3769 { X86::ZMM6, 27U }, 3770 { X86::ZMM7, 28U }, 3771 { X86::ZMM8, -2U }, 3772 { X86::ZMM9, -2U }, 3773 { X86::ZMM10, -2U }, 3774 { X86::ZMM11, -2U }, 3775 { X86::ZMM12, -2U }, 3776 { X86::ZMM13, -2U }, 3777 { X86::ZMM14, -2U }, 3778 { X86::ZMM15, -2U }, 3779 { X86::ZMM16, -2U }, 3780 { X86::ZMM17, -2U }, 3781 { X86::ZMM18, -2U }, 3782 { X86::ZMM19, -2U }, 3783 { X86::ZMM20, -2U }, 3784 { X86::ZMM21, -2U }, 3785 { X86::ZMM22, -2U }, 3786 { X86::ZMM23, -2U }, 3787 { X86::ZMM24, -2U }, 3788 { X86::ZMM25, -2U }, 3789 { X86::ZMM26, -2U }, 3790 { X86::ZMM27, -2U }, 3791 { X86::ZMM28, -2U }, 3792 { X86::ZMM29, -2U }, 3793 { X86::ZMM30, -2U }, 3794 { X86::ZMM31, -2U }, 3795}; 3796extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf); 3797 3798extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = { 3799 { X86::EAX, 0U }, 3800 { X86::EBP, 5U }, 3801 { X86::EBX, 3U }, 3802 { X86::ECX, 1U }, 3803 { X86::EDI, 7U }, 3804 { X86::EDX, 2U }, 3805 { X86::EIP, 8U }, 3806 { X86::ESI, 6U }, 3807 { X86::ESP, 4U }, 3808 { X86::RAX, -2U }, 3809 { X86::RBP, -2U }, 3810 { X86::RBX, -2U }, 3811 { X86::RCX, -2U }, 3812 { X86::RDI, -2U }, 3813 { X86::RDX, -2U }, 3814 { X86::RIP, -2U }, 3815 { X86::RSI, -2U }, 3816 { X86::RSP, -2U }, 3817 { X86::K0, 93U }, 3818 { X86::K1, 94U }, 3819 { X86::K2, 95U }, 3820 { X86::K3, 96U }, 3821 { X86::K4, 97U }, 3822 { X86::K5, 98U }, 3823 { X86::K6, 99U }, 3824 { X86::K7, 100U }, 3825 { X86::MM0, 29U }, 3826 { X86::MM1, 30U }, 3827 { X86::MM2, 31U }, 3828 { X86::MM3, 32U }, 3829 { X86::MM4, 33U }, 3830 { X86::MM5, 34U }, 3831 { X86::MM6, 35U }, 3832 { X86::MM7, 36U }, 3833 { X86::R8, -2U }, 3834 { X86::R9, -2U }, 3835 { X86::R10, -2U }, 3836 { X86::R11, -2U }, 3837 { X86::R12, -2U }, 3838 { X86::R13, -2U }, 3839 { X86::R14, -2U }, 3840 { X86::R15, -2U }, 3841 { X86::ST0, 11U }, 3842 { X86::ST1, 12U }, 3843 { X86::ST2, 13U }, 3844 { X86::ST3, 14U }, 3845 { X86::ST4, 15U }, 3846 { X86::ST5, 16U }, 3847 { X86::ST6, 17U }, 3848 { X86::ST7, 18U }, 3849 { X86::XMM0, 21U }, 3850 { X86::XMM1, 22U }, 3851 { X86::XMM2, 23U }, 3852 { X86::XMM3, 24U }, 3853 { X86::XMM4, 25U }, 3854 { X86::XMM5, 26U }, 3855 { X86::XMM6, 27U }, 3856 { X86::XMM7, 28U }, 3857 { X86::XMM8, -2U }, 3858 { X86::XMM9, -2U }, 3859 { X86::XMM10, -2U }, 3860 { X86::XMM11, -2U }, 3861 { X86::XMM12, -2U }, 3862 { X86::XMM13, -2U }, 3863 { X86::XMM14, -2U }, 3864 { X86::XMM15, -2U }, 3865 { X86::XMM16, -2U }, 3866 { X86::XMM17, -2U }, 3867 { X86::XMM18, -2U }, 3868 { X86::XMM19, -2U }, 3869 { X86::XMM20, -2U }, 3870 { X86::XMM21, -2U }, 3871 { X86::XMM22, -2U }, 3872 { X86::XMM23, -2U }, 3873 { X86::XMM24, -2U }, 3874 { X86::XMM25, -2U }, 3875 { X86::XMM26, -2U }, 3876 { X86::XMM27, -2U }, 3877 { X86::XMM28, -2U }, 3878 { X86::XMM29, -2U }, 3879 { X86::XMM30, -2U }, 3880 { X86::XMM31, -2U }, 3881 { X86::YMM0, 21U }, 3882 { X86::YMM1, 22U }, 3883 { X86::YMM2, 23U }, 3884 { X86::YMM3, 24U }, 3885 { X86::YMM4, 25U }, 3886 { X86::YMM5, 26U }, 3887 { X86::YMM6, 27U }, 3888 { X86::YMM7, 28U }, 3889 { X86::YMM8, -2U }, 3890 { X86::YMM9, -2U }, 3891 { X86::YMM10, -2U }, 3892 { X86::YMM11, -2U }, 3893 { X86::YMM12, -2U }, 3894 { X86::YMM13, -2U }, 3895 { X86::YMM14, -2U }, 3896 { X86::YMM15, -2U }, 3897 { X86::YMM16, -2U }, 3898 { X86::YMM17, -2U }, 3899 { X86::YMM18, -2U }, 3900 { X86::YMM19, -2U }, 3901 { X86::YMM20, -2U }, 3902 { X86::YMM21, -2U }, 3903 { X86::YMM22, -2U }, 3904 { X86::YMM23, -2U }, 3905 { X86::YMM24, -2U }, 3906 { X86::YMM25, -2U }, 3907 { X86::YMM26, -2U }, 3908 { X86::YMM27, -2U }, 3909 { X86::YMM28, -2U }, 3910 { X86::YMM29, -2U }, 3911 { X86::YMM30, -2U }, 3912 { X86::YMM31, -2U }, 3913 { X86::ZMM0, 21U }, 3914 { X86::ZMM1, 22U }, 3915 { X86::ZMM2, 23U }, 3916 { X86::ZMM3, 24U }, 3917 { X86::ZMM4, 25U }, 3918 { X86::ZMM5, 26U }, 3919 { X86::ZMM6, 27U }, 3920 { X86::ZMM7, 28U }, 3921 { X86::ZMM8, -2U }, 3922 { X86::ZMM9, -2U }, 3923 { X86::ZMM10, -2U }, 3924 { X86::ZMM11, -2U }, 3925 { X86::ZMM12, -2U }, 3926 { X86::ZMM13, -2U }, 3927 { X86::ZMM14, -2U }, 3928 { X86::ZMM15, -2U }, 3929 { X86::ZMM16, -2U }, 3930 { X86::ZMM17, -2U }, 3931 { X86::ZMM18, -2U }, 3932 { X86::ZMM19, -2U }, 3933 { X86::ZMM20, -2U }, 3934 { X86::ZMM21, -2U }, 3935 { X86::ZMM22, -2U }, 3936 { X86::ZMM23, -2U }, 3937 { X86::ZMM24, -2U }, 3938 { X86::ZMM25, -2U }, 3939 { X86::ZMM26, -2U }, 3940 { X86::ZMM27, -2U }, 3941 { X86::ZMM28, -2U }, 3942 { X86::ZMM29, -2U }, 3943 { X86::ZMM30, -2U }, 3944 { X86::ZMM31, -2U }, 3945}; 3946extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf); 3947 3948extern const uint16_t X86RegEncodingTable[] = { 3949 0, 3950 4, 3951 0, 3952 0, 3953 7, 3954 3, 3955 5, 3956 65535, 3957 5, 3958 3, 3959 5, 3960 1, 3961 1, 3962 1, 3963 0, 3964 6, 3965 7, 3966 65535, 3967 7, 3968 2, 3969 3, 3970 2, 3971 0, 3972 5, 3973 3, 3974 1, 3975 7, 3976 2, 3977 0, 3978 0, 3979 4, 3980 0, 3981 6, 3982 4, 3983 0, 3984 0, 3985 4, 3986 5, 3987 65535, 3988 65535, 3989 65535, 3990 65535, 3991 65535, 3992 65535, 3993 65535, 3994 65535, 3995 65535, 3996 0, 3997 0, 3998 0, 3999 5, 4000 3, 4001 1, 4002 7, 4003 2, 4004 0, 4005 4, 4006 6, 4007 4, 4008 6, 4009 65535, 4010 6, 4011 4, 4012 65535, 4013 4, 4014 2, 4015 0, 4016 0, 4017 1, 4018 2, 4019 3, 4020 0, 4021 1, 4022 2, 4023 3, 4024 4, 4025 5, 4026 6, 4027 7, 4028 8, 4029 9, 4030 10, 4031 11, 4032 12, 4033 13, 4034 14, 4035 15, 4036 0, 4037 1, 4038 2, 4039 3, 4040 4, 4041 5, 4042 6, 4043 7, 4044 8, 4045 9, 4046 10, 4047 11, 4048 12, 4049 13, 4050 14, 4051 15, 4052 0, 4053 0, 4054 0, 4055 0, 4056 0, 4057 0, 4058 0, 4059 0, 4060 0, 4061 1, 4062 2, 4063 3, 4064 4, 4065 5, 4066 6, 4067 7, 4068 0, 4069 1, 4070 2, 4071 3, 4072 4, 4073 5, 4074 6, 4075 7, 4076 8, 4077 9, 4078 10, 4079 11, 4080 12, 4081 13, 4082 14, 4083 15, 4084 0, 4085 1, 4086 2, 4087 3, 4088 4, 4089 5, 4090 6, 4091 7, 4092 0, 4093 1, 4094 2, 4095 3, 4096 4, 4097 5, 4098 6, 4099 7, 4100 8, 4101 9, 4102 10, 4103 11, 4104 12, 4105 13, 4106 14, 4107 15, 4108 16, 4109 17, 4110 18, 4111 19, 4112 20, 4113 21, 4114 22, 4115 23, 4116 24, 4117 25, 4118 26, 4119 27, 4120 28, 4121 29, 4122 30, 4123 31, 4124 0, 4125 1, 4126 2, 4127 3, 4128 4, 4129 5, 4130 6, 4131 7, 4132 8, 4133 9, 4134 10, 4135 11, 4136 12, 4137 13, 4138 14, 4139 15, 4140 16, 4141 17, 4142 18, 4143 19, 4144 20, 4145 21, 4146 22, 4147 23, 4148 24, 4149 25, 4150 26, 4151 27, 4152 28, 4153 29, 4154 30, 4155 31, 4156 0, 4157 1, 4158 2, 4159 3, 4160 4, 4161 5, 4162 6, 4163 7, 4164 8, 4165 9, 4166 10, 4167 11, 4168 12, 4169 13, 4170 14, 4171 15, 4172 16, 4173 17, 4174 18, 4175 19, 4176 20, 4177 21, 4178 22, 4179 23, 4180 24, 4181 25, 4182 26, 4183 27, 4184 28, 4185 29, 4186 30, 4187 31, 4188 8, 4189 9, 4190 10, 4191 11, 4192 12, 4193 13, 4194 14, 4195 15, 4196 65535, 4197 65535, 4198 65535, 4199 65535, 4200 65535, 4201 65535, 4202 65535, 4203 65535, 4204 8, 4205 9, 4206 10, 4207 11, 4208 12, 4209 13, 4210 14, 4211 15, 4212 8, 4213 9, 4214 10, 4215 11, 4216 12, 4217 13, 4218 14, 4219 15, 4220 65535, 4221 65535, 4222 65535, 4223 65535, 4224 65535, 4225 65535, 4226 65535, 4227 65535, 4228 0, 4229 2, 4230 4, 4231 6, 4232}; 4233static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 4234 RI->InitMCRegisterInfo(X86RegDesc, 283, RA, PC, X86MCRegisterClasses, 118, X86RegUnitRoots, 164, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 11, 4235X86SubRegIdxRanges, X86RegEncodingTable); 4236 4237 switch (DwarfFlavour) { 4238 default: 4239 llvm_unreachable("Unknown DWARF flavour"); 4240 case 0: 4241 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false); 4242 break; 4243 case 1: 4244 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false); 4245 break; 4246 case 2: 4247 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false); 4248 break; 4249 } 4250 switch (EHFlavour) { 4251 default: 4252 llvm_unreachable("Unknown DWARF flavour"); 4253 case 0: 4254 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true); 4255 break; 4256 case 1: 4257 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true); 4258 break; 4259 case 2: 4260 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true); 4261 break; 4262 } 4263 switch (DwarfFlavour) { 4264 default: 4265 llvm_unreachable("Unknown DWARF flavour"); 4266 case 0: 4267 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false); 4268 break; 4269 case 1: 4270 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false); 4271 break; 4272 case 2: 4273 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false); 4274 break; 4275 } 4276 switch (EHFlavour) { 4277 default: 4278 llvm_unreachable("Unknown DWARF flavour"); 4279 case 0: 4280 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true); 4281 break; 4282 case 1: 4283 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true); 4284 break; 4285 case 2: 4286 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true); 4287 break; 4288 } 4289} 4290 4291} // end namespace llvm 4292 4293#endif // GET_REGINFO_MC_DESC 4294 4295/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 4296|* *| 4297|* Register Information Header Fragment *| 4298|* *| 4299|* Automatically generated file, do not edit! *| 4300|* *| 4301\*===----------------------------------------------------------------------===*/ 4302 4303 4304#ifdef GET_REGINFO_HEADER 4305#undef GET_REGINFO_HEADER 4306 4307#include "llvm/CodeGen/TargetRegisterInfo.h" 4308 4309namespace llvm { 4310 4311class X86FrameLowering; 4312 4313struct X86GenRegisterInfo : public TargetRegisterInfo { 4314 explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, 4315 unsigned PC = 0, unsigned HwMode = 0); 4316 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; 4317 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 4318 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 4319 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; 4320 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; 4321 unsigned getRegUnitWeight(unsigned RegUnit) const override; 4322 unsigned getNumRegPressureSets() const override; 4323 const char *getRegPressureSetName(unsigned Idx) const override; 4324 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; 4325 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; 4326 const int *getRegUnitPressureSets(unsigned RegUnit) const override; 4327 ArrayRef<const char *> getRegMaskNames() const override; 4328 ArrayRef<const uint32_t *> getRegMasks() const override; 4329 /// Devirtualized TargetFrameLowering. 4330 static const X86FrameLowering *getFrameLowering( 4331 const MachineFunction &MF); 4332}; 4333 4334namespace X86 { // Register classes 4335 extern const TargetRegisterClass GR8RegClass; 4336 extern const TargetRegisterClass GRH8RegClass; 4337 extern const TargetRegisterClass GR8_NOREXRegClass; 4338 extern const TargetRegisterClass GR8_ABCD_HRegClass; 4339 extern const TargetRegisterClass GR8_ABCD_LRegClass; 4340 extern const TargetRegisterClass GRH16RegClass; 4341 extern const TargetRegisterClass GR16RegClass; 4342 extern const TargetRegisterClass GR16_NOREXRegClass; 4343 extern const TargetRegisterClass VK1RegClass; 4344 extern const TargetRegisterClass VK16RegClass; 4345 extern const TargetRegisterClass VK2RegClass; 4346 extern const TargetRegisterClass VK4RegClass; 4347 extern const TargetRegisterClass VK8RegClass; 4348 extern const TargetRegisterClass VK16WMRegClass; 4349 extern const TargetRegisterClass VK1WMRegClass; 4350 extern const TargetRegisterClass VK2WMRegClass; 4351 extern const TargetRegisterClass VK4WMRegClass; 4352 extern const TargetRegisterClass VK8WMRegClass; 4353 extern const TargetRegisterClass SEGMENT_REGRegClass; 4354 extern const TargetRegisterClass GR16_ABCDRegClass; 4355 extern const TargetRegisterClass FPCCRRegClass; 4356 extern const TargetRegisterClass VK16PAIRRegClass; 4357 extern const TargetRegisterClass VK1PAIRRegClass; 4358 extern const TargetRegisterClass VK2PAIRRegClass; 4359 extern const TargetRegisterClass VK4PAIRRegClass; 4360 extern const TargetRegisterClass VK8PAIRRegClass; 4361 extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass; 4362 extern const TargetRegisterClass FR32XRegClass; 4363 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass; 4364 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass; 4365 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass; 4366 extern const TargetRegisterClass DEBUG_REGRegClass; 4367 extern const TargetRegisterClass FR32RegClass; 4368 extern const TargetRegisterClass GR32RegClass; 4369 extern const TargetRegisterClass GR32_NOSPRegClass; 4370 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass; 4371 extern const TargetRegisterClass GR32_NOREXRegClass; 4372 extern const TargetRegisterClass VK32RegClass; 4373 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass; 4374 extern const TargetRegisterClass RFP32RegClass; 4375 extern const TargetRegisterClass VK32WMRegClass; 4376 extern const TargetRegisterClass GR32_ABCDRegClass; 4377 extern const TargetRegisterClass GR32_TCRegClass; 4378 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass; 4379 extern const TargetRegisterClass GR32_ADRegClass; 4380 extern const TargetRegisterClass GR32_BPSPRegClass; 4381 extern const TargetRegisterClass GR32_BSIRegClass; 4382 extern const TargetRegisterClass GR32_CBRegClass; 4383 extern const TargetRegisterClass GR32_DCRegClass; 4384 extern const TargetRegisterClass GR32_DIBPRegClass; 4385 extern const TargetRegisterClass GR32_SIDIRegClass; 4386 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass; 4387 extern const TargetRegisterClass CCRRegClass; 4388 extern const TargetRegisterClass DFCCRRegClass; 4389 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass; 4390 extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass; 4391 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass; 4392 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass; 4393 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass; 4394 extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass; 4395 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass; 4396 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass; 4397 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass; 4398 extern const TargetRegisterClass RFP64RegClass; 4399 extern const TargetRegisterClass FR64XRegClass; 4400 extern const TargetRegisterClass GR64RegClass; 4401 extern const TargetRegisterClass CONTROL_REGRegClass; 4402 extern const TargetRegisterClass FR64RegClass; 4403 extern const TargetRegisterClass GR64_with_sub_8bitRegClass; 4404 extern const TargetRegisterClass GR64_NOSPRegClass; 4405 extern const TargetRegisterClass GR64_TCRegClass; 4406 extern const TargetRegisterClass GR64_NOREXRegClass; 4407 extern const TargetRegisterClass GR64_TCW64RegClass; 4408 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass; 4409 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass; 4410 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass; 4411 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass; 4412 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass; 4413 extern const TargetRegisterClass VK64RegClass; 4414 extern const TargetRegisterClass VR64RegClass; 4415 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass; 4416 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass; 4417 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass; 4418 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass; 4419 extern const TargetRegisterClass VK64WMRegClass; 4420 extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass; 4421 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass; 4422 extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass; 4423 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass; 4424 extern const TargetRegisterClass GR64_ABCDRegClass; 4425 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass; 4426 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass; 4427 extern const TargetRegisterClass GR64_ADRegClass; 4428 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass; 4429 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass; 4430 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass; 4431 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass; 4432 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass; 4433 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass; 4434 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass; 4435 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass; 4436 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass; 4437 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass; 4438 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass; 4439 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass; 4440 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass; 4441 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass; 4442 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass; 4443 extern const TargetRegisterClass RSTRegClass; 4444 extern const TargetRegisterClass RFP80RegClass; 4445 extern const TargetRegisterClass RFP80_7RegClass; 4446 extern const TargetRegisterClass VR128XRegClass; 4447 extern const TargetRegisterClass VR128RegClass; 4448 extern const TargetRegisterClass BNDRRegClass; 4449 extern const TargetRegisterClass VR256XRegClass; 4450 extern const TargetRegisterClass VR256RegClass; 4451 extern const TargetRegisterClass VR512RegClass; 4452 extern const TargetRegisterClass VR512_0_15RegClass; 4453} // end namespace X86 4454 4455} // end namespace llvm 4456 4457#endif // GET_REGINFO_HEADER 4458 4459/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 4460|* *| 4461|* Target Register and Register Classes Information *| 4462|* *| 4463|* Automatically generated file, do not edit! *| 4464|* *| 4465\*===----------------------------------------------------------------------===*/ 4466 4467 4468#ifdef GET_REGINFO_TARGET_DESC 4469#undef GET_REGINFO_TARGET_DESC 4470 4471namespace llvm { 4472 4473extern const MCRegisterClass X86MCRegisterClasses[]; 4474 4475static const MVT::SimpleValueType VTLists[] = { 4476 /* 0 */ MVT::i8, MVT::Other, 4477 /* 2 */ MVT::i16, MVT::Other, 4478 /* 4 */ MVT::i32, MVT::Other, 4479 /* 6 */ MVT::i64, MVT::Other, 4480 /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other, 4481 /* 12 */ MVT::f64, MVT::Other, 4482 /* 14 */ MVT::f80, MVT::Other, 4483 /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other, 4484 /* 24 */ MVT::v1i1, MVT::Other, 4485 /* 26 */ MVT::v2i1, MVT::Other, 4486 /* 28 */ MVT::v4i1, MVT::Other, 4487 /* 30 */ MVT::v8i1, MVT::Other, 4488 /* 32 */ MVT::v16i1, MVT::Other, 4489 /* 34 */ MVT::v32i1, MVT::Other, 4490 /* 36 */ MVT::v64i1, MVT::Other, 4491 /* 38 */ MVT::v2i64, MVT::Other, 4492 /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other, 4493 /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other, 4494 /* 54 */ MVT::x86mmx, MVT::Other, 4495 /* 56 */ MVT::Untyped, MVT::Other, 4496}; 4497 4498static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" }; 4499 4500 4501static const LaneBitmask SubRegIndexLaneMaskTable[] = { 4502 LaneBitmask::getAll(), 4503 LaneBitmask(0x00000001), // sub_8bit 4504 LaneBitmask(0x00000002), // sub_8bit_hi 4505 LaneBitmask(0x00000004), // sub_8bit_hi_phony 4506 LaneBitmask(0x00000007), // sub_16bit 4507 LaneBitmask(0x00000008), // sub_16bit_hi 4508 LaneBitmask(0x0000000F), // sub_32bit 4509 LaneBitmask(0x00000010), // sub_mask_0 4510 LaneBitmask(0x00000020), // sub_mask_1 4511 LaneBitmask(0x00000040), // sub_xmm 4512 LaneBitmask(0x00000040), // sub_ymm 4513 }; 4514 4515 4516 4517static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { 4518 // Mode = 0 (Default) 4519 { 8, 8, 8, VTLists+0 }, // GR8 4520 { 8, 8, 8, VTLists+0 }, // GRH8 4521 { 8, 8, 8, VTLists+0 }, // GR8_NOREX 4522 { 8, 8, 8, VTLists+0 }, // GR8_ABCD_H 4523 { 8, 8, 8, VTLists+0 }, // GR8_ABCD_L 4524 { 16, 16, 16, VTLists+2 }, // GRH16 4525 { 16, 16, 16, VTLists+2 }, // GR16 4526 { 16, 16, 16, VTLists+2 }, // GR16_NOREX 4527 { 16, 16, 16, VTLists+24 }, // VK1 4528 { 16, 16, 16, VTLists+32 }, // VK16 4529 { 16, 16, 16, VTLists+26 }, // VK2 4530 { 16, 16, 16, VTLists+28 }, // VK4 4531 { 16, 16, 16, VTLists+30 }, // VK8 4532 { 16, 16, 16, VTLists+32 }, // VK16WM 4533 { 16, 16, 16, VTLists+24 }, // VK1WM 4534 { 16, 16, 16, VTLists+26 }, // VK2WM 4535 { 16, 16, 16, VTLists+28 }, // VK4WM 4536 { 16, 16, 16, VTLists+30 }, // VK8WM 4537 { 16, 16, 16, VTLists+2 }, // SEGMENT_REG 4538 { 16, 16, 16, VTLists+2 }, // GR16_ABCD 4539 { 16, 16, 16, VTLists+2 }, // FPCCR 4540 { 32, 32, 16, VTLists+56 }, // VK16PAIR 4541 { 32, 32, 16, VTLists+56 }, // VK1PAIR 4542 { 32, 32, 16, VTLists+56 }, // VK2PAIR 4543 { 32, 32, 16, VTLists+56 }, // VK4PAIR 4544 { 32, 32, 16, VTLists+56 }, // VK8PAIR 4545 { 32, 32, 16, VTLists+56 }, // VK16PAIR_with_sub_mask_0_in_VK16WM 4546 { 32, 32, 32, VTLists+10 }, // FR32X 4547 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP 4548 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS 4549 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit 4550 { 32, 32, 32, VTLists+4 }, // DEBUG_REG 4551 { 32, 32, 32, VTLists+10 }, // FR32 4552 { 32, 32, 32, VTLists+4 }, // GR32 4553 { 32, 32, 32, VTLists+4 }, // GR32_NOSP 4554 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 4555 { 32, 32, 32, VTLists+4 }, // GR32_NOREX 4556 { 32, 32, 32, VTLists+34 }, // VK32 4557 { 32, 32, 32, VTLists+4 }, // GR32_NOREX_NOSP 4558 { 32, 32, 32, VTLists+10 }, // RFP32 4559 { 32, 32, 32, VTLists+34 }, // VK32WM 4560 { 32, 32, 32, VTLists+4 }, // GR32_ABCD 4561 { 32, 32, 32, VTLists+4 }, // GR32_TC 4562 { 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_TC 4563 { 32, 32, 32, VTLists+4 }, // GR32_AD 4564 { 32, 32, 32, VTLists+4 }, // GR32_BPSP 4565 { 32, 32, 32, VTLists+4 }, // GR32_BSI 4566 { 32, 32, 32, VTLists+4 }, // GR32_CB 4567 { 32, 32, 32, VTLists+4 }, // GR32_DC 4568 { 32, 32, 32, VTLists+4 }, // GR32_DIBP 4569 { 32, 32, 32, VTLists+4 }, // GR32_SIDI 4570 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit 4571 { 32, 32, 32, VTLists+4 }, // CCR 4572 { 32, 32, 32, VTLists+4 }, // DFCCR 4573 { 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_BSI 4574 { 32, 32, 32, VTLists+4 }, // GR32_AD_and_GR32_DC 4575 { 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_DIBP 4576 { 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_TC 4577 { 32, 32, 32, VTLists+4 }, // GR32_BSI_and_GR32_SIDI 4578 { 32, 32, 32, VTLists+4 }, // GR32_CB_and_GR32_DC 4579 { 32, 32, 32, VTLists+4 }, // GR32_DIBP_and_GR32_SIDI 4580 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 4581 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_with_sub_32bit 4582 { 64, 64, 32, VTLists+12 }, // RFP64 4583 { 64, 64, 64, VTLists+12 }, // FR64X 4584 { 64, 64, 64, VTLists+6 }, // GR64 4585 { 64, 64, 64, VTLists+6 }, // CONTROL_REG 4586 { 64, 64, 64, VTLists+12 }, // FR64 4587 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_8bit 4588 { 64, 64, 64, VTLists+6 }, // GR64_NOSP 4589 { 64, 64, 64, VTLists+6 }, // GR64_TC 4590 { 64, 64, 64, VTLists+6 }, // GR64_NOREX 4591 { 64, 64, 64, VTLists+6 }, // GR64_TCW64 4592 { 64, 64, 64, VTLists+6 }, // GR64_TC_with_sub_8bit 4593 { 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TC 4594 { 64, 64, 64, VTLists+6 }, // GR64_TCW64_with_sub_8bit 4595 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_TCW64 4596 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_16bit_in_GR16_NOREX 4597 { 64, 64, 64, VTLists+36 }, // VK64 4598 { 64, 64, 64, VTLists+54 }, // VR64 4599 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_NOSP 4600 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TC 4601 { 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TCW64 4602 { 64, 64, 64, VTLists+6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit 4603 { 64, 64, 64, VTLists+36 }, // VK64WM 4604 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 4605 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 4606 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_NOSP_and_GR64_TC 4607 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TCW64 4608 { 64, 64, 64, VTLists+6 }, // GR64_ABCD 4609 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_TC 4610 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 4611 { 64, 64, 64, VTLists+6 }, // GR64_AD 4612 { 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP 4613 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP 4614 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI 4615 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB 4616 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DC 4617 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP 4618 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_SIDI 4619 { 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS 4620 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 4621 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 4622 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 4623 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 4624 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 4625 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 4626 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 4627 { 80, 80, 32, VTLists+8 }, // RST 4628 { 80, 80, 32, VTLists+14 }, // RFP80 4629 { 80, 80, 32, VTLists+14 }, // RFP80_7 4630 { 128, 128, 128, VTLists+16 }, // VR128X 4631 { 128, 128, 128, VTLists+16 }, // VR128 4632 { 128, 128, 128, VTLists+38 }, // BNDR 4633 { 256, 256, 256, VTLists+40 }, // VR256X 4634 { 256, 256, 256, VTLists+40 }, // VR256 4635 { 512, 512, 512, VTLists+47 }, // VR512 4636 { 512, 512, 512, VTLists+47 }, // VR512_0_15 4637}; 4638 4639static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; 4640 4641static const uint32_t GR8SubClassMask[] = { 4642 0x0000001d, 0x00000000, 0x00000000, 0x00000000, 4643 0x400800c0, 0x3fc7fe5e, 0xdeed2e30, 0x00000fef, // sub_8bit 4644 0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi 4645}; 4646 4647static const uint32_t GRH8SubClassMask[] = { 4648 0x00000002, 0x00000000, 0x00000000, 0x00000000, 4649}; 4650 4651static const uint32_t GR8_NOREXSubClassMask[] = { 4652 0x0000001c, 0x00000000, 0x00000000, 0x00000000, 4653 0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit 4654 0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi 4655}; 4656 4657static const uint32_t GR8_ABCD_HSubClassMask[] = { 4658 0x00000008, 0x00000000, 0x00000000, 0x00000000, 4659 0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi 4660}; 4661 4662static const uint32_t GR8_ABCD_LSubClassMask[] = { 4663 0x00000010, 0x00000000, 0x00000000, 0x00000000, 4664 0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit 4665}; 4666 4667static const uint32_t GRH16SubClassMask[] = { 4668 0x00000020, 0x00000000, 0x00000000, 0x00000000, 4669}; 4670 4671static const uint32_t GR16SubClassMask[] = { 4672 0x000800c0, 0x00000000, 0x00000000, 0x00000000, 4673 0x40000000, 0x3fc7fe5e, 0xdeed2e30, 0x00000fef, // sub_16bit 4674}; 4675 4676static const uint32_t GR16_NOREXSubClassMask[] = { 4677 0x00080080, 0x00000000, 0x00000000, 0x00000000, 4678 0x00000000, 0x3fc7fe58, 0xdec12000, 0x00000fef, // sub_16bit 4679}; 4680 4681static const uint32_t VK1SubClassMask[] = { 4682 0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 4683 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4684 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4685}; 4686 4687static const uint32_t VK16SubClassMask[] = { 4688 0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 4689 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4690 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4691}; 4692 4693static const uint32_t VK2SubClassMask[] = { 4694 0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 4695 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4696 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4697}; 4698 4699static const uint32_t VK4SubClassMask[] = { 4700 0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 4701 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4702 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4703}; 4704 4705static const uint32_t VK8SubClassMask[] = { 4706 0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 4707 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4708 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4709}; 4710 4711static const uint32_t VK16WMSubClassMask[] = { 4712 0x0003e000, 0x00000100, 0x00100000, 0x00000000, 4713 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4714 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4715}; 4716 4717static const uint32_t VK1WMSubClassMask[] = { 4718 0x0003e000, 0x00000100, 0x00100000, 0x00000000, 4719 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4720 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4721}; 4722 4723static const uint32_t VK2WMSubClassMask[] = { 4724 0x0003e000, 0x00000100, 0x00100000, 0x00000000, 4725 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4726 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4727}; 4728 4729static const uint32_t VK4WMSubClassMask[] = { 4730 0x0003e000, 0x00000100, 0x00100000, 0x00000000, 4731 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4732 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4733}; 4734 4735static const uint32_t VK8WMSubClassMask[] = { 4736 0x0003e000, 0x00000100, 0x00100000, 0x00000000, 4737 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4738 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4739}; 4740 4741static const uint32_t SEGMENT_REGSubClassMask[] = { 4742 0x00040000, 0x00000000, 0x00000000, 0x00000000, 4743}; 4744 4745static const uint32_t GR16_ABCDSubClassMask[] = { 4746 0x00080000, 0x00000000, 0x00000000, 0x00000000, 4747 0x00000000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_16bit 4748}; 4749 4750static const uint32_t FPCCRSubClassMask[] = { 4751 0x00100000, 0x00000000, 0x00000000, 0x00000000, 4752}; 4753 4754static const uint32_t VK16PAIRSubClassMask[] = { 4755 0x07e00000, 0x00000000, 0x00000000, 0x00000000, 4756}; 4757 4758static const uint32_t VK1PAIRSubClassMask[] = { 4759 0x07e00000, 0x00000000, 0x00000000, 0x00000000, 4760}; 4761 4762static const uint32_t VK2PAIRSubClassMask[] = { 4763 0x07e00000, 0x00000000, 0x00000000, 0x00000000, 4764}; 4765 4766static const uint32_t VK4PAIRSubClassMask[] = { 4767 0x07e00000, 0x00000000, 0x00000000, 0x00000000, 4768}; 4769 4770static const uint32_t VK8PAIRSubClassMask[] = { 4771 0x07e00000, 0x00000000, 0x00000000, 0x00000000, 4772}; 4773 4774static const uint32_t VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask[] = { 4775 0x04000000, 0x00000000, 0x00000000, 0x00000000, 4776}; 4777 4778static const uint32_t FR32XSubClassMask[] = { 4779 0x08000000, 0x00000001, 0x00000009, 0x00018000, 4780 0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm 4781}; 4782 4783static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = { 4784 0x70000000, 0x7fcffe5e, 0x20000000, 0x00000090, 4785 0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit 4786}; 4787 4788static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = { 4789 0x20000000, 0x5fc7fe56, 0x00000000, 0x00000010, 4790 0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit 4791}; 4792 4793static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = { 4794 0x40000000, 0x3fc7fe5e, 0x00000000, 0x00000080, 4795 0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit 4796}; 4797 4798static const uint32_t DEBUG_REGSubClassMask[] = { 4799 0x80000000, 0x00000000, 0x00000000, 0x00000000, 4800}; 4801 4802static const uint32_t FR32SubClassMask[] = { 4803 0x00000000, 0x00000001, 0x00000008, 0x00010000, 4804 0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm 4805}; 4806 4807static const uint32_t GR32SubClassMask[] = { 4808 0x00000000, 0x1fc7fe56, 0x00000000, 0x00000000, 4809 0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit 4810}; 4811 4812static const uint32_t GR32_NOSPSubClassMask[] = { 4813 0x00000000, 0x1dc7da44, 0x00000000, 0x00000000, 4814 0x00000000, 0x20000000, 0x9aa50420, 0x00000eef, // sub_32bit 4815}; 4816 4817static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = { 4818 0x00000000, 0x3fc7fe58, 0x00000000, 0x00000080, 4819 0x00000000, 0x20000000, 0xdec12000, 0x00000fef, // sub_32bit 4820}; 4821 4822static const uint32_t GR32_NOREXSubClassMask[] = { 4823 0x00000000, 0x1fc7fe50, 0x00000000, 0x00000000, 4824 0x00000000, 0x20000000, 0xdec12000, 0x00000fef, // sub_32bit 4825}; 4826 4827static const uint32_t VK32SubClassMask[] = { 4828 0x00000000, 0x00000120, 0x00104000, 0x00000000, 4829 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4830 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4831}; 4832 4833static const uint32_t GR32_NOREX_NOSPSubClassMask[] = { 4834 0x00000000, 0x1dc7da40, 0x00000000, 0x00000000, 4835 0x00000000, 0x20000000, 0x9a810000, 0x00000eef, // sub_32bit 4836}; 4837 4838static const uint32_t RFP32SubClassMask[] = { 4839 0x00000000, 0x80000080, 0x00000000, 0x00002000, 4840}; 4841 4842static const uint32_t VK32WMSubClassMask[] = { 4843 0x00000000, 0x00000100, 0x00100000, 0x00000000, 4844 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 4845 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 4846}; 4847 4848static const uint32_t GR32_ABCDSubClassMask[] = { 4849 0x00000000, 0x08c19a00, 0x00000000, 0x00000000, 4850 0x00000000, 0x00000000, 0x1a000000, 0x00000463, // sub_32bit 4851}; 4852 4853static const uint32_t GR32_TCSubClassMask[] = { 4854 0x00000000, 0x0a811c00, 0x00000000, 0x00000000, 4855 0x00000000, 0x00000000, 0x1c000000, 0x00000542, // sub_32bit 4856}; 4857 4858static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = { 4859 0x00000000, 0x08811800, 0x00000000, 0x00000000, 4860 0x00000000, 0x00000000, 0x18000000, 0x00000442, // sub_32bit 4861}; 4862 4863static const uint32_t GR32_ADSubClassMask[] = { 4864 0x00000000, 0x00801000, 0x00000000, 0x00000000, 4865 0x00000000, 0x00000000, 0x10000000, 0x00000040, // sub_32bit 4866}; 4867 4868static const uint32_t GR32_BPSPSubClassMask[] = { 4869 0x00000000, 0x03002000, 0x00000000, 0x00000000, 4870 0x00000000, 0x20000000, 0x40000000, 0x00000180, // sub_32bit 4871}; 4872 4873static const uint32_t GR32_BSISubClassMask[] = { 4874 0x00000000, 0x04404000, 0x00000000, 0x00000000, 4875 0x00000000, 0x00000000, 0x80000000, 0x00000220, // sub_32bit 4876}; 4877 4878static const uint32_t GR32_CBSubClassMask[] = { 4879 0x00000000, 0x08408000, 0x00000000, 0x00000000, 4880 0x00000000, 0x00000000, 0x00000000, 0x00000421, // sub_32bit 4881}; 4882 4883static const uint32_t GR32_DCSubClassMask[] = { 4884 0x00000000, 0x08810000, 0x00000000, 0x00000000, 4885 0x00000000, 0x00000000, 0x00000000, 0x00000442, // sub_32bit 4886}; 4887 4888static const uint32_t GR32_DIBPSubClassMask[] = { 4889 0x00000000, 0x11020000, 0x00000000, 0x00000000, 4890 0x00000000, 0x20000000, 0x00000000, 0x00000884, // sub_32bit 4891}; 4892 4893static const uint32_t GR32_SIDISubClassMask[] = { 4894 0x00000000, 0x14040000, 0x00000000, 0x00000000, 4895 0x00000000, 0x00000000, 0x00000000, 0x00000a08, // sub_32bit 4896}; 4897 4898static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = { 4899 0x00000000, 0x60080000, 0x20000000, 0x00000090, 4900}; 4901 4902static const uint32_t CCRSubClassMask[] = { 4903 0x00000000, 0x00100000, 0x00000000, 0x00000000, 4904}; 4905 4906static const uint32_t DFCCRSubClassMask[] = { 4907 0x00000000, 0x00200000, 0x00000000, 0x00000000, 4908}; 4909 4910static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = { 4911 0x00000000, 0x00400000, 0x00000000, 0x00000000, 4912 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32bit 4913}; 4914 4915static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = { 4916 0x00000000, 0x00800000, 0x00000000, 0x00000000, 4917 0x00000000, 0x00000000, 0x00000000, 0x00000040, // sub_32bit 4918}; 4919 4920static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = { 4921 0x00000000, 0x01000000, 0x00000000, 0x00000000, 4922 0x00000000, 0x20000000, 0x00000000, 0x00000080, // sub_32bit 4923}; 4924 4925static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = { 4926 0x00000000, 0x02000000, 0x00000000, 0x00000000, 4927 0x00000000, 0x00000000, 0x00000000, 0x00000100, // sub_32bit 4928}; 4929 4930static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = { 4931 0x00000000, 0x04000000, 0x00000000, 0x00000000, 4932 0x00000000, 0x00000000, 0x00000000, 0x00000200, // sub_32bit 4933}; 4934 4935static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = { 4936 0x00000000, 0x08000000, 0x00000000, 0x00000000, 4937 0x00000000, 0x00000000, 0x00000000, 0x00000400, // sub_32bit 4938}; 4939 4940static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = { 4941 0x00000000, 0x10000000, 0x00000000, 0x00000000, 4942 0x00000000, 0x00000000, 0x00000000, 0x00000800, // sub_32bit 4943}; 4944 4945static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = { 4946 0x00000000, 0x20000000, 0x00000000, 0x00000080, 4947}; 4948 4949static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = { 4950 0x00000000, 0x40000000, 0x00000000, 0x00000010, 4951}; 4952 4953static const uint32_t RFP64SubClassMask[] = { 4954 0x00000000, 0x80000000, 0x00000000, 0x00002000, 4955}; 4956 4957static const uint32_t FR64XSubClassMask[] = { 4958 0x00000000, 0x00000000, 0x00000009, 0x00018000, 4959 0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm 4960}; 4961 4962static const uint32_t GR64SubClassMask[] = { 4963 0x00000000, 0x00000000, 0xffef3ff2, 0x00000fff, 4964}; 4965 4966static const uint32_t CONTROL_REGSubClassMask[] = { 4967 0x00000000, 0x00000000, 0x00000004, 0x00000000, 4968}; 4969 4970static const uint32_t FR64SubClassMask[] = { 4971 0x00000000, 0x00000000, 0x00000008, 0x00010000, 4972 0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm 4973}; 4974 4975static const uint32_t GR64_with_sub_8bitSubClassMask[] = { 4976 0x00000000, 0x00000000, 0xdeed2e30, 0x00000fef, 4977}; 4978 4979static const uint32_t GR64_NOSPSubClassMask[] = { 4980 0x00000000, 0x00000000, 0x9aa50420, 0x00000eef, 4981}; 4982 4983static const uint32_t GR64_TCSubClassMask[] = { 4984 0x00000000, 0x00000000, 0x1dea1640, 0x00000f5a, 4985}; 4986 4987static const uint32_t GR64_NOREXSubClassMask[] = { 4988 0x00000000, 0x00000000, 0xffc32080, 0x00000fff, 4989}; 4990 4991static const uint32_t GR64_TCW64SubClassMask[] = { 4992 0x00000000, 0x00000000, 0x1d2c1900, 0x00000552, 4993}; 4994 4995static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = { 4996 0x00000000, 0x00000000, 0x1ce80600, 0x00000f4a, 4997}; 4998 4999static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = { 5000 0x00000000, 0x00000000, 0x18a00400, 0x00000e4a, 5001}; 5002 5003static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = { 5004 0x00000000, 0x00000000, 0x1c2c0800, 0x00000542, 5005}; 5006 5007static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = { 5008 0x00000000, 0x00000000, 0x1d281000, 0x00000552, 5009}; 5010 5011static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = { 5012 0x00000000, 0x00000000, 0xdec12000, 0x00000fef, 5013}; 5014 5015static const uint32_t VK64SubClassMask[] = { 5016 0x00000000, 0x00000000, 0x00104000, 0x00000000, 5017 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 5018 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 5019}; 5020 5021static const uint32_t VR64SubClassMask[] = { 5022 0x00000000, 0x00000000, 0x00008000, 0x00000000, 5023}; 5024 5025static const uint32_t GR64_NOREX_NOSPSubClassMask[] = { 5026 0x00000000, 0x00000000, 0x9a810000, 0x00000eef, 5027}; 5028 5029static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = { 5030 0x00000000, 0x00000000, 0x1dc20000, 0x00000f5a, 5031}; 5032 5033static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = { 5034 0x00000000, 0x00000000, 0x18240000, 0x00000442, 5035}; 5036 5037static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = { 5038 0x00000000, 0x00000000, 0x1c280000, 0x00000542, 5039}; 5040 5041static const uint32_t VK64WMSubClassMask[] = { 5042 0x00000000, 0x00000000, 0x00100000, 0x00000000, 5043 0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0 5044 0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1 5045}; 5046 5047static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = { 5048 0x00000000, 0x00000000, 0x18200000, 0x00000442, 5049}; 5050 5051static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = { 5052 0x00000000, 0x00000000, 0x1cc00000, 0x00000f4a, 5053}; 5054 5055static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = { 5056 0x00000000, 0x00000000, 0x18800000, 0x00000e4a, 5057}; 5058 5059static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = { 5060 0x00000000, 0x00000000, 0x1d000000, 0x00000552, 5061}; 5062 5063static const uint32_t GR64_ABCDSubClassMask[] = { 5064 0x00000000, 0x00000000, 0x1a000000, 0x00000463, 5065}; 5066 5067static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = { 5068 0x00000000, 0x00000000, 0x1c000000, 0x00000542, 5069}; 5070 5071static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = { 5072 0x00000000, 0x00000000, 0x18000000, 0x00000442, 5073}; 5074 5075static const uint32_t GR64_ADSubClassMask[] = { 5076 0x00000000, 0x00000000, 0x10000000, 0x00000040, 5077}; 5078 5079static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = { 5080 0x00000000, 0x00000000, 0x20000000, 0x00000090, 5081}; 5082 5083static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = { 5084 0x00000000, 0x00000000, 0x40000000, 0x00000180, 5085}; 5086 5087static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = { 5088 0x00000000, 0x00000000, 0x80000000, 0x00000220, 5089}; 5090 5091static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = { 5092 0x00000000, 0x00000000, 0x00000000, 0x00000421, 5093}; 5094 5095static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = { 5096 0x00000000, 0x00000000, 0x00000000, 0x00000442, 5097}; 5098 5099static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = { 5100 0x00000000, 0x00000000, 0x00000000, 0x00000884, 5101}; 5102 5103static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = { 5104 0x00000000, 0x00000000, 0x00000000, 0x00000a08, 5105}; 5106 5107static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = { 5108 0x00000000, 0x00000000, 0x00000000, 0x00000010, 5109}; 5110 5111static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = { 5112 0x00000000, 0x00000000, 0x00000000, 0x00000020, 5113}; 5114 5115static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = { 5116 0x00000000, 0x00000000, 0x00000000, 0x00000040, 5117}; 5118 5119static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = { 5120 0x00000000, 0x00000000, 0x00000000, 0x00000080, 5121}; 5122 5123static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = { 5124 0x00000000, 0x00000000, 0x00000000, 0x00000100, 5125}; 5126 5127static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = { 5128 0x00000000, 0x00000000, 0x00000000, 0x00000200, 5129}; 5130 5131static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = { 5132 0x00000000, 0x00000000, 0x00000000, 0x00000400, 5133}; 5134 5135static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = { 5136 0x00000000, 0x00000000, 0x00000000, 0x00000800, 5137}; 5138 5139static const uint32_t RSTSubClassMask[] = { 5140 0x00000000, 0x00000000, 0x00000000, 0x00001000, 5141}; 5142 5143static const uint32_t RFP80SubClassMask[] = { 5144 0x00000000, 0x00000000, 0x00000000, 0x00002000, 5145}; 5146 5147static const uint32_t RFP80_7SubClassMask[] = { 5148 0x00000000, 0x00000000, 0x00000000, 0x00004000, 5149}; 5150 5151static const uint32_t VR128XSubClassMask[] = { 5152 0x00000000, 0x00000000, 0x00000000, 0x00018000, 5153 0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm 5154}; 5155 5156static const uint32_t VR128SubClassMask[] = { 5157 0x00000000, 0x00000000, 0x00000000, 0x00010000, 5158 0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm 5159}; 5160 5161static const uint32_t BNDRSubClassMask[] = { 5162 0x00000000, 0x00000000, 0x00000000, 0x00020000, 5163}; 5164 5165static const uint32_t VR256XSubClassMask[] = { 5166 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 5167 0x00000000, 0x00000000, 0x00000000, 0x00300000, // sub_ymm 5168}; 5169 5170static const uint32_t VR256SubClassMask[] = { 5171 0x00000000, 0x00000000, 0x00000000, 0x00080000, 5172 0x00000000, 0x00000000, 0x00000000, 0x00200000, // sub_ymm 5173}; 5174 5175static const uint32_t VR512SubClassMask[] = { 5176 0x00000000, 0x00000000, 0x00000000, 0x00300000, 5177}; 5178 5179static const uint32_t VR512_0_15SubClassMask[] = { 5180 0x00000000, 0x00000000, 0x00000000, 0x00200000, 5181}; 5182 5183static const uint16_t SuperRegIdxSeqs[] = { 5184 /* 0 */ 1, 0, 5185 /* 2 */ 1, 2, 0, 5186 /* 5 */ 4, 0, 5187 /* 7 */ 6, 0, 5188 /* 9 */ 7, 8, 0, 5189 /* 12 */ 9, 0, 5190 /* 14 */ 10, 0, 5191}; 5192 5193static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = { 5194 &X86::GR8RegClass, 5195 nullptr 5196}; 5197 5198static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = { 5199 &X86::GR8RegClass, 5200 &X86::GR8_NOREXRegClass, 5201 nullptr 5202}; 5203 5204static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = { 5205 &X86::GR8RegClass, 5206 &X86::GR8_NOREXRegClass, 5207 nullptr 5208}; 5209 5210static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = { 5211 &X86::GR16RegClass, 5212 nullptr 5213}; 5214 5215static const TargetRegisterClass *const VK1Superclasses[] = { 5216 &X86::VK16RegClass, 5217 &X86::VK2RegClass, 5218 &X86::VK4RegClass, 5219 &X86::VK8RegClass, 5220 nullptr 5221}; 5222 5223static const TargetRegisterClass *const VK16Superclasses[] = { 5224 &X86::VK1RegClass, 5225 &X86::VK2RegClass, 5226 &X86::VK4RegClass, 5227 &X86::VK8RegClass, 5228 nullptr 5229}; 5230 5231static const TargetRegisterClass *const VK2Superclasses[] = { 5232 &X86::VK1RegClass, 5233 &X86::VK16RegClass, 5234 &X86::VK4RegClass, 5235 &X86::VK8RegClass, 5236 nullptr 5237}; 5238 5239static const TargetRegisterClass *const VK4Superclasses[] = { 5240 &X86::VK1RegClass, 5241 &X86::VK16RegClass, 5242 &X86::VK2RegClass, 5243 &X86::VK8RegClass, 5244 nullptr 5245}; 5246 5247static const TargetRegisterClass *const VK8Superclasses[] = { 5248 &X86::VK1RegClass, 5249 &X86::VK16RegClass, 5250 &X86::VK2RegClass, 5251 &X86::VK4RegClass, 5252 nullptr 5253}; 5254 5255static const TargetRegisterClass *const VK16WMSuperclasses[] = { 5256 &X86::VK1RegClass, 5257 &X86::VK16RegClass, 5258 &X86::VK2RegClass, 5259 &X86::VK4RegClass, 5260 &X86::VK8RegClass, 5261 &X86::VK1WMRegClass, 5262 &X86::VK2WMRegClass, 5263 &X86::VK4WMRegClass, 5264 &X86::VK8WMRegClass, 5265 nullptr 5266}; 5267 5268static const TargetRegisterClass *const VK1WMSuperclasses[] = { 5269 &X86::VK1RegClass, 5270 &X86::VK16RegClass, 5271 &X86::VK2RegClass, 5272 &X86::VK4RegClass, 5273 &X86::VK8RegClass, 5274 &X86::VK16WMRegClass, 5275 &X86::VK2WMRegClass, 5276 &X86::VK4WMRegClass, 5277 &X86::VK8WMRegClass, 5278 nullptr 5279}; 5280 5281static const TargetRegisterClass *const VK2WMSuperclasses[] = { 5282 &X86::VK1RegClass, 5283 &X86::VK16RegClass, 5284 &X86::VK2RegClass, 5285 &X86::VK4RegClass, 5286 &X86::VK8RegClass, 5287 &X86::VK16WMRegClass, 5288 &X86::VK1WMRegClass, 5289 &X86::VK4WMRegClass, 5290 &X86::VK8WMRegClass, 5291 nullptr 5292}; 5293 5294static const TargetRegisterClass *const VK4WMSuperclasses[] = { 5295 &X86::VK1RegClass, 5296 &X86::VK16RegClass, 5297 &X86::VK2RegClass, 5298 &X86::VK4RegClass, 5299 &X86::VK8RegClass, 5300 &X86::VK16WMRegClass, 5301 &X86::VK1WMRegClass, 5302 &X86::VK2WMRegClass, 5303 &X86::VK8WMRegClass, 5304 nullptr 5305}; 5306 5307static const TargetRegisterClass *const VK8WMSuperclasses[] = { 5308 &X86::VK1RegClass, 5309 &X86::VK16RegClass, 5310 &X86::VK2RegClass, 5311 &X86::VK4RegClass, 5312 &X86::VK8RegClass, 5313 &X86::VK16WMRegClass, 5314 &X86::VK1WMRegClass, 5315 &X86::VK2WMRegClass, 5316 &X86::VK4WMRegClass, 5317 nullptr 5318}; 5319 5320static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = { 5321 &X86::GR16RegClass, 5322 &X86::GR16_NOREXRegClass, 5323 nullptr 5324}; 5325 5326static const TargetRegisterClass *const VK16PAIRSuperclasses[] = { 5327 &X86::VK1PAIRRegClass, 5328 &X86::VK2PAIRRegClass, 5329 &X86::VK4PAIRRegClass, 5330 &X86::VK8PAIRRegClass, 5331 nullptr 5332}; 5333 5334static const TargetRegisterClass *const VK1PAIRSuperclasses[] = { 5335 &X86::VK16PAIRRegClass, 5336 &X86::VK2PAIRRegClass, 5337 &X86::VK4PAIRRegClass, 5338 &X86::VK8PAIRRegClass, 5339 nullptr 5340}; 5341 5342static const TargetRegisterClass *const VK2PAIRSuperclasses[] = { 5343 &X86::VK16PAIRRegClass, 5344 &X86::VK1PAIRRegClass, 5345 &X86::VK4PAIRRegClass, 5346 &X86::VK8PAIRRegClass, 5347 nullptr 5348}; 5349 5350static const TargetRegisterClass *const VK4PAIRSuperclasses[] = { 5351 &X86::VK16PAIRRegClass, 5352 &X86::VK1PAIRRegClass, 5353 &X86::VK2PAIRRegClass, 5354 &X86::VK8PAIRRegClass, 5355 nullptr 5356}; 5357 5358static const TargetRegisterClass *const VK8PAIRSuperclasses[] = { 5359 &X86::VK16PAIRRegClass, 5360 &X86::VK1PAIRRegClass, 5361 &X86::VK2PAIRRegClass, 5362 &X86::VK4PAIRRegClass, 5363 nullptr 5364}; 5365 5366static const TargetRegisterClass *const VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses[] = { 5367 &X86::VK16PAIRRegClass, 5368 &X86::VK1PAIRRegClass, 5369 &X86::VK2PAIRRegClass, 5370 &X86::VK4PAIRRegClass, 5371 &X86::VK8PAIRRegClass, 5372 nullptr 5373}; 5374 5375static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = { 5376 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5377 nullptr 5378}; 5379 5380static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = { 5381 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5382 nullptr 5383}; 5384 5385static const TargetRegisterClass *const FR32Superclasses[] = { 5386 &X86::FR32XRegClass, 5387 nullptr 5388}; 5389 5390static const TargetRegisterClass *const GR32Superclasses[] = { 5391 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5392 &X86::LOW32_ADDR_ACCESSRegClass, 5393 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5394 nullptr 5395}; 5396 5397static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = { 5398 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5399 &X86::LOW32_ADDR_ACCESSRegClass, 5400 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5401 &X86::GR32RegClass, 5402 nullptr 5403}; 5404 5405static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = { 5406 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5407 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5408 nullptr 5409}; 5410 5411static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = { 5412 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5413 &X86::LOW32_ADDR_ACCESSRegClass, 5414 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5415 &X86::GR32RegClass, 5416 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5417 nullptr 5418}; 5419 5420static const TargetRegisterClass *const VK32Superclasses[] = { 5421 &X86::VK1RegClass, 5422 &X86::VK16RegClass, 5423 &X86::VK2RegClass, 5424 &X86::VK4RegClass, 5425 &X86::VK8RegClass, 5426 nullptr 5427}; 5428 5429static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = { 5430 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5431 &X86::LOW32_ADDR_ACCESSRegClass, 5432 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5433 &X86::GR32RegClass, 5434 &X86::GR32_NOSPRegClass, 5435 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5436 &X86::GR32_NOREXRegClass, 5437 nullptr 5438}; 5439 5440static const TargetRegisterClass *const VK32WMSuperclasses[] = { 5441 &X86::VK1RegClass, 5442 &X86::VK16RegClass, 5443 &X86::VK2RegClass, 5444 &X86::VK4RegClass, 5445 &X86::VK8RegClass, 5446 &X86::VK16WMRegClass, 5447 &X86::VK1WMRegClass, 5448 &X86::VK2WMRegClass, 5449 &X86::VK4WMRegClass, 5450 &X86::VK8WMRegClass, 5451 &X86::VK32RegClass, 5452 nullptr 5453}; 5454 5455static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = { 5456 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5457 &X86::LOW32_ADDR_ACCESSRegClass, 5458 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5459 &X86::GR32RegClass, 5460 &X86::GR32_NOSPRegClass, 5461 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5462 &X86::GR32_NOREXRegClass, 5463 &X86::GR32_NOREX_NOSPRegClass, 5464 nullptr 5465}; 5466 5467static const TargetRegisterClass *const GR32_TCSuperclasses[] = { 5468 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5469 &X86::LOW32_ADDR_ACCESSRegClass, 5470 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5471 &X86::GR32RegClass, 5472 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5473 &X86::GR32_NOREXRegClass, 5474 nullptr 5475}; 5476 5477static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = { 5478 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5479 &X86::LOW32_ADDR_ACCESSRegClass, 5480 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5481 &X86::GR32RegClass, 5482 &X86::GR32_NOSPRegClass, 5483 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5484 &X86::GR32_NOREXRegClass, 5485 &X86::GR32_NOREX_NOSPRegClass, 5486 &X86::GR32_ABCDRegClass, 5487 &X86::GR32_TCRegClass, 5488 nullptr 5489}; 5490 5491static const TargetRegisterClass *const GR32_ADSuperclasses[] = { 5492 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5493 &X86::LOW32_ADDR_ACCESSRegClass, 5494 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5495 &X86::GR32RegClass, 5496 &X86::GR32_NOSPRegClass, 5497 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5498 &X86::GR32_NOREXRegClass, 5499 &X86::GR32_NOREX_NOSPRegClass, 5500 &X86::GR32_ABCDRegClass, 5501 &X86::GR32_TCRegClass, 5502 &X86::GR32_ABCD_and_GR32_TCRegClass, 5503 nullptr 5504}; 5505 5506static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = { 5507 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5508 &X86::LOW32_ADDR_ACCESSRegClass, 5509 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5510 &X86::GR32RegClass, 5511 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5512 &X86::GR32_NOREXRegClass, 5513 nullptr 5514}; 5515 5516static const TargetRegisterClass *const GR32_BSISuperclasses[] = { 5517 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5518 &X86::LOW32_ADDR_ACCESSRegClass, 5519 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5520 &X86::GR32RegClass, 5521 &X86::GR32_NOSPRegClass, 5522 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5523 &X86::GR32_NOREXRegClass, 5524 &X86::GR32_NOREX_NOSPRegClass, 5525 nullptr 5526}; 5527 5528static const TargetRegisterClass *const GR32_CBSuperclasses[] = { 5529 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5530 &X86::LOW32_ADDR_ACCESSRegClass, 5531 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5532 &X86::GR32RegClass, 5533 &X86::GR32_NOSPRegClass, 5534 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5535 &X86::GR32_NOREXRegClass, 5536 &X86::GR32_NOREX_NOSPRegClass, 5537 &X86::GR32_ABCDRegClass, 5538 nullptr 5539}; 5540 5541static const TargetRegisterClass *const GR32_DCSuperclasses[] = { 5542 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5543 &X86::LOW32_ADDR_ACCESSRegClass, 5544 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5545 &X86::GR32RegClass, 5546 &X86::GR32_NOSPRegClass, 5547 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5548 &X86::GR32_NOREXRegClass, 5549 &X86::GR32_NOREX_NOSPRegClass, 5550 &X86::GR32_ABCDRegClass, 5551 &X86::GR32_TCRegClass, 5552 &X86::GR32_ABCD_and_GR32_TCRegClass, 5553 nullptr 5554}; 5555 5556static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = { 5557 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5558 &X86::LOW32_ADDR_ACCESSRegClass, 5559 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5560 &X86::GR32RegClass, 5561 &X86::GR32_NOSPRegClass, 5562 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5563 &X86::GR32_NOREXRegClass, 5564 &X86::GR32_NOREX_NOSPRegClass, 5565 nullptr 5566}; 5567 5568static const TargetRegisterClass *const GR32_SIDISuperclasses[] = { 5569 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5570 &X86::LOW32_ADDR_ACCESSRegClass, 5571 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5572 &X86::GR32RegClass, 5573 &X86::GR32_NOSPRegClass, 5574 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5575 &X86::GR32_NOREXRegClass, 5576 &X86::GR32_NOREX_NOSPRegClass, 5577 nullptr 5578}; 5579 5580static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = { 5581 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5582 nullptr 5583}; 5584 5585static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = { 5586 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5587 &X86::LOW32_ADDR_ACCESSRegClass, 5588 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5589 &X86::GR32RegClass, 5590 &X86::GR32_NOSPRegClass, 5591 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5592 &X86::GR32_NOREXRegClass, 5593 &X86::GR32_NOREX_NOSPRegClass, 5594 &X86::GR32_ABCDRegClass, 5595 &X86::GR32_BSIRegClass, 5596 &X86::GR32_CBRegClass, 5597 nullptr 5598}; 5599 5600static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = { 5601 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5602 &X86::LOW32_ADDR_ACCESSRegClass, 5603 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5604 &X86::GR32RegClass, 5605 &X86::GR32_NOSPRegClass, 5606 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5607 &X86::GR32_NOREXRegClass, 5608 &X86::GR32_NOREX_NOSPRegClass, 5609 &X86::GR32_ABCDRegClass, 5610 &X86::GR32_TCRegClass, 5611 &X86::GR32_ABCD_and_GR32_TCRegClass, 5612 &X86::GR32_ADRegClass, 5613 &X86::GR32_DCRegClass, 5614 nullptr 5615}; 5616 5617static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = { 5618 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5619 &X86::LOW32_ADDR_ACCESSRegClass, 5620 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5621 &X86::GR32RegClass, 5622 &X86::GR32_NOSPRegClass, 5623 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5624 &X86::GR32_NOREXRegClass, 5625 &X86::GR32_NOREX_NOSPRegClass, 5626 &X86::GR32_BPSPRegClass, 5627 &X86::GR32_DIBPRegClass, 5628 nullptr 5629}; 5630 5631static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = { 5632 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5633 &X86::LOW32_ADDR_ACCESSRegClass, 5634 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5635 &X86::GR32RegClass, 5636 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5637 &X86::GR32_NOREXRegClass, 5638 &X86::GR32_TCRegClass, 5639 &X86::GR32_BPSPRegClass, 5640 nullptr 5641}; 5642 5643static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = { 5644 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5645 &X86::LOW32_ADDR_ACCESSRegClass, 5646 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5647 &X86::GR32RegClass, 5648 &X86::GR32_NOSPRegClass, 5649 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5650 &X86::GR32_NOREXRegClass, 5651 &X86::GR32_NOREX_NOSPRegClass, 5652 &X86::GR32_BSIRegClass, 5653 &X86::GR32_SIDIRegClass, 5654 nullptr 5655}; 5656 5657static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = { 5658 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5659 &X86::LOW32_ADDR_ACCESSRegClass, 5660 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5661 &X86::GR32RegClass, 5662 &X86::GR32_NOSPRegClass, 5663 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5664 &X86::GR32_NOREXRegClass, 5665 &X86::GR32_NOREX_NOSPRegClass, 5666 &X86::GR32_ABCDRegClass, 5667 &X86::GR32_TCRegClass, 5668 &X86::GR32_ABCD_and_GR32_TCRegClass, 5669 &X86::GR32_CBRegClass, 5670 &X86::GR32_DCRegClass, 5671 nullptr 5672}; 5673 5674static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = { 5675 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5676 &X86::LOW32_ADDR_ACCESSRegClass, 5677 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5678 &X86::GR32RegClass, 5679 &X86::GR32_NOSPRegClass, 5680 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5681 &X86::GR32_NOREXRegClass, 5682 &X86::GR32_NOREX_NOSPRegClass, 5683 &X86::GR32_DIBPRegClass, 5684 &X86::GR32_SIDIRegClass, 5685 nullptr 5686}; 5687 5688static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = { 5689 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5690 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 5691 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 5692 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 5693 nullptr 5694}; 5695 5696static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = { 5697 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5698 &X86::LOW32_ADDR_ACCESSRegClass, 5699 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 5700 nullptr 5701}; 5702 5703static const TargetRegisterClass *const RFP64Superclasses[] = { 5704 &X86::RFP32RegClass, 5705 nullptr 5706}; 5707 5708static const TargetRegisterClass *const FR64XSuperclasses[] = { 5709 &X86::FR32XRegClass, 5710 nullptr 5711}; 5712 5713static const TargetRegisterClass *const FR64Superclasses[] = { 5714 &X86::FR32XRegClass, 5715 &X86::FR32RegClass, 5716 &X86::FR64XRegClass, 5717 nullptr 5718}; 5719 5720static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = { 5721 &X86::GR64RegClass, 5722 nullptr 5723}; 5724 5725static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = { 5726 &X86::GR64RegClass, 5727 &X86::GR64_with_sub_8bitRegClass, 5728 nullptr 5729}; 5730 5731static const TargetRegisterClass *const GR64_TCSuperclasses[] = { 5732 &X86::GR64RegClass, 5733 nullptr 5734}; 5735 5736static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = { 5737 &X86::GR64RegClass, 5738 nullptr 5739}; 5740 5741static const TargetRegisterClass *const GR64_TCW64Superclasses[] = { 5742 &X86::GR64RegClass, 5743 nullptr 5744}; 5745 5746static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = { 5747 &X86::GR64RegClass, 5748 &X86::GR64_with_sub_8bitRegClass, 5749 &X86::GR64_TCRegClass, 5750 nullptr 5751}; 5752 5753static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = { 5754 &X86::GR64RegClass, 5755 &X86::GR64_with_sub_8bitRegClass, 5756 &X86::GR64_NOSPRegClass, 5757 &X86::GR64_TCRegClass, 5758 &X86::GR64_TC_with_sub_8bitRegClass, 5759 nullptr 5760}; 5761 5762static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = { 5763 &X86::GR64RegClass, 5764 &X86::GR64_with_sub_8bitRegClass, 5765 &X86::GR64_TCW64RegClass, 5766 nullptr 5767}; 5768 5769static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = { 5770 &X86::GR64RegClass, 5771 &X86::GR64_TCRegClass, 5772 &X86::GR64_TCW64RegClass, 5773 nullptr 5774}; 5775 5776static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = { 5777 &X86::GR64RegClass, 5778 &X86::GR64_with_sub_8bitRegClass, 5779 &X86::GR64_NOREXRegClass, 5780 nullptr 5781}; 5782 5783static const TargetRegisterClass *const VK64Superclasses[] = { 5784 &X86::VK1RegClass, 5785 &X86::VK16RegClass, 5786 &X86::VK2RegClass, 5787 &X86::VK4RegClass, 5788 &X86::VK8RegClass, 5789 &X86::VK32RegClass, 5790 nullptr 5791}; 5792 5793static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = { 5794 &X86::GR64RegClass, 5795 &X86::GR64_with_sub_8bitRegClass, 5796 &X86::GR64_NOSPRegClass, 5797 &X86::GR64_NOREXRegClass, 5798 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5799 nullptr 5800}; 5801 5802static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = { 5803 &X86::GR64RegClass, 5804 &X86::GR64_TCRegClass, 5805 &X86::GR64_NOREXRegClass, 5806 nullptr 5807}; 5808 5809static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = { 5810 &X86::GR64RegClass, 5811 &X86::GR64_with_sub_8bitRegClass, 5812 &X86::GR64_NOSPRegClass, 5813 &X86::GR64_TCW64RegClass, 5814 &X86::GR64_TCW64_with_sub_8bitRegClass, 5815 nullptr 5816}; 5817 5818static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = { 5819 &X86::GR64RegClass, 5820 &X86::GR64_with_sub_8bitRegClass, 5821 &X86::GR64_TCRegClass, 5822 &X86::GR64_TCW64RegClass, 5823 &X86::GR64_TC_with_sub_8bitRegClass, 5824 &X86::GR64_TCW64_with_sub_8bitRegClass, 5825 &X86::GR64_TC_and_GR64_TCW64RegClass, 5826 nullptr 5827}; 5828 5829static const TargetRegisterClass *const VK64WMSuperclasses[] = { 5830 &X86::VK1RegClass, 5831 &X86::VK16RegClass, 5832 &X86::VK2RegClass, 5833 &X86::VK4RegClass, 5834 &X86::VK8RegClass, 5835 &X86::VK16WMRegClass, 5836 &X86::VK1WMRegClass, 5837 &X86::VK2WMRegClass, 5838 &X86::VK4WMRegClass, 5839 &X86::VK8WMRegClass, 5840 &X86::VK32RegClass, 5841 &X86::VK32WMRegClass, 5842 &X86::VK64RegClass, 5843 nullptr 5844}; 5845 5846static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = { 5847 &X86::GR64RegClass, 5848 &X86::GR64_with_sub_8bitRegClass, 5849 &X86::GR64_NOSPRegClass, 5850 &X86::GR64_TCRegClass, 5851 &X86::GR64_TCW64RegClass, 5852 &X86::GR64_TC_with_sub_8bitRegClass, 5853 &X86::GR64_NOSP_and_GR64_TCRegClass, 5854 &X86::GR64_TCW64_with_sub_8bitRegClass, 5855 &X86::GR64_TC_and_GR64_TCW64RegClass, 5856 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 5857 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 5858 nullptr 5859}; 5860 5861static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = { 5862 &X86::GR64RegClass, 5863 &X86::GR64_with_sub_8bitRegClass, 5864 &X86::GR64_TCRegClass, 5865 &X86::GR64_NOREXRegClass, 5866 &X86::GR64_TC_with_sub_8bitRegClass, 5867 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5868 &X86::GR64_NOREX_and_GR64_TCRegClass, 5869 nullptr 5870}; 5871 5872static const TargetRegisterClass *const GR64_NOREX_NOSP_and_GR64_TCSuperclasses[] = { 5873 &X86::GR64RegClass, 5874 &X86::GR64_with_sub_8bitRegClass, 5875 &X86::GR64_NOSPRegClass, 5876 &X86::GR64_TCRegClass, 5877 &X86::GR64_NOREXRegClass, 5878 &X86::GR64_TC_with_sub_8bitRegClass, 5879 &X86::GR64_NOSP_and_GR64_TCRegClass, 5880 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5881 &X86::GR64_NOREX_NOSPRegClass, 5882 &X86::GR64_NOREX_and_GR64_TCRegClass, 5883 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5884 nullptr 5885}; 5886 5887static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = { 5888 &X86::GR64RegClass, 5889 &X86::GR64_TCRegClass, 5890 &X86::GR64_NOREXRegClass, 5891 &X86::GR64_TCW64RegClass, 5892 &X86::GR64_TC_and_GR64_TCW64RegClass, 5893 &X86::GR64_NOREX_and_GR64_TCRegClass, 5894 nullptr 5895}; 5896 5897static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = { 5898 &X86::GR64RegClass, 5899 &X86::GR64_with_sub_8bitRegClass, 5900 &X86::GR64_NOSPRegClass, 5901 &X86::GR64_NOREXRegClass, 5902 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5903 &X86::GR64_NOREX_NOSPRegClass, 5904 nullptr 5905}; 5906 5907static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = { 5908 &X86::GR64RegClass, 5909 &X86::GR64_with_sub_8bitRegClass, 5910 &X86::GR64_TCRegClass, 5911 &X86::GR64_NOREXRegClass, 5912 &X86::GR64_TCW64RegClass, 5913 &X86::GR64_TC_with_sub_8bitRegClass, 5914 &X86::GR64_TCW64_with_sub_8bitRegClass, 5915 &X86::GR64_TC_and_GR64_TCW64RegClass, 5916 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5917 &X86::GR64_NOREX_and_GR64_TCRegClass, 5918 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 5919 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5920 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 5921 nullptr 5922}; 5923 5924static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = { 5925 &X86::GR64RegClass, 5926 &X86::GR64_with_sub_8bitRegClass, 5927 &X86::GR64_NOSPRegClass, 5928 &X86::GR64_TCRegClass, 5929 &X86::GR64_NOREXRegClass, 5930 &X86::GR64_TCW64RegClass, 5931 &X86::GR64_TC_with_sub_8bitRegClass, 5932 &X86::GR64_NOSP_and_GR64_TCRegClass, 5933 &X86::GR64_TCW64_with_sub_8bitRegClass, 5934 &X86::GR64_TC_and_GR64_TCW64RegClass, 5935 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5936 &X86::GR64_NOREX_NOSPRegClass, 5937 &X86::GR64_NOREX_and_GR64_TCRegClass, 5938 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 5939 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 5940 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 5941 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5942 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 5943 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 5944 &X86::GR64_ABCDRegClass, 5945 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 5946 nullptr 5947}; 5948 5949static const TargetRegisterClass *const GR64_ADSuperclasses[] = { 5950 &X86::GR64RegClass, 5951 &X86::GR64_with_sub_8bitRegClass, 5952 &X86::GR64_NOSPRegClass, 5953 &X86::GR64_TCRegClass, 5954 &X86::GR64_NOREXRegClass, 5955 &X86::GR64_TCW64RegClass, 5956 &X86::GR64_TC_with_sub_8bitRegClass, 5957 &X86::GR64_NOSP_and_GR64_TCRegClass, 5958 &X86::GR64_TCW64_with_sub_8bitRegClass, 5959 &X86::GR64_TC_and_GR64_TCW64RegClass, 5960 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5961 &X86::GR64_NOREX_NOSPRegClass, 5962 &X86::GR64_NOREX_and_GR64_TCRegClass, 5963 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 5964 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 5965 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 5966 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5967 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 5968 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 5969 &X86::GR64_ABCDRegClass, 5970 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 5971 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass, 5972 nullptr 5973}; 5974 5975static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = { 5976 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 5977 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 5978 &X86::GR64RegClass, 5979 &X86::GR64_NOREXRegClass, 5980 nullptr 5981}; 5982 5983static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = { 5984 &X86::GR64RegClass, 5985 &X86::GR64_with_sub_8bitRegClass, 5986 &X86::GR64_NOREXRegClass, 5987 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5988 nullptr 5989}; 5990 5991static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = { 5992 &X86::GR64RegClass, 5993 &X86::GR64_with_sub_8bitRegClass, 5994 &X86::GR64_NOSPRegClass, 5995 &X86::GR64_NOREXRegClass, 5996 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 5997 &X86::GR64_NOREX_NOSPRegClass, 5998 nullptr 5999}; 6000 6001static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = { 6002 &X86::GR64RegClass, 6003 &X86::GR64_with_sub_8bitRegClass, 6004 &X86::GR64_NOSPRegClass, 6005 &X86::GR64_NOREXRegClass, 6006 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6007 &X86::GR64_NOREX_NOSPRegClass, 6008 &X86::GR64_ABCDRegClass, 6009 nullptr 6010}; 6011 6012static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = { 6013 &X86::GR64RegClass, 6014 &X86::GR64_with_sub_8bitRegClass, 6015 &X86::GR64_NOSPRegClass, 6016 &X86::GR64_TCRegClass, 6017 &X86::GR64_NOREXRegClass, 6018 &X86::GR64_TCW64RegClass, 6019 &X86::GR64_TC_with_sub_8bitRegClass, 6020 &X86::GR64_NOSP_and_GR64_TCRegClass, 6021 &X86::GR64_TCW64_with_sub_8bitRegClass, 6022 &X86::GR64_TC_and_GR64_TCW64RegClass, 6023 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6024 &X86::GR64_NOREX_NOSPRegClass, 6025 &X86::GR64_NOREX_and_GR64_TCRegClass, 6026 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 6027 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 6028 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 6029 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6030 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6031 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 6032 &X86::GR64_ABCDRegClass, 6033 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 6034 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass, 6035 nullptr 6036}; 6037 6038static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = { 6039 &X86::GR64RegClass, 6040 &X86::GR64_with_sub_8bitRegClass, 6041 &X86::GR64_NOSPRegClass, 6042 &X86::GR64_NOREXRegClass, 6043 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6044 &X86::GR64_NOREX_NOSPRegClass, 6045 nullptr 6046}; 6047 6048static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = { 6049 &X86::GR64RegClass, 6050 &X86::GR64_with_sub_8bitRegClass, 6051 &X86::GR64_NOSPRegClass, 6052 &X86::GR64_TCRegClass, 6053 &X86::GR64_NOREXRegClass, 6054 &X86::GR64_TC_with_sub_8bitRegClass, 6055 &X86::GR64_NOSP_and_GR64_TCRegClass, 6056 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6057 &X86::GR64_NOREX_NOSPRegClass, 6058 &X86::GR64_NOREX_and_GR64_TCRegClass, 6059 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6060 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6061 nullptr 6062}; 6063 6064static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = { 6065 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 6066 &X86::LOW32_ADDR_ACCESSRegClass, 6067 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 6068 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass, 6069 &X86::GR64RegClass, 6070 &X86::GR64_TCRegClass, 6071 &X86::GR64_NOREXRegClass, 6072 &X86::GR64_TCW64RegClass, 6073 &X86::GR64_TC_and_GR64_TCW64RegClass, 6074 &X86::GR64_NOREX_and_GR64_TCRegClass, 6075 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 6076 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass, 6077 nullptr 6078}; 6079 6080static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = { 6081 &X86::GR64RegClass, 6082 &X86::GR64_with_sub_8bitRegClass, 6083 &X86::GR64_NOSPRegClass, 6084 &X86::GR64_NOREXRegClass, 6085 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6086 &X86::GR64_NOREX_NOSPRegClass, 6087 &X86::GR64_ABCDRegClass, 6088 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass, 6089 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass, 6090 nullptr 6091}; 6092 6093static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses[] = { 6094 &X86::GR64RegClass, 6095 &X86::GR64_with_sub_8bitRegClass, 6096 &X86::GR64_NOSPRegClass, 6097 &X86::GR64_TCRegClass, 6098 &X86::GR64_NOREXRegClass, 6099 &X86::GR64_TCW64RegClass, 6100 &X86::GR64_TC_with_sub_8bitRegClass, 6101 &X86::GR64_NOSP_and_GR64_TCRegClass, 6102 &X86::GR64_TCW64_with_sub_8bitRegClass, 6103 &X86::GR64_TC_and_GR64_TCW64RegClass, 6104 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6105 &X86::GR64_NOREX_NOSPRegClass, 6106 &X86::GR64_NOREX_and_GR64_TCRegClass, 6107 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 6108 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 6109 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 6110 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6111 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6112 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 6113 &X86::GR64_ABCDRegClass, 6114 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 6115 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass, 6116 &X86::GR64_ADRegClass, 6117 &X86::GR64_with_sub_32bit_in_GR32_DCRegClass, 6118 nullptr 6119}; 6120 6121static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = { 6122 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 6123 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 6124 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 6125 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 6126 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass, 6127 &X86::GR64RegClass, 6128 &X86::GR64_with_sub_8bitRegClass, 6129 &X86::GR64_NOSPRegClass, 6130 &X86::GR64_NOREXRegClass, 6131 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6132 &X86::GR64_NOREX_NOSPRegClass, 6133 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass, 6134 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass, 6135 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass, 6136 nullptr 6137}; 6138 6139static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = { 6140 &X86::GR64RegClass, 6141 &X86::GR64_with_sub_8bitRegClass, 6142 &X86::GR64_TCRegClass, 6143 &X86::GR64_NOREXRegClass, 6144 &X86::GR64_TCW64RegClass, 6145 &X86::GR64_TC_with_sub_8bitRegClass, 6146 &X86::GR64_TCW64_with_sub_8bitRegClass, 6147 &X86::GR64_TC_and_GR64_TCW64RegClass, 6148 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6149 &X86::GR64_NOREX_and_GR64_TCRegClass, 6150 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 6151 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6152 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 6153 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 6154 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass, 6155 nullptr 6156}; 6157 6158static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = { 6159 &X86::GR64RegClass, 6160 &X86::GR64_with_sub_8bitRegClass, 6161 &X86::GR64_NOSPRegClass, 6162 &X86::GR64_TCRegClass, 6163 &X86::GR64_NOREXRegClass, 6164 &X86::GR64_TC_with_sub_8bitRegClass, 6165 &X86::GR64_NOSP_and_GR64_TCRegClass, 6166 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6167 &X86::GR64_NOREX_NOSPRegClass, 6168 &X86::GR64_NOREX_and_GR64_TCRegClass, 6169 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6170 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6171 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass, 6172 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass, 6173 nullptr 6174}; 6175 6176static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses[] = { 6177 &X86::GR64RegClass, 6178 &X86::GR64_with_sub_8bitRegClass, 6179 &X86::GR64_NOSPRegClass, 6180 &X86::GR64_TCRegClass, 6181 &X86::GR64_NOREXRegClass, 6182 &X86::GR64_TCW64RegClass, 6183 &X86::GR64_TC_with_sub_8bitRegClass, 6184 &X86::GR64_NOSP_and_GR64_TCRegClass, 6185 &X86::GR64_TCW64_with_sub_8bitRegClass, 6186 &X86::GR64_TC_and_GR64_TCW64RegClass, 6187 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6188 &X86::GR64_NOREX_NOSPRegClass, 6189 &X86::GR64_NOREX_and_GR64_TCRegClass, 6190 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 6191 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 6192 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 6193 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6194 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6195 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 6196 &X86::GR64_ABCDRegClass, 6197 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 6198 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass, 6199 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass, 6200 &X86::GR64_with_sub_32bit_in_GR32_DCRegClass, 6201 nullptr 6202}; 6203 6204static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = { 6205 &X86::GR64RegClass, 6206 &X86::GR64_with_sub_8bitRegClass, 6207 &X86::GR64_NOSPRegClass, 6208 &X86::GR64_TCRegClass, 6209 &X86::GR64_NOREXRegClass, 6210 &X86::GR64_TC_with_sub_8bitRegClass, 6211 &X86::GR64_NOSP_and_GR64_TCRegClass, 6212 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6213 &X86::GR64_NOREX_NOSPRegClass, 6214 &X86::GR64_NOREX_and_GR64_TCRegClass, 6215 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 6216 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 6217 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass, 6218 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass, 6219 nullptr 6220}; 6221 6222static const TargetRegisterClass *const RFP80Superclasses[] = { 6223 &X86::RFP32RegClass, 6224 &X86::RFP64RegClass, 6225 nullptr 6226}; 6227 6228static const TargetRegisterClass *const VR128XSuperclasses[] = { 6229 &X86::FR32XRegClass, 6230 &X86::FR64XRegClass, 6231 nullptr 6232}; 6233 6234static const TargetRegisterClass *const VR128Superclasses[] = { 6235 &X86::FR32XRegClass, 6236 &X86::FR32RegClass, 6237 &X86::FR64XRegClass, 6238 &X86::FR64RegClass, 6239 &X86::VR128XRegClass, 6240 nullptr 6241}; 6242 6243static const TargetRegisterClass *const VR256Superclasses[] = { 6244 &X86::VR256XRegClass, 6245 nullptr 6246}; 6247 6248static const TargetRegisterClass *const VR512_0_15Superclasses[] = { 6249 &X86::VR512RegClass, 6250 nullptr 6251}; 6252 6253 6254static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) { 6255 return MF.getSubtarget<X86Subtarget>().is64Bit(); 6256 } 6257 6258static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) { 6259 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B }; 6260 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID]; 6261 const ArrayRef<MCPhysReg> Order[] = { 6262 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6263 makeArrayRef(AltOrder1) 6264 }; 6265 const unsigned Select = GR8AltOrderSelect(MF); 6266 assert(Select < 2); 6267 return Order[Select]; 6268} 6269 6270static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) { 6271 return MF.getSubtarget<X86Subtarget>().is64Bit(); 6272 } 6273 6274static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) { 6275 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL }; 6276 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID]; 6277 const ArrayRef<MCPhysReg> Order[] = { 6278 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6279 makeArrayRef(AltOrder1) 6280 }; 6281 const unsigned Select = GR8_NOREXAltOrderSelect(MF); 6282 assert(Select < 2); 6283 return Order[Select]; 6284} 6285 6286namespace X86 { // Register class instances 6287 extern const TargetRegisterClass GR8RegClass = { 6288 &X86MCRegisterClasses[GR8RegClassID], 6289 GR8SubClassMask, 6290 SuperRegIdxSeqs + 2, 6291 LaneBitmask(0x00000001), 6292 0, 6293 false, /* HasDisjunctSubRegs */ 6294 false, /* CoveredBySubRegs */ 6295 NullRegClasses, 6296 GR8GetRawAllocationOrder 6297 }; 6298 6299 extern const TargetRegisterClass GRH8RegClass = { 6300 &X86MCRegisterClasses[GRH8RegClassID], 6301 GRH8SubClassMask, 6302 SuperRegIdxSeqs + 1, 6303 LaneBitmask(0x00000001), 6304 0, 6305 false, /* HasDisjunctSubRegs */ 6306 false, /* CoveredBySubRegs */ 6307 NullRegClasses, 6308 nullptr 6309 }; 6310 6311 extern const TargetRegisterClass GR8_NOREXRegClass = { 6312 &X86MCRegisterClasses[GR8_NOREXRegClassID], 6313 GR8_NOREXSubClassMask, 6314 SuperRegIdxSeqs + 2, 6315 LaneBitmask(0x00000001), 6316 0, 6317 false, /* HasDisjunctSubRegs */ 6318 false, /* CoveredBySubRegs */ 6319 GR8_NOREXSuperclasses, 6320 GR8_NOREXGetRawAllocationOrder 6321 }; 6322 6323 extern const TargetRegisterClass GR8_ABCD_HRegClass = { 6324 &X86MCRegisterClasses[GR8_ABCD_HRegClassID], 6325 GR8_ABCD_HSubClassMask, 6326 SuperRegIdxSeqs + 3, 6327 LaneBitmask(0x00000001), 6328 0, 6329 false, /* HasDisjunctSubRegs */ 6330 false, /* CoveredBySubRegs */ 6331 GR8_ABCD_HSuperclasses, 6332 nullptr 6333 }; 6334 6335 extern const TargetRegisterClass GR8_ABCD_LRegClass = { 6336 &X86MCRegisterClasses[GR8_ABCD_LRegClassID], 6337 GR8_ABCD_LSubClassMask, 6338 SuperRegIdxSeqs + 0, 6339 LaneBitmask(0x00000001), 6340 0, 6341 false, /* HasDisjunctSubRegs */ 6342 false, /* CoveredBySubRegs */ 6343 GR8_ABCD_LSuperclasses, 6344 nullptr 6345 }; 6346 6347 extern const TargetRegisterClass GRH16RegClass = { 6348 &X86MCRegisterClasses[GRH16RegClassID], 6349 GRH16SubClassMask, 6350 SuperRegIdxSeqs + 1, 6351 LaneBitmask(0x00000001), 6352 0, 6353 false, /* HasDisjunctSubRegs */ 6354 false, /* CoveredBySubRegs */ 6355 NullRegClasses, 6356 nullptr 6357 }; 6358 6359 extern const TargetRegisterClass GR16RegClass = { 6360 &X86MCRegisterClasses[GR16RegClassID], 6361 GR16SubClassMask, 6362 SuperRegIdxSeqs + 5, 6363 LaneBitmask(0x00000003), 6364 0, 6365 true, /* HasDisjunctSubRegs */ 6366 true, /* CoveredBySubRegs */ 6367 NullRegClasses, 6368 nullptr 6369 }; 6370 6371 extern const TargetRegisterClass GR16_NOREXRegClass = { 6372 &X86MCRegisterClasses[GR16_NOREXRegClassID], 6373 GR16_NOREXSubClassMask, 6374 SuperRegIdxSeqs + 5, 6375 LaneBitmask(0x00000003), 6376 0, 6377 true, /* HasDisjunctSubRegs */ 6378 true, /* CoveredBySubRegs */ 6379 GR16_NOREXSuperclasses, 6380 nullptr 6381 }; 6382 6383 extern const TargetRegisterClass VK1RegClass = { 6384 &X86MCRegisterClasses[VK1RegClassID], 6385 VK1SubClassMask, 6386 SuperRegIdxSeqs + 9, 6387 LaneBitmask(0x00000001), 6388 0, 6389 false, /* HasDisjunctSubRegs */ 6390 false, /* CoveredBySubRegs */ 6391 VK1Superclasses, 6392 nullptr 6393 }; 6394 6395 extern const TargetRegisterClass VK16RegClass = { 6396 &X86MCRegisterClasses[VK16RegClassID], 6397 VK16SubClassMask, 6398 SuperRegIdxSeqs + 9, 6399 LaneBitmask(0x00000001), 6400 0, 6401 false, /* HasDisjunctSubRegs */ 6402 false, /* CoveredBySubRegs */ 6403 VK16Superclasses, 6404 nullptr 6405 }; 6406 6407 extern const TargetRegisterClass VK2RegClass = { 6408 &X86MCRegisterClasses[VK2RegClassID], 6409 VK2SubClassMask, 6410 SuperRegIdxSeqs + 9, 6411 LaneBitmask(0x00000001), 6412 0, 6413 false, /* HasDisjunctSubRegs */ 6414 false, /* CoveredBySubRegs */ 6415 VK2Superclasses, 6416 nullptr 6417 }; 6418 6419 extern const TargetRegisterClass VK4RegClass = { 6420 &X86MCRegisterClasses[VK4RegClassID], 6421 VK4SubClassMask, 6422 SuperRegIdxSeqs + 9, 6423 LaneBitmask(0x00000001), 6424 0, 6425 false, /* HasDisjunctSubRegs */ 6426 false, /* CoveredBySubRegs */ 6427 VK4Superclasses, 6428 nullptr 6429 }; 6430 6431 extern const TargetRegisterClass VK8RegClass = { 6432 &X86MCRegisterClasses[VK8RegClassID], 6433 VK8SubClassMask, 6434 SuperRegIdxSeqs + 9, 6435 LaneBitmask(0x00000001), 6436 0, 6437 false, /* HasDisjunctSubRegs */ 6438 false, /* CoveredBySubRegs */ 6439 VK8Superclasses, 6440 nullptr 6441 }; 6442 6443 extern const TargetRegisterClass VK16WMRegClass = { 6444 &X86MCRegisterClasses[VK16WMRegClassID], 6445 VK16WMSubClassMask, 6446 SuperRegIdxSeqs + 9, 6447 LaneBitmask(0x00000001), 6448 0, 6449 false, /* HasDisjunctSubRegs */ 6450 false, /* CoveredBySubRegs */ 6451 VK16WMSuperclasses, 6452 nullptr 6453 }; 6454 6455 extern const TargetRegisterClass VK1WMRegClass = { 6456 &X86MCRegisterClasses[VK1WMRegClassID], 6457 VK1WMSubClassMask, 6458 SuperRegIdxSeqs + 9, 6459 LaneBitmask(0x00000001), 6460 0, 6461 false, /* HasDisjunctSubRegs */ 6462 false, /* CoveredBySubRegs */ 6463 VK1WMSuperclasses, 6464 nullptr 6465 }; 6466 6467 extern const TargetRegisterClass VK2WMRegClass = { 6468 &X86MCRegisterClasses[VK2WMRegClassID], 6469 VK2WMSubClassMask, 6470 SuperRegIdxSeqs + 9, 6471 LaneBitmask(0x00000001), 6472 0, 6473 false, /* HasDisjunctSubRegs */ 6474 false, /* CoveredBySubRegs */ 6475 VK2WMSuperclasses, 6476 nullptr 6477 }; 6478 6479 extern const TargetRegisterClass VK4WMRegClass = { 6480 &X86MCRegisterClasses[VK4WMRegClassID], 6481 VK4WMSubClassMask, 6482 SuperRegIdxSeqs + 9, 6483 LaneBitmask(0x00000001), 6484 0, 6485 false, /* HasDisjunctSubRegs */ 6486 false, /* CoveredBySubRegs */ 6487 VK4WMSuperclasses, 6488 nullptr 6489 }; 6490 6491 extern const TargetRegisterClass VK8WMRegClass = { 6492 &X86MCRegisterClasses[VK8WMRegClassID], 6493 VK8WMSubClassMask, 6494 SuperRegIdxSeqs + 9, 6495 LaneBitmask(0x00000001), 6496 0, 6497 false, /* HasDisjunctSubRegs */ 6498 false, /* CoveredBySubRegs */ 6499 VK8WMSuperclasses, 6500 nullptr 6501 }; 6502 6503 extern const TargetRegisterClass SEGMENT_REGRegClass = { 6504 &X86MCRegisterClasses[SEGMENT_REGRegClassID], 6505 SEGMENT_REGSubClassMask, 6506 SuperRegIdxSeqs + 1, 6507 LaneBitmask(0x00000001), 6508 0, 6509 false, /* HasDisjunctSubRegs */ 6510 false, /* CoveredBySubRegs */ 6511 NullRegClasses, 6512 nullptr 6513 }; 6514 6515 extern const TargetRegisterClass GR16_ABCDRegClass = { 6516 &X86MCRegisterClasses[GR16_ABCDRegClassID], 6517 GR16_ABCDSubClassMask, 6518 SuperRegIdxSeqs + 5, 6519 LaneBitmask(0x00000003), 6520 0, 6521 true, /* HasDisjunctSubRegs */ 6522 true, /* CoveredBySubRegs */ 6523 GR16_ABCDSuperclasses, 6524 nullptr 6525 }; 6526 6527 extern const TargetRegisterClass FPCCRRegClass = { 6528 &X86MCRegisterClasses[FPCCRRegClassID], 6529 FPCCRSubClassMask, 6530 SuperRegIdxSeqs + 1, 6531 LaneBitmask(0x00000001), 6532 0, 6533 false, /* HasDisjunctSubRegs */ 6534 false, /* CoveredBySubRegs */ 6535 NullRegClasses, 6536 nullptr 6537 }; 6538 6539 extern const TargetRegisterClass VK16PAIRRegClass = { 6540 &X86MCRegisterClasses[VK16PAIRRegClassID], 6541 VK16PAIRSubClassMask, 6542 SuperRegIdxSeqs + 1, 6543 LaneBitmask(0x00000030), 6544 0, 6545 true, /* HasDisjunctSubRegs */ 6546 true, /* CoveredBySubRegs */ 6547 VK16PAIRSuperclasses, 6548 nullptr 6549 }; 6550 6551 extern const TargetRegisterClass VK1PAIRRegClass = { 6552 &X86MCRegisterClasses[VK1PAIRRegClassID], 6553 VK1PAIRSubClassMask, 6554 SuperRegIdxSeqs + 1, 6555 LaneBitmask(0x00000030), 6556 0, 6557 true, /* HasDisjunctSubRegs */ 6558 true, /* CoveredBySubRegs */ 6559 VK1PAIRSuperclasses, 6560 nullptr 6561 }; 6562 6563 extern const TargetRegisterClass VK2PAIRRegClass = { 6564 &X86MCRegisterClasses[VK2PAIRRegClassID], 6565 VK2PAIRSubClassMask, 6566 SuperRegIdxSeqs + 1, 6567 LaneBitmask(0x00000030), 6568 0, 6569 true, /* HasDisjunctSubRegs */ 6570 true, /* CoveredBySubRegs */ 6571 VK2PAIRSuperclasses, 6572 nullptr 6573 }; 6574 6575 extern const TargetRegisterClass VK4PAIRRegClass = { 6576 &X86MCRegisterClasses[VK4PAIRRegClassID], 6577 VK4PAIRSubClassMask, 6578 SuperRegIdxSeqs + 1, 6579 LaneBitmask(0x00000030), 6580 0, 6581 true, /* HasDisjunctSubRegs */ 6582 true, /* CoveredBySubRegs */ 6583 VK4PAIRSuperclasses, 6584 nullptr 6585 }; 6586 6587 extern const TargetRegisterClass VK8PAIRRegClass = { 6588 &X86MCRegisterClasses[VK8PAIRRegClassID], 6589 VK8PAIRSubClassMask, 6590 SuperRegIdxSeqs + 1, 6591 LaneBitmask(0x00000030), 6592 0, 6593 true, /* HasDisjunctSubRegs */ 6594 true, /* CoveredBySubRegs */ 6595 VK8PAIRSuperclasses, 6596 nullptr 6597 }; 6598 6599 extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass = { 6600 &X86MCRegisterClasses[VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID], 6601 VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask, 6602 SuperRegIdxSeqs + 1, 6603 LaneBitmask(0x00000030), 6604 0, 6605 true, /* HasDisjunctSubRegs */ 6606 true, /* CoveredBySubRegs */ 6607 VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses, 6608 nullptr 6609 }; 6610 6611 extern const TargetRegisterClass FR32XRegClass = { 6612 &X86MCRegisterClasses[FR32XRegClassID], 6613 FR32XSubClassMask, 6614 SuperRegIdxSeqs + 12, 6615 LaneBitmask(0x00000001), 6616 0, 6617 false, /* HasDisjunctSubRegs */ 6618 false, /* CoveredBySubRegs */ 6619 NullRegClasses, 6620 nullptr 6621 }; 6622 6623 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = { 6624 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID], 6625 LOW32_ADDR_ACCESS_RBPSubClassMask, 6626 SuperRegIdxSeqs + 7, 6627 LaneBitmask(0x0000000F), 6628 0, 6629 true, /* HasDisjunctSubRegs */ 6630 false, /* CoveredBySubRegs */ 6631 NullRegClasses, 6632 nullptr 6633 }; 6634 6635 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = { 6636 &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID], 6637 LOW32_ADDR_ACCESSSubClassMask, 6638 SuperRegIdxSeqs + 7, 6639 LaneBitmask(0x0000000F), 6640 0, 6641 true, /* HasDisjunctSubRegs */ 6642 false, /* CoveredBySubRegs */ 6643 LOW32_ADDR_ACCESSSuperclasses, 6644 nullptr 6645 }; 6646 6647 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = { 6648 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID], 6649 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask, 6650 SuperRegIdxSeqs + 7, 6651 LaneBitmask(0x0000000F), 6652 0, 6653 true, /* HasDisjunctSubRegs */ 6654 false, /* CoveredBySubRegs */ 6655 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, 6656 nullptr 6657 }; 6658 6659 extern const TargetRegisterClass DEBUG_REGRegClass = { 6660 &X86MCRegisterClasses[DEBUG_REGRegClassID], 6661 DEBUG_REGSubClassMask, 6662 SuperRegIdxSeqs + 1, 6663 LaneBitmask(0x00000001), 6664 0, 6665 false, /* HasDisjunctSubRegs */ 6666 false, /* CoveredBySubRegs */ 6667 NullRegClasses, 6668 nullptr 6669 }; 6670 6671 extern const TargetRegisterClass FR32RegClass = { 6672 &X86MCRegisterClasses[FR32RegClassID], 6673 FR32SubClassMask, 6674 SuperRegIdxSeqs + 12, 6675 LaneBitmask(0x00000001), 6676 0, 6677 false, /* HasDisjunctSubRegs */ 6678 false, /* CoveredBySubRegs */ 6679 FR32Superclasses, 6680 nullptr 6681 }; 6682 6683 extern const TargetRegisterClass GR32RegClass = { 6684 &X86MCRegisterClasses[GR32RegClassID], 6685 GR32SubClassMask, 6686 SuperRegIdxSeqs + 7, 6687 LaneBitmask(0x00000007), 6688 0, 6689 true, /* HasDisjunctSubRegs */ 6690 true, /* CoveredBySubRegs */ 6691 GR32Superclasses, 6692 nullptr 6693 }; 6694 6695 extern const TargetRegisterClass GR32_NOSPRegClass = { 6696 &X86MCRegisterClasses[GR32_NOSPRegClassID], 6697 GR32_NOSPSubClassMask, 6698 SuperRegIdxSeqs + 7, 6699 LaneBitmask(0x00000007), 6700 0, 6701 true, /* HasDisjunctSubRegs */ 6702 true, /* CoveredBySubRegs */ 6703 GR32_NOSPSuperclasses, 6704 nullptr 6705 }; 6706 6707 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = { 6708 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID], 6709 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask, 6710 SuperRegIdxSeqs + 7, 6711 LaneBitmask(0x0000000F), 6712 0, 6713 true, /* HasDisjunctSubRegs */ 6714 false, /* CoveredBySubRegs */ 6715 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, 6716 nullptr 6717 }; 6718 6719 extern const TargetRegisterClass GR32_NOREXRegClass = { 6720 &X86MCRegisterClasses[GR32_NOREXRegClassID], 6721 GR32_NOREXSubClassMask, 6722 SuperRegIdxSeqs + 7, 6723 LaneBitmask(0x00000007), 6724 0, 6725 true, /* HasDisjunctSubRegs */ 6726 true, /* CoveredBySubRegs */ 6727 GR32_NOREXSuperclasses, 6728 nullptr 6729 }; 6730 6731 extern const TargetRegisterClass VK32RegClass = { 6732 &X86MCRegisterClasses[VK32RegClassID], 6733 VK32SubClassMask, 6734 SuperRegIdxSeqs + 9, 6735 LaneBitmask(0x00000001), 6736 0, 6737 false, /* HasDisjunctSubRegs */ 6738 false, /* CoveredBySubRegs */ 6739 VK32Superclasses, 6740 nullptr 6741 }; 6742 6743 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = { 6744 &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID], 6745 GR32_NOREX_NOSPSubClassMask, 6746 SuperRegIdxSeqs + 7, 6747 LaneBitmask(0x00000007), 6748 0, 6749 true, /* HasDisjunctSubRegs */ 6750 true, /* CoveredBySubRegs */ 6751 GR32_NOREX_NOSPSuperclasses, 6752 nullptr 6753 }; 6754 6755 extern const TargetRegisterClass RFP32RegClass = { 6756 &X86MCRegisterClasses[RFP32RegClassID], 6757 RFP32SubClassMask, 6758 SuperRegIdxSeqs + 1, 6759 LaneBitmask(0x00000001), 6760 0, 6761 false, /* HasDisjunctSubRegs */ 6762 false, /* CoveredBySubRegs */ 6763 NullRegClasses, 6764 nullptr 6765 }; 6766 6767 extern const TargetRegisterClass VK32WMRegClass = { 6768 &X86MCRegisterClasses[VK32WMRegClassID], 6769 VK32WMSubClassMask, 6770 SuperRegIdxSeqs + 9, 6771 LaneBitmask(0x00000001), 6772 0, 6773 false, /* HasDisjunctSubRegs */ 6774 false, /* CoveredBySubRegs */ 6775 VK32WMSuperclasses, 6776 nullptr 6777 }; 6778 6779 extern const TargetRegisterClass GR32_ABCDRegClass = { 6780 &X86MCRegisterClasses[GR32_ABCDRegClassID], 6781 GR32_ABCDSubClassMask, 6782 SuperRegIdxSeqs + 7, 6783 LaneBitmask(0x00000007), 6784 0, 6785 true, /* HasDisjunctSubRegs */ 6786 true, /* CoveredBySubRegs */ 6787 GR32_ABCDSuperclasses, 6788 nullptr 6789 }; 6790 6791 extern const TargetRegisterClass GR32_TCRegClass = { 6792 &X86MCRegisterClasses[GR32_TCRegClassID], 6793 GR32_TCSubClassMask, 6794 SuperRegIdxSeqs + 7, 6795 LaneBitmask(0x00000007), 6796 0, 6797 true, /* HasDisjunctSubRegs */ 6798 true, /* CoveredBySubRegs */ 6799 GR32_TCSuperclasses, 6800 nullptr 6801 }; 6802 6803 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = { 6804 &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID], 6805 GR32_ABCD_and_GR32_TCSubClassMask, 6806 SuperRegIdxSeqs + 7, 6807 LaneBitmask(0x00000007), 6808 0, 6809 true, /* HasDisjunctSubRegs */ 6810 true, /* CoveredBySubRegs */ 6811 GR32_ABCD_and_GR32_TCSuperclasses, 6812 nullptr 6813 }; 6814 6815 extern const TargetRegisterClass GR32_ADRegClass = { 6816 &X86MCRegisterClasses[GR32_ADRegClassID], 6817 GR32_ADSubClassMask, 6818 SuperRegIdxSeqs + 7, 6819 LaneBitmask(0x00000007), 6820 0, 6821 true, /* HasDisjunctSubRegs */ 6822 true, /* CoveredBySubRegs */ 6823 GR32_ADSuperclasses, 6824 nullptr 6825 }; 6826 6827 extern const TargetRegisterClass GR32_BPSPRegClass = { 6828 &X86MCRegisterClasses[GR32_BPSPRegClassID], 6829 GR32_BPSPSubClassMask, 6830 SuperRegIdxSeqs + 7, 6831 LaneBitmask(0x00000007), 6832 0, 6833 true, /* HasDisjunctSubRegs */ 6834 true, /* CoveredBySubRegs */ 6835 GR32_BPSPSuperclasses, 6836 nullptr 6837 }; 6838 6839 extern const TargetRegisterClass GR32_BSIRegClass = { 6840 &X86MCRegisterClasses[GR32_BSIRegClassID], 6841 GR32_BSISubClassMask, 6842 SuperRegIdxSeqs + 7, 6843 LaneBitmask(0x00000007), 6844 0, 6845 true, /* HasDisjunctSubRegs */ 6846 true, /* CoveredBySubRegs */ 6847 GR32_BSISuperclasses, 6848 nullptr 6849 }; 6850 6851 extern const TargetRegisterClass GR32_CBRegClass = { 6852 &X86MCRegisterClasses[GR32_CBRegClassID], 6853 GR32_CBSubClassMask, 6854 SuperRegIdxSeqs + 7, 6855 LaneBitmask(0x00000007), 6856 0, 6857 true, /* HasDisjunctSubRegs */ 6858 true, /* CoveredBySubRegs */ 6859 GR32_CBSuperclasses, 6860 nullptr 6861 }; 6862 6863 extern const TargetRegisterClass GR32_DCRegClass = { 6864 &X86MCRegisterClasses[GR32_DCRegClassID], 6865 GR32_DCSubClassMask, 6866 SuperRegIdxSeqs + 7, 6867 LaneBitmask(0x00000007), 6868 0, 6869 true, /* HasDisjunctSubRegs */ 6870 true, /* CoveredBySubRegs */ 6871 GR32_DCSuperclasses, 6872 nullptr 6873 }; 6874 6875 extern const TargetRegisterClass GR32_DIBPRegClass = { 6876 &X86MCRegisterClasses[GR32_DIBPRegClassID], 6877 GR32_DIBPSubClassMask, 6878 SuperRegIdxSeqs + 7, 6879 LaneBitmask(0x00000007), 6880 0, 6881 true, /* HasDisjunctSubRegs */ 6882 true, /* CoveredBySubRegs */ 6883 GR32_DIBPSuperclasses, 6884 nullptr 6885 }; 6886 6887 extern const TargetRegisterClass GR32_SIDIRegClass = { 6888 &X86MCRegisterClasses[GR32_SIDIRegClassID], 6889 GR32_SIDISubClassMask, 6890 SuperRegIdxSeqs + 7, 6891 LaneBitmask(0x00000007), 6892 0, 6893 true, /* HasDisjunctSubRegs */ 6894 true, /* CoveredBySubRegs */ 6895 GR32_SIDISuperclasses, 6896 nullptr 6897 }; 6898 6899 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = { 6900 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID], 6901 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask, 6902 SuperRegIdxSeqs + 1, 6903 LaneBitmask(0x0000000F), 6904 0, 6905 true, /* HasDisjunctSubRegs */ 6906 false, /* CoveredBySubRegs */ 6907 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, 6908 nullptr 6909 }; 6910 6911 extern const TargetRegisterClass CCRRegClass = { 6912 &X86MCRegisterClasses[CCRRegClassID], 6913 CCRSubClassMask, 6914 SuperRegIdxSeqs + 1, 6915 LaneBitmask(0x00000001), 6916 0, 6917 false, /* HasDisjunctSubRegs */ 6918 false, /* CoveredBySubRegs */ 6919 NullRegClasses, 6920 nullptr 6921 }; 6922 6923 extern const TargetRegisterClass DFCCRRegClass = { 6924 &X86MCRegisterClasses[DFCCRRegClassID], 6925 DFCCRSubClassMask, 6926 SuperRegIdxSeqs + 1, 6927 LaneBitmask(0x00000001), 6928 0, 6929 false, /* HasDisjunctSubRegs */ 6930 false, /* CoveredBySubRegs */ 6931 NullRegClasses, 6932 nullptr 6933 }; 6934 6935 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = { 6936 &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID], 6937 GR32_ABCD_and_GR32_BSISubClassMask, 6938 SuperRegIdxSeqs + 7, 6939 LaneBitmask(0x00000007), 6940 0, 6941 true, /* HasDisjunctSubRegs */ 6942 true, /* CoveredBySubRegs */ 6943 GR32_ABCD_and_GR32_BSISuperclasses, 6944 nullptr 6945 }; 6946 6947 extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass = { 6948 &X86MCRegisterClasses[GR32_AD_and_GR32_DCRegClassID], 6949 GR32_AD_and_GR32_DCSubClassMask, 6950 SuperRegIdxSeqs + 7, 6951 LaneBitmask(0x00000007), 6952 0, 6953 true, /* HasDisjunctSubRegs */ 6954 true, /* CoveredBySubRegs */ 6955 GR32_AD_and_GR32_DCSuperclasses, 6956 nullptr 6957 }; 6958 6959 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = { 6960 &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID], 6961 GR32_BPSP_and_GR32_DIBPSubClassMask, 6962 SuperRegIdxSeqs + 7, 6963 LaneBitmask(0x00000007), 6964 0, 6965 true, /* HasDisjunctSubRegs */ 6966 true, /* CoveredBySubRegs */ 6967 GR32_BPSP_and_GR32_DIBPSuperclasses, 6968 nullptr 6969 }; 6970 6971 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = { 6972 &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID], 6973 GR32_BPSP_and_GR32_TCSubClassMask, 6974 SuperRegIdxSeqs + 7, 6975 LaneBitmask(0x00000007), 6976 0, 6977 true, /* HasDisjunctSubRegs */ 6978 true, /* CoveredBySubRegs */ 6979 GR32_BPSP_and_GR32_TCSuperclasses, 6980 nullptr 6981 }; 6982 6983 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = { 6984 &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID], 6985 GR32_BSI_and_GR32_SIDISubClassMask, 6986 SuperRegIdxSeqs + 7, 6987 LaneBitmask(0x00000007), 6988 0, 6989 true, /* HasDisjunctSubRegs */ 6990 true, /* CoveredBySubRegs */ 6991 GR32_BSI_and_GR32_SIDISuperclasses, 6992 nullptr 6993 }; 6994 6995 extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass = { 6996 &X86MCRegisterClasses[GR32_CB_and_GR32_DCRegClassID], 6997 GR32_CB_and_GR32_DCSubClassMask, 6998 SuperRegIdxSeqs + 7, 6999 LaneBitmask(0x00000007), 7000 0, 7001 true, /* HasDisjunctSubRegs */ 7002 true, /* CoveredBySubRegs */ 7003 GR32_CB_and_GR32_DCSuperclasses, 7004 nullptr 7005 }; 7006 7007 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = { 7008 &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID], 7009 GR32_DIBP_and_GR32_SIDISubClassMask, 7010 SuperRegIdxSeqs + 7, 7011 LaneBitmask(0x00000007), 7012 0, 7013 true, /* HasDisjunctSubRegs */ 7014 true, /* CoveredBySubRegs */ 7015 GR32_DIBP_and_GR32_SIDISuperclasses, 7016 nullptr 7017 }; 7018 7019 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = { 7020 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID], 7021 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask, 7022 SuperRegIdxSeqs + 1, 7023 LaneBitmask(0x0000000F), 7024 0, 7025 true, /* HasDisjunctSubRegs */ 7026 false, /* CoveredBySubRegs */ 7027 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, 7028 nullptr 7029 }; 7030 7031 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = { 7032 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID], 7033 LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask, 7034 SuperRegIdxSeqs + 1, 7035 LaneBitmask(0x0000000F), 7036 0, 7037 true, /* HasDisjunctSubRegs */ 7038 false, /* CoveredBySubRegs */ 7039 LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, 7040 nullptr 7041 }; 7042 7043 extern const TargetRegisterClass RFP64RegClass = { 7044 &X86MCRegisterClasses[RFP64RegClassID], 7045 RFP64SubClassMask, 7046 SuperRegIdxSeqs + 1, 7047 LaneBitmask(0x00000001), 7048 0, 7049 false, /* HasDisjunctSubRegs */ 7050 false, /* CoveredBySubRegs */ 7051 RFP64Superclasses, 7052 nullptr 7053 }; 7054 7055 extern const TargetRegisterClass FR64XRegClass = { 7056 &X86MCRegisterClasses[FR64XRegClassID], 7057 FR64XSubClassMask, 7058 SuperRegIdxSeqs + 12, 7059 LaneBitmask(0x00000001), 7060 0, 7061 false, /* HasDisjunctSubRegs */ 7062 false, /* CoveredBySubRegs */ 7063 FR64XSuperclasses, 7064 nullptr 7065 }; 7066 7067 extern const TargetRegisterClass GR64RegClass = { 7068 &X86MCRegisterClasses[GR64RegClassID], 7069 GR64SubClassMask, 7070 SuperRegIdxSeqs + 1, 7071 LaneBitmask(0x0000000F), 7072 0, 7073 true, /* HasDisjunctSubRegs */ 7074 false, /* CoveredBySubRegs */ 7075 NullRegClasses, 7076 nullptr 7077 }; 7078 7079 extern const TargetRegisterClass CONTROL_REGRegClass = { 7080 &X86MCRegisterClasses[CONTROL_REGRegClassID], 7081 CONTROL_REGSubClassMask, 7082 SuperRegIdxSeqs + 1, 7083 LaneBitmask(0x00000001), 7084 0, 7085 false, /* HasDisjunctSubRegs */ 7086 false, /* CoveredBySubRegs */ 7087 NullRegClasses, 7088 nullptr 7089 }; 7090 7091 extern const TargetRegisterClass FR64RegClass = { 7092 &X86MCRegisterClasses[FR64RegClassID], 7093 FR64SubClassMask, 7094 SuperRegIdxSeqs + 12, 7095 LaneBitmask(0x00000001), 7096 0, 7097 false, /* HasDisjunctSubRegs */ 7098 false, /* CoveredBySubRegs */ 7099 FR64Superclasses, 7100 nullptr 7101 }; 7102 7103 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = { 7104 &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID], 7105 GR64_with_sub_8bitSubClassMask, 7106 SuperRegIdxSeqs + 1, 7107 LaneBitmask(0x0000000F), 7108 0, 7109 true, /* HasDisjunctSubRegs */ 7110 false, /* CoveredBySubRegs */ 7111 GR64_with_sub_8bitSuperclasses, 7112 nullptr 7113 }; 7114 7115 extern const TargetRegisterClass GR64_NOSPRegClass = { 7116 &X86MCRegisterClasses[GR64_NOSPRegClassID], 7117 GR64_NOSPSubClassMask, 7118 SuperRegIdxSeqs + 1, 7119 LaneBitmask(0x0000000F), 7120 0, 7121 true, /* HasDisjunctSubRegs */ 7122 false, /* CoveredBySubRegs */ 7123 GR64_NOSPSuperclasses, 7124 nullptr 7125 }; 7126 7127 extern const TargetRegisterClass GR64_TCRegClass = { 7128 &X86MCRegisterClasses[GR64_TCRegClassID], 7129 GR64_TCSubClassMask, 7130 SuperRegIdxSeqs + 1, 7131 LaneBitmask(0x0000000F), 7132 0, 7133 true, /* HasDisjunctSubRegs */ 7134 false, /* CoveredBySubRegs */ 7135 GR64_TCSuperclasses, 7136 nullptr 7137 }; 7138 7139 extern const TargetRegisterClass GR64_NOREXRegClass = { 7140 &X86MCRegisterClasses[GR64_NOREXRegClassID], 7141 GR64_NOREXSubClassMask, 7142 SuperRegIdxSeqs + 1, 7143 LaneBitmask(0x0000000F), 7144 0, 7145 true, /* HasDisjunctSubRegs */ 7146 false, /* CoveredBySubRegs */ 7147 GR64_NOREXSuperclasses, 7148 nullptr 7149 }; 7150 7151 extern const TargetRegisterClass GR64_TCW64RegClass = { 7152 &X86MCRegisterClasses[GR64_TCW64RegClassID], 7153 GR64_TCW64SubClassMask, 7154 SuperRegIdxSeqs + 1, 7155 LaneBitmask(0x0000000F), 7156 0, 7157 true, /* HasDisjunctSubRegs */ 7158 false, /* CoveredBySubRegs */ 7159 GR64_TCW64Superclasses, 7160 nullptr 7161 }; 7162 7163 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = { 7164 &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID], 7165 GR64_TC_with_sub_8bitSubClassMask, 7166 SuperRegIdxSeqs + 1, 7167 LaneBitmask(0x0000000F), 7168 0, 7169 true, /* HasDisjunctSubRegs */ 7170 false, /* CoveredBySubRegs */ 7171 GR64_TC_with_sub_8bitSuperclasses, 7172 nullptr 7173 }; 7174 7175 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass = { 7176 &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCRegClassID], 7177 GR64_NOSP_and_GR64_TCSubClassMask, 7178 SuperRegIdxSeqs + 1, 7179 LaneBitmask(0x0000000F), 7180 0, 7181 true, /* HasDisjunctSubRegs */ 7182 false, /* CoveredBySubRegs */ 7183 GR64_NOSP_and_GR64_TCSuperclasses, 7184 nullptr 7185 }; 7186 7187 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = { 7188 &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID], 7189 GR64_TCW64_with_sub_8bitSubClassMask, 7190 SuperRegIdxSeqs + 1, 7191 LaneBitmask(0x0000000F), 7192 0, 7193 true, /* HasDisjunctSubRegs */ 7194 false, /* CoveredBySubRegs */ 7195 GR64_TCW64_with_sub_8bitSuperclasses, 7196 nullptr 7197 }; 7198 7199 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = { 7200 &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID], 7201 GR64_TC_and_GR64_TCW64SubClassMask, 7202 SuperRegIdxSeqs + 1, 7203 LaneBitmask(0x0000000F), 7204 0, 7205 true, /* HasDisjunctSubRegs */ 7206 false, /* CoveredBySubRegs */ 7207 GR64_TC_and_GR64_TCW64Superclasses, 7208 nullptr 7209 }; 7210 7211 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = { 7212 &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID], 7213 GR64_with_sub_16bit_in_GR16_NOREXSubClassMask, 7214 SuperRegIdxSeqs + 1, 7215 LaneBitmask(0x0000000F), 7216 0, 7217 true, /* HasDisjunctSubRegs */ 7218 false, /* CoveredBySubRegs */ 7219 GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 7220 nullptr 7221 }; 7222 7223 extern const TargetRegisterClass VK64RegClass = { 7224 &X86MCRegisterClasses[VK64RegClassID], 7225 VK64SubClassMask, 7226 SuperRegIdxSeqs + 9, 7227 LaneBitmask(0x00000001), 7228 0, 7229 false, /* HasDisjunctSubRegs */ 7230 false, /* CoveredBySubRegs */ 7231 VK64Superclasses, 7232 nullptr 7233 }; 7234 7235 extern const TargetRegisterClass VR64RegClass = { 7236 &X86MCRegisterClasses[VR64RegClassID], 7237 VR64SubClassMask, 7238 SuperRegIdxSeqs + 1, 7239 LaneBitmask(0x00000001), 7240 0, 7241 false, /* HasDisjunctSubRegs */ 7242 false, /* CoveredBySubRegs */ 7243 NullRegClasses, 7244 nullptr 7245 }; 7246 7247 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = { 7248 &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID], 7249 GR64_NOREX_NOSPSubClassMask, 7250 SuperRegIdxSeqs + 1, 7251 LaneBitmask(0x0000000F), 7252 0, 7253 true, /* HasDisjunctSubRegs */ 7254 false, /* CoveredBySubRegs */ 7255 GR64_NOREX_NOSPSuperclasses, 7256 nullptr 7257 }; 7258 7259 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = { 7260 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID], 7261 GR64_NOREX_and_GR64_TCSubClassMask, 7262 SuperRegIdxSeqs + 1, 7263 LaneBitmask(0x0000000F), 7264 0, 7265 true, /* HasDisjunctSubRegs */ 7266 false, /* CoveredBySubRegs */ 7267 GR64_NOREX_and_GR64_TCSuperclasses, 7268 nullptr 7269 }; 7270 7271 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass = { 7272 &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCW64RegClassID], 7273 GR64_NOSP_and_GR64_TCW64SubClassMask, 7274 SuperRegIdxSeqs + 1, 7275 LaneBitmask(0x0000000F), 7276 0, 7277 true, /* HasDisjunctSubRegs */ 7278 false, /* CoveredBySubRegs */ 7279 GR64_NOSP_and_GR64_TCW64Superclasses, 7280 nullptr 7281 }; 7282 7283 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = { 7284 &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID], 7285 GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask, 7286 SuperRegIdxSeqs + 1, 7287 LaneBitmask(0x0000000F), 7288 0, 7289 true, /* HasDisjunctSubRegs */ 7290 false, /* CoveredBySubRegs */ 7291 GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, 7292 nullptr 7293 }; 7294 7295 extern const TargetRegisterClass VK64WMRegClass = { 7296 &X86MCRegisterClasses[VK64WMRegClassID], 7297 VK64WMSubClassMask, 7298 SuperRegIdxSeqs + 9, 7299 LaneBitmask(0x00000001), 7300 0, 7301 false, /* HasDisjunctSubRegs */ 7302 false, /* CoveredBySubRegs */ 7303 VK64WMSuperclasses, 7304 nullptr 7305 }; 7306 7307 extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass = { 7308 &X86MCRegisterClasses[GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID], 7309 GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask, 7310 SuperRegIdxSeqs + 1, 7311 LaneBitmask(0x0000000F), 7312 0, 7313 true, /* HasDisjunctSubRegs */ 7314 false, /* CoveredBySubRegs */ 7315 GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses, 7316 nullptr 7317 }; 7318 7319 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = { 7320 &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID], 7321 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask, 7322 SuperRegIdxSeqs + 1, 7323 LaneBitmask(0x0000000F), 7324 0, 7325 true, /* HasDisjunctSubRegs */ 7326 false, /* CoveredBySubRegs */ 7327 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 7328 nullptr 7329 }; 7330 7331 extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass = { 7332 &X86MCRegisterClasses[GR64_NOREX_NOSP_and_GR64_TCRegClassID], 7333 GR64_NOREX_NOSP_and_GR64_TCSubClassMask, 7334 SuperRegIdxSeqs + 1, 7335 LaneBitmask(0x0000000F), 7336 0, 7337 true, /* HasDisjunctSubRegs */ 7338 false, /* CoveredBySubRegs */ 7339 GR64_NOREX_NOSP_and_GR64_TCSuperclasses, 7340 nullptr 7341 }; 7342 7343 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = { 7344 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID], 7345 GR64_NOREX_and_GR64_TCW64SubClassMask, 7346 SuperRegIdxSeqs + 1, 7347 LaneBitmask(0x0000000F), 7348 0, 7349 true, /* HasDisjunctSubRegs */ 7350 false, /* CoveredBySubRegs */ 7351 GR64_NOREX_and_GR64_TCW64Superclasses, 7352 nullptr 7353 }; 7354 7355 extern const TargetRegisterClass GR64_ABCDRegClass = { 7356 &X86MCRegisterClasses[GR64_ABCDRegClassID], 7357 GR64_ABCDSubClassMask, 7358 SuperRegIdxSeqs + 1, 7359 LaneBitmask(0x0000000F), 7360 0, 7361 true, /* HasDisjunctSubRegs */ 7362 false, /* CoveredBySubRegs */ 7363 GR64_ABCDSuperclasses, 7364 nullptr 7365 }; 7366 7367 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = { 7368 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID], 7369 GR64_with_sub_32bit_in_GR32_TCSubClassMask, 7370 SuperRegIdxSeqs + 1, 7371 LaneBitmask(0x0000000F), 7372 0, 7373 true, /* HasDisjunctSubRegs */ 7374 false, /* CoveredBySubRegs */ 7375 GR64_with_sub_32bit_in_GR32_TCSuperclasses, 7376 nullptr 7377 }; 7378 7379 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = { 7380 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID], 7381 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask, 7382 SuperRegIdxSeqs + 1, 7383 LaneBitmask(0x0000000F), 7384 0, 7385 true, /* HasDisjunctSubRegs */ 7386 false, /* CoveredBySubRegs */ 7387 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, 7388 nullptr 7389 }; 7390 7391 extern const TargetRegisterClass GR64_ADRegClass = { 7392 &X86MCRegisterClasses[GR64_ADRegClassID], 7393 GR64_ADSubClassMask, 7394 SuperRegIdxSeqs + 1, 7395 LaneBitmask(0x0000000F), 7396 0, 7397 true, /* HasDisjunctSubRegs */ 7398 false, /* CoveredBySubRegs */ 7399 GR64_ADSuperclasses, 7400 nullptr 7401 }; 7402 7403 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = { 7404 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID], 7405 GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask, 7406 SuperRegIdxSeqs + 1, 7407 LaneBitmask(0x0000000F), 7408 0, 7409 true, /* HasDisjunctSubRegs */ 7410 false, /* CoveredBySubRegs */ 7411 GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, 7412 nullptr 7413 }; 7414 7415 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = { 7416 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID], 7417 GR64_with_sub_32bit_in_GR32_BPSPSubClassMask, 7418 SuperRegIdxSeqs + 1, 7419 LaneBitmask(0x0000000F), 7420 0, 7421 true, /* HasDisjunctSubRegs */ 7422 false, /* CoveredBySubRegs */ 7423 GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, 7424 nullptr 7425 }; 7426 7427 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = { 7428 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID], 7429 GR64_with_sub_32bit_in_GR32_BSISubClassMask, 7430 SuperRegIdxSeqs + 1, 7431 LaneBitmask(0x0000000F), 7432 0, 7433 true, /* HasDisjunctSubRegs */ 7434 false, /* CoveredBySubRegs */ 7435 GR64_with_sub_32bit_in_GR32_BSISuperclasses, 7436 nullptr 7437 }; 7438 7439 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = { 7440 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID], 7441 GR64_with_sub_32bit_in_GR32_CBSubClassMask, 7442 SuperRegIdxSeqs + 1, 7443 LaneBitmask(0x0000000F), 7444 0, 7445 true, /* HasDisjunctSubRegs */ 7446 false, /* CoveredBySubRegs */ 7447 GR64_with_sub_32bit_in_GR32_CBSuperclasses, 7448 nullptr 7449 }; 7450 7451 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass = { 7452 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DCRegClassID], 7453 GR64_with_sub_32bit_in_GR32_DCSubClassMask, 7454 SuperRegIdxSeqs + 1, 7455 LaneBitmask(0x0000000F), 7456 0, 7457 true, /* HasDisjunctSubRegs */ 7458 false, /* CoveredBySubRegs */ 7459 GR64_with_sub_32bit_in_GR32_DCSuperclasses, 7460 nullptr 7461 }; 7462 7463 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = { 7464 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID], 7465 GR64_with_sub_32bit_in_GR32_DIBPSubClassMask, 7466 SuperRegIdxSeqs + 1, 7467 LaneBitmask(0x0000000F), 7468 0, 7469 true, /* HasDisjunctSubRegs */ 7470 false, /* CoveredBySubRegs */ 7471 GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, 7472 nullptr 7473 }; 7474 7475 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = { 7476 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID], 7477 GR64_with_sub_32bit_in_GR32_SIDISubClassMask, 7478 SuperRegIdxSeqs + 1, 7479 LaneBitmask(0x0000000F), 7480 0, 7481 true, /* HasDisjunctSubRegs */ 7482 false, /* CoveredBySubRegs */ 7483 GR64_with_sub_32bit_in_GR32_SIDISuperclasses, 7484 nullptr 7485 }; 7486 7487 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = { 7488 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID], 7489 GR64_and_LOW32_ADDR_ACCESSSubClassMask, 7490 SuperRegIdxSeqs + 1, 7491 LaneBitmask(0x0000000F), 7492 0, 7493 true, /* HasDisjunctSubRegs */ 7494 false, /* CoveredBySubRegs */ 7495 GR64_and_LOW32_ADDR_ACCESSSuperclasses, 7496 nullptr 7497 }; 7498 7499 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = { 7500 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID], 7501 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask, 7502 SuperRegIdxSeqs + 1, 7503 LaneBitmask(0x0000000F), 7504 0, 7505 true, /* HasDisjunctSubRegs */ 7506 false, /* CoveredBySubRegs */ 7507 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, 7508 nullptr 7509 }; 7510 7511 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass = { 7512 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID], 7513 GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask, 7514 SuperRegIdxSeqs + 1, 7515 LaneBitmask(0x0000000F), 7516 0, 7517 true, /* HasDisjunctSubRegs */ 7518 false, /* CoveredBySubRegs */ 7519 GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses, 7520 nullptr 7521 }; 7522 7523 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = { 7524 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID], 7525 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask, 7526 SuperRegIdxSeqs + 1, 7527 LaneBitmask(0x0000000F), 7528 0, 7529 true, /* HasDisjunctSubRegs */ 7530 false, /* CoveredBySubRegs */ 7531 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, 7532 nullptr 7533 }; 7534 7535 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = { 7536 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID], 7537 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask, 7538 SuperRegIdxSeqs + 1, 7539 LaneBitmask(0x0000000F), 7540 0, 7541 true, /* HasDisjunctSubRegs */ 7542 false, /* CoveredBySubRegs */ 7543 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, 7544 nullptr 7545 }; 7546 7547 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = { 7548 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID], 7549 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask, 7550 SuperRegIdxSeqs + 1, 7551 LaneBitmask(0x0000000F), 7552 0, 7553 true, /* HasDisjunctSubRegs */ 7554 false, /* CoveredBySubRegs */ 7555 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, 7556 nullptr 7557 }; 7558 7559 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass = { 7560 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID], 7561 GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask, 7562 SuperRegIdxSeqs + 1, 7563 LaneBitmask(0x0000000F), 7564 0, 7565 true, /* HasDisjunctSubRegs */ 7566 false, /* CoveredBySubRegs */ 7567 GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses, 7568 nullptr 7569 }; 7570 7571 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = { 7572 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID], 7573 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask, 7574 SuperRegIdxSeqs + 1, 7575 LaneBitmask(0x0000000F), 7576 0, 7577 true, /* HasDisjunctSubRegs */ 7578 false, /* CoveredBySubRegs */ 7579 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, 7580 nullptr 7581 }; 7582 7583 extern const TargetRegisterClass RSTRegClass = { 7584 &X86MCRegisterClasses[RSTRegClassID], 7585 RSTSubClassMask, 7586 SuperRegIdxSeqs + 1, 7587 LaneBitmask(0x00000001), 7588 0, 7589 false, /* HasDisjunctSubRegs */ 7590 false, /* CoveredBySubRegs */ 7591 NullRegClasses, 7592 nullptr 7593 }; 7594 7595 extern const TargetRegisterClass RFP80RegClass = { 7596 &X86MCRegisterClasses[RFP80RegClassID], 7597 RFP80SubClassMask, 7598 SuperRegIdxSeqs + 1, 7599 LaneBitmask(0x00000001), 7600 0, 7601 false, /* HasDisjunctSubRegs */ 7602 false, /* CoveredBySubRegs */ 7603 RFP80Superclasses, 7604 nullptr 7605 }; 7606 7607 extern const TargetRegisterClass RFP80_7RegClass = { 7608 &X86MCRegisterClasses[RFP80_7RegClassID], 7609 RFP80_7SubClassMask, 7610 SuperRegIdxSeqs + 1, 7611 LaneBitmask(0x00000001), 7612 0, 7613 false, /* HasDisjunctSubRegs */ 7614 false, /* CoveredBySubRegs */ 7615 NullRegClasses, 7616 nullptr 7617 }; 7618 7619 extern const TargetRegisterClass VR128XRegClass = { 7620 &X86MCRegisterClasses[VR128XRegClassID], 7621 VR128XSubClassMask, 7622 SuperRegIdxSeqs + 12, 7623 LaneBitmask(0x00000001), 7624 0, 7625 false, /* HasDisjunctSubRegs */ 7626 false, /* CoveredBySubRegs */ 7627 VR128XSuperclasses, 7628 nullptr 7629 }; 7630 7631 extern const TargetRegisterClass VR128RegClass = { 7632 &X86MCRegisterClasses[VR128RegClassID], 7633 VR128SubClassMask, 7634 SuperRegIdxSeqs + 12, 7635 LaneBitmask(0x00000001), 7636 0, 7637 false, /* HasDisjunctSubRegs */ 7638 false, /* CoveredBySubRegs */ 7639 VR128Superclasses, 7640 nullptr 7641 }; 7642 7643 extern const TargetRegisterClass BNDRRegClass = { 7644 &X86MCRegisterClasses[BNDRRegClassID], 7645 BNDRSubClassMask, 7646 SuperRegIdxSeqs + 1, 7647 LaneBitmask(0x00000001), 7648 0, 7649 false, /* HasDisjunctSubRegs */ 7650 false, /* CoveredBySubRegs */ 7651 NullRegClasses, 7652 nullptr 7653 }; 7654 7655 extern const TargetRegisterClass VR256XRegClass = { 7656 &X86MCRegisterClasses[VR256XRegClassID], 7657 VR256XSubClassMask, 7658 SuperRegIdxSeqs + 14, 7659 LaneBitmask(0x00000040), 7660 0, 7661 false, /* HasDisjunctSubRegs */ 7662 false, /* CoveredBySubRegs */ 7663 NullRegClasses, 7664 nullptr 7665 }; 7666 7667 extern const TargetRegisterClass VR256RegClass = { 7668 &X86MCRegisterClasses[VR256RegClassID], 7669 VR256SubClassMask, 7670 SuperRegIdxSeqs + 14, 7671 LaneBitmask(0x00000040), 7672 0, 7673 false, /* HasDisjunctSubRegs */ 7674 false, /* CoveredBySubRegs */ 7675 VR256Superclasses, 7676 nullptr 7677 }; 7678 7679 extern const TargetRegisterClass VR512RegClass = { 7680 &X86MCRegisterClasses[VR512RegClassID], 7681 VR512SubClassMask, 7682 SuperRegIdxSeqs + 1, 7683 LaneBitmask(0x00000040), 7684 0, 7685 false, /* HasDisjunctSubRegs */ 7686 false, /* CoveredBySubRegs */ 7687 NullRegClasses, 7688 nullptr 7689 }; 7690 7691 extern const TargetRegisterClass VR512_0_15RegClass = { 7692 &X86MCRegisterClasses[VR512_0_15RegClassID], 7693 VR512_0_15SubClassMask, 7694 SuperRegIdxSeqs + 1, 7695 LaneBitmask(0x00000040), 7696 0, 7697 false, /* HasDisjunctSubRegs */ 7698 false, /* CoveredBySubRegs */ 7699 VR512_0_15Superclasses, 7700 nullptr 7701 }; 7702 7703} // end namespace X86 7704 7705namespace { 7706 const TargetRegisterClass* const RegisterClasses[] = { 7707 &X86::GR8RegClass, 7708 &X86::GRH8RegClass, 7709 &X86::GR8_NOREXRegClass, 7710 &X86::GR8_ABCD_HRegClass, 7711 &X86::GR8_ABCD_LRegClass, 7712 &X86::GRH16RegClass, 7713 &X86::GR16RegClass, 7714 &X86::GR16_NOREXRegClass, 7715 &X86::VK1RegClass, 7716 &X86::VK16RegClass, 7717 &X86::VK2RegClass, 7718 &X86::VK4RegClass, 7719 &X86::VK8RegClass, 7720 &X86::VK16WMRegClass, 7721 &X86::VK1WMRegClass, 7722 &X86::VK2WMRegClass, 7723 &X86::VK4WMRegClass, 7724 &X86::VK8WMRegClass, 7725 &X86::SEGMENT_REGRegClass, 7726 &X86::GR16_ABCDRegClass, 7727 &X86::FPCCRRegClass, 7728 &X86::VK16PAIRRegClass, 7729 &X86::VK1PAIRRegClass, 7730 &X86::VK2PAIRRegClass, 7731 &X86::VK4PAIRRegClass, 7732 &X86::VK8PAIRRegClass, 7733 &X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClass, 7734 &X86::FR32XRegClass, 7735 &X86::LOW32_ADDR_ACCESS_RBPRegClass, 7736 &X86::LOW32_ADDR_ACCESSRegClass, 7737 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass, 7738 &X86::DEBUG_REGRegClass, 7739 &X86::FR32RegClass, 7740 &X86::GR32RegClass, 7741 &X86::GR32_NOSPRegClass, 7742 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass, 7743 &X86::GR32_NOREXRegClass, 7744 &X86::VK32RegClass, 7745 &X86::GR32_NOREX_NOSPRegClass, 7746 &X86::RFP32RegClass, 7747 &X86::VK32WMRegClass, 7748 &X86::GR32_ABCDRegClass, 7749 &X86::GR32_TCRegClass, 7750 &X86::GR32_ABCD_and_GR32_TCRegClass, 7751 &X86::GR32_ADRegClass, 7752 &X86::GR32_BPSPRegClass, 7753 &X86::GR32_BSIRegClass, 7754 &X86::GR32_CBRegClass, 7755 &X86::GR32_DCRegClass, 7756 &X86::GR32_DIBPRegClass, 7757 &X86::GR32_SIDIRegClass, 7758 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass, 7759 &X86::CCRRegClass, 7760 &X86::DFCCRRegClass, 7761 &X86::GR32_ABCD_and_GR32_BSIRegClass, 7762 &X86::GR32_AD_and_GR32_DCRegClass, 7763 &X86::GR32_BPSP_and_GR32_DIBPRegClass, 7764 &X86::GR32_BPSP_and_GR32_TCRegClass, 7765 &X86::GR32_BSI_and_GR32_SIDIRegClass, 7766 &X86::GR32_CB_and_GR32_DCRegClass, 7767 &X86::GR32_DIBP_and_GR32_SIDIRegClass, 7768 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass, 7769 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass, 7770 &X86::RFP64RegClass, 7771 &X86::FR64XRegClass, 7772 &X86::GR64RegClass, 7773 &X86::CONTROL_REGRegClass, 7774 &X86::FR64RegClass, 7775 &X86::GR64_with_sub_8bitRegClass, 7776 &X86::GR64_NOSPRegClass, 7777 &X86::GR64_TCRegClass, 7778 &X86::GR64_NOREXRegClass, 7779 &X86::GR64_TCW64RegClass, 7780 &X86::GR64_TC_with_sub_8bitRegClass, 7781 &X86::GR64_NOSP_and_GR64_TCRegClass, 7782 &X86::GR64_TCW64_with_sub_8bitRegClass, 7783 &X86::GR64_TC_and_GR64_TCW64RegClass, 7784 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass, 7785 &X86::VK64RegClass, 7786 &X86::VR64RegClass, 7787 &X86::GR64_NOREX_NOSPRegClass, 7788 &X86::GR64_NOREX_and_GR64_TCRegClass, 7789 &X86::GR64_NOSP_and_GR64_TCW64RegClass, 7790 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass, 7791 &X86::VK64WMRegClass, 7792 &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass, 7793 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass, 7794 &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass, 7795 &X86::GR64_NOREX_and_GR64_TCW64RegClass, 7796 &X86::GR64_ABCDRegClass, 7797 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass, 7798 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass, 7799 &X86::GR64_ADRegClass, 7800 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass, 7801 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass, 7802 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass, 7803 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass, 7804 &X86::GR64_with_sub_32bit_in_GR32_DCRegClass, 7805 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass, 7806 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass, 7807 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass, 7808 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass, 7809 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass, 7810 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass, 7811 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass, 7812 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass, 7813 &X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass, 7814 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass, 7815 &X86::RSTRegClass, 7816 &X86::RFP80RegClass, 7817 &X86::RFP80_7RegClass, 7818 &X86::VR128XRegClass, 7819 &X86::VR128RegClass, 7820 &X86::BNDRRegClass, 7821 &X86::VR256XRegClass, 7822 &X86::VR256RegClass, 7823 &X86::VR512RegClass, 7824 &X86::VR512_0_15RegClass, 7825 }; 7826} // end anonymous namespace 7827 7828static const TargetRegisterInfoDesc X86RegInfoDesc[] = { // Extra Descriptors 7829 { 0, false }, 7830 { 0, true }, 7831 { 0, true }, 7832 { 0, true }, 7833 { 0, true }, 7834 { 0, true }, 7835 { 0, true }, 7836 { 0, false }, 7837 { 1, true }, 7838 { 0, true }, 7839 { 0, true }, 7840 { 0, true }, 7841 { 0, true }, 7842 { 0, true }, 7843 { 0, false }, 7844 { 0, true }, 7845 { 0, true }, 7846 { 0, false }, 7847 { 1, true }, 7848 { 0, true }, 7849 { 0, true }, 7850 { 0, true }, 7851 { 0, true }, 7852 { 0, true }, 7853 { 0, true }, 7854 { 0, true }, 7855 { 0, true }, 7856 { 0, true }, 7857 { 0, false }, 7858 { 0, false }, 7859 { 0, false }, 7860 { 0, true }, 7861 { 0, true }, 7862 { 0, true }, 7863 { 0, false }, 7864 { 0, false }, 7865 { 0, true }, 7866 { 0, true }, 7867 { 0, false }, 7868 { 0, false }, 7869 { 0, false }, 7870 { 0, false }, 7871 { 0, false }, 7872 { 0, false }, 7873 { 0, false }, 7874 { 0, false }, 7875 { 0, false }, 7876 { 0, false }, 7877 { 0, false }, 7878 { 0, true }, 7879 { 0, true }, 7880 { 0, true }, 7881 { 0, true }, 7882 { 0, true }, 7883 { 0, true }, 7884 { 1, true }, 7885 { 0, false }, 7886 { 0, true }, 7887 { 0, true }, 7888 { 0, true }, 7889 { 0, false }, 7890 { 1, true }, 7891 { 0, true }, 7892 { 0, false }, 7893 { 1, true }, 7894 { 0, true }, 7895 { 0, false }, 7896 { 0, true }, 7897 { 0, true }, 7898 { 0, true }, 7899 { 0, true }, 7900 { 0, true }, 7901 { 0, true }, 7902 { 0, true }, 7903 { 0, true }, 7904 { 0, true }, 7905 { 0, true }, 7906 { 0, true }, 7907 { 0, true }, 7908 { 0, true }, 7909 { 0, true }, 7910 { 0, true }, 7911 { 0, true }, 7912 { 0, true }, 7913 { 0, true }, 7914 { 0, true }, 7915 { 0, true }, 7916 { 0, true }, 7917 { 0, true }, 7918 { 0, true }, 7919 { 0, true }, 7920 { 0, true }, 7921 { 0, true }, 7922 { 0, true }, 7923 { 0, true }, 7924 { 0, true }, 7925 { 0, true }, 7926 { 0, true }, 7927 { 0, true }, 7928 { 0, true }, 7929 { 0, true }, 7930 { 0, true }, 7931 { 0, true }, 7932 { 0, true }, 7933 { 0, true }, 7934 { 0, true }, 7935 { 0, true }, 7936 { 0, true }, 7937 { 0, true }, 7938 { 0, true }, 7939 { 0, false }, 7940 { 0, true }, 7941 { 0, true }, 7942 { 0, true }, 7943 { 0, true }, 7944 { 0, true }, 7945 { 0, true }, 7946 { 0, true }, 7947 { 0, true }, 7948 { 0, true }, 7949 { 0, true }, 7950 { 0, true }, 7951 { 0, true }, 7952 { 0, true }, 7953 { 0, true }, 7954 { 0, true }, 7955 { 0, true }, 7956 { 1, true }, 7957 { 1, true }, 7958 { 1, true }, 7959 { 1, true }, 7960 { 1, true }, 7961 { 1, true }, 7962 { 1, true }, 7963 { 1, true }, 7964 { 0, false }, 7965 { 0, false }, 7966 { 0, false }, 7967 { 0, false }, 7968 { 0, false }, 7969 { 0, false }, 7970 { 0, false }, 7971 { 0, false }, 7972 { 0, true }, 7973 { 0, true }, 7974 { 0, true }, 7975 { 0, true }, 7976 { 0, true }, 7977 { 0, true }, 7978 { 0, true }, 7979 { 0, true }, 7980 { 1, true }, 7981 { 1, true }, 7982 { 1, true }, 7983 { 1, true }, 7984 { 1, true }, 7985 { 1, true }, 7986 { 1, true }, 7987 { 1, true }, 7988 { 1, true }, 7989 { 1, true }, 7990 { 1, true }, 7991 { 1, true }, 7992 { 1, true }, 7993 { 1, true }, 7994 { 1, true }, 7995 { 1, true }, 7996 { 1, true }, 7997 { 1, true }, 7998 { 1, true }, 7999 { 1, true }, 8000 { 1, true }, 8001 { 1, true }, 8002 { 1, true }, 8003 { 1, true }, 8004 { 0, true }, 8005 { 0, true }, 8006 { 0, true }, 8007 { 0, true }, 8008 { 0, true }, 8009 { 0, true }, 8010 { 0, true }, 8011 { 0, true }, 8012 { 0, true }, 8013 { 0, true }, 8014 { 0, true }, 8015 { 0, true }, 8016 { 0, true }, 8017 { 0, true }, 8018 { 0, true }, 8019 { 0, true }, 8020 { 0, true }, 8021 { 0, true }, 8022 { 0, true }, 8023 { 0, true }, 8024 { 0, true }, 8025 { 0, true }, 8026 { 0, true }, 8027 { 0, true }, 8028 { 0, true }, 8029 { 0, true }, 8030 { 0, true }, 8031 { 0, true }, 8032 { 0, true }, 8033 { 0, true }, 8034 { 0, true }, 8035 { 0, true }, 8036 { 0, true }, 8037 { 0, true }, 8038 { 0, true }, 8039 { 0, true }, 8040 { 0, true }, 8041 { 0, true }, 8042 { 0, true }, 8043 { 0, true }, 8044 { 0, true }, 8045 { 0, true }, 8046 { 0, true }, 8047 { 0, true }, 8048 { 0, true }, 8049 { 0, true }, 8050 { 0, true }, 8051 { 0, true }, 8052 { 0, true }, 8053 { 0, true }, 8054 { 0, true }, 8055 { 0, true }, 8056 { 0, true }, 8057 { 0, true }, 8058 { 0, true }, 8059 { 0, true }, 8060 { 0, true }, 8061 { 0, true }, 8062 { 0, true }, 8063 { 0, true }, 8064 { 0, true }, 8065 { 0, true }, 8066 { 0, true }, 8067 { 0, true }, 8068 { 1, true }, 8069 { 1, true }, 8070 { 1, true }, 8071 { 1, true }, 8072 { 1, true }, 8073 { 1, true }, 8074 { 1, true }, 8075 { 1, true }, 8076 { 0, false }, 8077 { 0, false }, 8078 { 0, false }, 8079 { 0, false }, 8080 { 0, false }, 8081 { 0, false }, 8082 { 0, false }, 8083 { 0, false }, 8084 { 1, true }, 8085 { 1, true }, 8086 { 1, true }, 8087 { 1, true }, 8088 { 1, true }, 8089 { 1, true }, 8090 { 1, true }, 8091 { 1, true }, 8092 { 1, true }, 8093 { 1, true }, 8094 { 1, true }, 8095 { 1, true }, 8096 { 1, true }, 8097 { 1, true }, 8098 { 1, true }, 8099 { 1, true }, 8100 { 0, false }, 8101 { 0, false }, 8102 { 0, false }, 8103 { 0, false }, 8104 { 0, false }, 8105 { 0, false }, 8106 { 0, false }, 8107 { 0, false }, 8108 { 0, true }, 8109 { 0, true }, 8110 { 0, true }, 8111 { 0, true }, 8112}; 8113unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { 8114 static const uint8_t Rows[1][10] = { 8115 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, }, 8116 }; 8117 8118 --IdxA; assert(IdxA < 10); 8119 --IdxB; assert(IdxB < 10); 8120 return Rows[0][IdxB]; 8121} 8122 8123 struct MaskRolOp { 8124 LaneBitmask Mask; 8125 uint8_t RotateLeft; 8126 }; 8127 static const MaskRolOp LaneMaskComposeSequences[] = { 8128 { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 8129 { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 8130 { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 8131 { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 8132 { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 8133 { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 8134 { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12 8135 }; 8136 static const MaskRolOp *const CompositeSequences[] = { 8137 &LaneMaskComposeSequences[0], // to sub_8bit 8138 &LaneMaskComposeSequences[2], // to sub_8bit_hi 8139 &LaneMaskComposeSequences[4], // to sub_8bit_hi_phony 8140 &LaneMaskComposeSequences[0], // to sub_16bit 8141 &LaneMaskComposeSequences[6], // to sub_16bit_hi 8142 &LaneMaskComposeSequences[0], // to sub_32bit 8143 &LaneMaskComposeSequences[8], // to sub_mask_0 8144 &LaneMaskComposeSequences[10], // to sub_mask_1 8145 &LaneMaskComposeSequences[12], // to sub_xmm 8146 &LaneMaskComposeSequences[0] // to sub_ymm 8147 }; 8148 8149LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 8150 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds"); 8151 LaneBitmask Result; 8152 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 8153 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); 8154 if (unsigned S = Ops->RotateLeft) 8155 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); 8156 else 8157 Result |= LaneBitmask(M); 8158 } 8159 return Result; 8160} 8161 8162LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 8163 LaneMask &= getSubRegIndexLaneMask(IdxA); 8164 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds"); 8165 LaneBitmask Result; 8166 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 8167 LaneBitmask::Type M = LaneMask.getAsInteger(); 8168 if (unsigned S = Ops->RotateLeft) 8169 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); 8170 else 8171 Result |= LaneBitmask(M); 8172 } 8173 return Result; 8174} 8175 8176const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 8177 static const uint8_t Table[118][10] = { 8178 { // GR8 8179 0, // sub_8bit 8180 0, // sub_8bit_hi 8181 0, // sub_8bit_hi_phony 8182 0, // sub_16bit 8183 0, // sub_16bit_hi 8184 0, // sub_32bit 8185 0, // sub_mask_0 8186 0, // sub_mask_1 8187 0, // sub_xmm 8188 0, // sub_ymm 8189 }, 8190 { // GRH8 8191 0, // sub_8bit 8192 0, // sub_8bit_hi 8193 0, // sub_8bit_hi_phony 8194 0, // sub_16bit 8195 0, // sub_16bit_hi 8196 0, // sub_32bit 8197 0, // sub_mask_0 8198 0, // sub_mask_1 8199 0, // sub_xmm 8200 0, // sub_ymm 8201 }, 8202 { // GR8_NOREX 8203 0, // sub_8bit 8204 0, // sub_8bit_hi 8205 0, // sub_8bit_hi_phony 8206 0, // sub_16bit 8207 0, // sub_16bit_hi 8208 0, // sub_32bit 8209 0, // sub_mask_0 8210 0, // sub_mask_1 8211 0, // sub_xmm 8212 0, // sub_ymm 8213 }, 8214 { // GR8_ABCD_H 8215 0, // sub_8bit 8216 0, // sub_8bit_hi 8217 0, // sub_8bit_hi_phony 8218 0, // sub_16bit 8219 0, // sub_16bit_hi 8220 0, // sub_32bit 8221 0, // sub_mask_0 8222 0, // sub_mask_1 8223 0, // sub_xmm 8224 0, // sub_ymm 8225 }, 8226 { // GR8_ABCD_L 8227 0, // sub_8bit 8228 0, // sub_8bit_hi 8229 0, // sub_8bit_hi_phony 8230 0, // sub_16bit 8231 0, // sub_16bit_hi 8232 0, // sub_32bit 8233 0, // sub_mask_0 8234 0, // sub_mask_1 8235 0, // sub_xmm 8236 0, // sub_ymm 8237 }, 8238 { // GRH16 8239 0, // sub_8bit 8240 0, // sub_8bit_hi 8241 0, // sub_8bit_hi_phony 8242 0, // sub_16bit 8243 0, // sub_16bit_hi 8244 0, // sub_32bit 8245 0, // sub_mask_0 8246 0, // sub_mask_1 8247 0, // sub_xmm 8248 0, // sub_ymm 8249 }, 8250 { // GR16 8251 7, // sub_8bit -> GR16 8252 20, // sub_8bit_hi -> GR16_ABCD 8253 0, // sub_8bit_hi_phony 8254 0, // sub_16bit 8255 0, // sub_16bit_hi 8256 0, // sub_32bit 8257 0, // sub_mask_0 8258 0, // sub_mask_1 8259 0, // sub_xmm 8260 0, // sub_ymm 8261 }, 8262 { // GR16_NOREX 8263 8, // sub_8bit -> GR16_NOREX 8264 20, // sub_8bit_hi -> GR16_ABCD 8265 0, // sub_8bit_hi_phony 8266 0, // sub_16bit 8267 0, // sub_16bit_hi 8268 0, // sub_32bit 8269 0, // sub_mask_0 8270 0, // sub_mask_1 8271 0, // sub_xmm 8272 0, // sub_ymm 8273 }, 8274 { // VK1 8275 0, // sub_8bit 8276 0, // sub_8bit_hi 8277 0, // sub_8bit_hi_phony 8278 0, // sub_16bit 8279 0, // sub_16bit_hi 8280 0, // sub_32bit 8281 0, // sub_mask_0 8282 0, // sub_mask_1 8283 0, // sub_xmm 8284 0, // sub_ymm 8285 }, 8286 { // VK16 8287 0, // sub_8bit 8288 0, // sub_8bit_hi 8289 0, // sub_8bit_hi_phony 8290 0, // sub_16bit 8291 0, // sub_16bit_hi 8292 0, // sub_32bit 8293 0, // sub_mask_0 8294 0, // sub_mask_1 8295 0, // sub_xmm 8296 0, // sub_ymm 8297 }, 8298 { // VK2 8299 0, // sub_8bit 8300 0, // sub_8bit_hi 8301 0, // sub_8bit_hi_phony 8302 0, // sub_16bit 8303 0, // sub_16bit_hi 8304 0, // sub_32bit 8305 0, // sub_mask_0 8306 0, // sub_mask_1 8307 0, // sub_xmm 8308 0, // sub_ymm 8309 }, 8310 { // VK4 8311 0, // sub_8bit 8312 0, // sub_8bit_hi 8313 0, // sub_8bit_hi_phony 8314 0, // sub_16bit 8315 0, // sub_16bit_hi 8316 0, // sub_32bit 8317 0, // sub_mask_0 8318 0, // sub_mask_1 8319 0, // sub_xmm 8320 0, // sub_ymm 8321 }, 8322 { // VK8 8323 0, // sub_8bit 8324 0, // sub_8bit_hi 8325 0, // sub_8bit_hi_phony 8326 0, // sub_16bit 8327 0, // sub_16bit_hi 8328 0, // sub_32bit 8329 0, // sub_mask_0 8330 0, // sub_mask_1 8331 0, // sub_xmm 8332 0, // sub_ymm 8333 }, 8334 { // VK16WM 8335 0, // sub_8bit 8336 0, // sub_8bit_hi 8337 0, // sub_8bit_hi_phony 8338 0, // sub_16bit 8339 0, // sub_16bit_hi 8340 0, // sub_32bit 8341 0, // sub_mask_0 8342 0, // sub_mask_1 8343 0, // sub_xmm 8344 0, // sub_ymm 8345 }, 8346 { // VK1WM 8347 0, // sub_8bit 8348 0, // sub_8bit_hi 8349 0, // sub_8bit_hi_phony 8350 0, // sub_16bit 8351 0, // sub_16bit_hi 8352 0, // sub_32bit 8353 0, // sub_mask_0 8354 0, // sub_mask_1 8355 0, // sub_xmm 8356 0, // sub_ymm 8357 }, 8358 { // VK2WM 8359 0, // sub_8bit 8360 0, // sub_8bit_hi 8361 0, // sub_8bit_hi_phony 8362 0, // sub_16bit 8363 0, // sub_16bit_hi 8364 0, // sub_32bit 8365 0, // sub_mask_0 8366 0, // sub_mask_1 8367 0, // sub_xmm 8368 0, // sub_ymm 8369 }, 8370 { // VK4WM 8371 0, // sub_8bit 8372 0, // sub_8bit_hi 8373 0, // sub_8bit_hi_phony 8374 0, // sub_16bit 8375 0, // sub_16bit_hi 8376 0, // sub_32bit 8377 0, // sub_mask_0 8378 0, // sub_mask_1 8379 0, // sub_xmm 8380 0, // sub_ymm 8381 }, 8382 { // VK8WM 8383 0, // sub_8bit 8384 0, // sub_8bit_hi 8385 0, // sub_8bit_hi_phony 8386 0, // sub_16bit 8387 0, // sub_16bit_hi 8388 0, // sub_32bit 8389 0, // sub_mask_0 8390 0, // sub_mask_1 8391 0, // sub_xmm 8392 0, // sub_ymm 8393 }, 8394 { // SEGMENT_REG 8395 0, // sub_8bit 8396 0, // sub_8bit_hi 8397 0, // sub_8bit_hi_phony 8398 0, // sub_16bit 8399 0, // sub_16bit_hi 8400 0, // sub_32bit 8401 0, // sub_mask_0 8402 0, // sub_mask_1 8403 0, // sub_xmm 8404 0, // sub_ymm 8405 }, 8406 { // GR16_ABCD 8407 20, // sub_8bit -> GR16_ABCD 8408 20, // sub_8bit_hi -> GR16_ABCD 8409 0, // sub_8bit_hi_phony 8410 0, // sub_16bit 8411 0, // sub_16bit_hi 8412 0, // sub_32bit 8413 0, // sub_mask_0 8414 0, // sub_mask_1 8415 0, // sub_xmm 8416 0, // sub_ymm 8417 }, 8418 { // FPCCR 8419 0, // sub_8bit 8420 0, // sub_8bit_hi 8421 0, // sub_8bit_hi_phony 8422 0, // sub_16bit 8423 0, // sub_16bit_hi 8424 0, // sub_32bit 8425 0, // sub_mask_0 8426 0, // sub_mask_1 8427 0, // sub_xmm 8428 0, // sub_ymm 8429 }, 8430 { // VK16PAIR 8431 0, // sub_8bit 8432 0, // sub_8bit_hi 8433 0, // sub_8bit_hi_phony 8434 0, // sub_16bit 8435 0, // sub_16bit_hi 8436 0, // sub_32bit 8437 22, // sub_mask_0 -> VK16PAIR 8438 22, // sub_mask_1 -> VK16PAIR 8439 0, // sub_xmm 8440 0, // sub_ymm 8441 }, 8442 { // VK1PAIR 8443 0, // sub_8bit 8444 0, // sub_8bit_hi 8445 0, // sub_8bit_hi_phony 8446 0, // sub_16bit 8447 0, // sub_16bit_hi 8448 0, // sub_32bit 8449 23, // sub_mask_0 -> VK1PAIR 8450 23, // sub_mask_1 -> VK1PAIR 8451 0, // sub_xmm 8452 0, // sub_ymm 8453 }, 8454 { // VK2PAIR 8455 0, // sub_8bit 8456 0, // sub_8bit_hi 8457 0, // sub_8bit_hi_phony 8458 0, // sub_16bit 8459 0, // sub_16bit_hi 8460 0, // sub_32bit 8461 24, // sub_mask_0 -> VK2PAIR 8462 24, // sub_mask_1 -> VK2PAIR 8463 0, // sub_xmm 8464 0, // sub_ymm 8465 }, 8466 { // VK4PAIR 8467 0, // sub_8bit 8468 0, // sub_8bit_hi 8469 0, // sub_8bit_hi_phony 8470 0, // sub_16bit 8471 0, // sub_16bit_hi 8472 0, // sub_32bit 8473 25, // sub_mask_0 -> VK4PAIR 8474 25, // sub_mask_1 -> VK4PAIR 8475 0, // sub_xmm 8476 0, // sub_ymm 8477 }, 8478 { // VK8PAIR 8479 0, // sub_8bit 8480 0, // sub_8bit_hi 8481 0, // sub_8bit_hi_phony 8482 0, // sub_16bit 8483 0, // sub_16bit_hi 8484 0, // sub_32bit 8485 26, // sub_mask_0 -> VK8PAIR 8486 26, // sub_mask_1 -> VK8PAIR 8487 0, // sub_xmm 8488 0, // sub_ymm 8489 }, 8490 { // VK16PAIR_with_sub_mask_0_in_VK16WM 8491 0, // sub_8bit 8492 0, // sub_8bit_hi 8493 0, // sub_8bit_hi_phony 8494 0, // sub_16bit 8495 0, // sub_16bit_hi 8496 0, // sub_32bit 8497 27, // sub_mask_0 -> VK16PAIR_with_sub_mask_0_in_VK16WM 8498 27, // sub_mask_1 -> VK16PAIR_with_sub_mask_0_in_VK16WM 8499 0, // sub_xmm 8500 0, // sub_ymm 8501 }, 8502 { // FR32X 8503 0, // sub_8bit 8504 0, // sub_8bit_hi 8505 0, // sub_8bit_hi_phony 8506 0, // sub_16bit 8507 0, // sub_16bit_hi 8508 0, // sub_32bit 8509 0, // sub_mask_0 8510 0, // sub_mask_1 8511 0, // sub_xmm 8512 0, // sub_ymm 8513 }, 8514 { // LOW32_ADDR_ACCESS_RBP 8515 31, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit 8516 42, // sub_8bit_hi -> GR32_ABCD 8517 0, // sub_8bit_hi_phony 8518 29, // sub_16bit -> LOW32_ADDR_ACCESS_RBP 8519 0, // sub_16bit_hi 8520 52, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit 8521 0, // sub_mask_0 8522 0, // sub_mask_1 8523 0, // sub_xmm 8524 0, // sub_ymm 8525 }, 8526 { // LOW32_ADDR_ACCESS 8527 34, // sub_8bit -> GR32 8528 42, // sub_8bit_hi -> GR32_ABCD 8529 0, // sub_8bit_hi_phony 8530 30, // sub_16bit -> LOW32_ADDR_ACCESS 8531 0, // sub_16bit_hi 8532 63, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit 8533 0, // sub_mask_0 8534 0, // sub_mask_1 8535 0, // sub_xmm 8536 0, // sub_ymm 8537 }, 8538 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit 8539 31, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit 8540 42, // sub_8bit_hi -> GR32_ABCD 8541 0, // sub_8bit_hi_phony 8542 31, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit 8543 0, // sub_16bit_hi 8544 62, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8545 0, // sub_mask_0 8546 0, // sub_mask_1 8547 0, // sub_xmm 8548 0, // sub_ymm 8549 }, 8550 { // DEBUG_REG 8551 0, // sub_8bit 8552 0, // sub_8bit_hi 8553 0, // sub_8bit_hi_phony 8554 0, // sub_16bit 8555 0, // sub_16bit_hi 8556 0, // sub_32bit 8557 0, // sub_mask_0 8558 0, // sub_mask_1 8559 0, // sub_xmm 8560 0, // sub_ymm 8561 }, 8562 { // FR32 8563 0, // sub_8bit 8564 0, // sub_8bit_hi 8565 0, // sub_8bit_hi_phony 8566 0, // sub_16bit 8567 0, // sub_16bit_hi 8568 0, // sub_32bit 8569 0, // sub_mask_0 8570 0, // sub_mask_1 8571 0, // sub_xmm 8572 0, // sub_ymm 8573 }, 8574 { // GR32 8575 34, // sub_8bit -> GR32 8576 42, // sub_8bit_hi -> GR32_ABCD 8577 0, // sub_8bit_hi_phony 8578 34, // sub_16bit -> GR32 8579 0, // sub_16bit_hi 8580 0, // sub_32bit 8581 0, // sub_mask_0 8582 0, // sub_mask_1 8583 0, // sub_xmm 8584 0, // sub_ymm 8585 }, 8586 { // GR32_NOSP 8587 35, // sub_8bit -> GR32_NOSP 8588 42, // sub_8bit_hi -> GR32_ABCD 8589 0, // sub_8bit_hi_phony 8590 35, // sub_16bit -> GR32_NOSP 8591 0, // sub_16bit_hi 8592 0, // sub_32bit 8593 0, // sub_mask_0 8594 0, // sub_mask_1 8595 0, // sub_xmm 8596 0, // sub_ymm 8597 }, 8598 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 8599 36, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 8600 42, // sub_8bit_hi -> GR32_ABCD 8601 0, // sub_8bit_hi_phony 8602 36, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 8603 0, // sub_16bit_hi 8604 62, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8605 0, // sub_mask_0 8606 0, // sub_mask_1 8607 0, // sub_xmm 8608 0, // sub_ymm 8609 }, 8610 { // GR32_NOREX 8611 37, // sub_8bit -> GR32_NOREX 8612 42, // sub_8bit_hi -> GR32_ABCD 8613 0, // sub_8bit_hi_phony 8614 37, // sub_16bit -> GR32_NOREX 8615 0, // sub_16bit_hi 8616 0, // sub_32bit 8617 0, // sub_mask_0 8618 0, // sub_mask_1 8619 0, // sub_xmm 8620 0, // sub_ymm 8621 }, 8622 { // VK32 8623 0, // sub_8bit 8624 0, // sub_8bit_hi 8625 0, // sub_8bit_hi_phony 8626 0, // sub_16bit 8627 0, // sub_16bit_hi 8628 0, // sub_32bit 8629 0, // sub_mask_0 8630 0, // sub_mask_1 8631 0, // sub_xmm 8632 0, // sub_ymm 8633 }, 8634 { // GR32_NOREX_NOSP 8635 39, // sub_8bit -> GR32_NOREX_NOSP 8636 42, // sub_8bit_hi -> GR32_ABCD 8637 0, // sub_8bit_hi_phony 8638 39, // sub_16bit -> GR32_NOREX_NOSP 8639 0, // sub_16bit_hi 8640 0, // sub_32bit 8641 0, // sub_mask_0 8642 0, // sub_mask_1 8643 0, // sub_xmm 8644 0, // sub_ymm 8645 }, 8646 { // RFP32 8647 0, // sub_8bit 8648 0, // sub_8bit_hi 8649 0, // sub_8bit_hi_phony 8650 0, // sub_16bit 8651 0, // sub_16bit_hi 8652 0, // sub_32bit 8653 0, // sub_mask_0 8654 0, // sub_mask_1 8655 0, // sub_xmm 8656 0, // sub_ymm 8657 }, 8658 { // VK32WM 8659 0, // sub_8bit 8660 0, // sub_8bit_hi 8661 0, // sub_8bit_hi_phony 8662 0, // sub_16bit 8663 0, // sub_16bit_hi 8664 0, // sub_32bit 8665 0, // sub_mask_0 8666 0, // sub_mask_1 8667 0, // sub_xmm 8668 0, // sub_ymm 8669 }, 8670 { // GR32_ABCD 8671 42, // sub_8bit -> GR32_ABCD 8672 42, // sub_8bit_hi -> GR32_ABCD 8673 0, // sub_8bit_hi_phony 8674 42, // sub_16bit -> GR32_ABCD 8675 0, // sub_16bit_hi 8676 0, // sub_32bit 8677 0, // sub_mask_0 8678 0, // sub_mask_1 8679 0, // sub_xmm 8680 0, // sub_ymm 8681 }, 8682 { // GR32_TC 8683 43, // sub_8bit -> GR32_TC 8684 44, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC 8685 0, // sub_8bit_hi_phony 8686 43, // sub_16bit -> GR32_TC 8687 0, // sub_16bit_hi 8688 0, // sub_32bit 8689 0, // sub_mask_0 8690 0, // sub_mask_1 8691 0, // sub_xmm 8692 0, // sub_ymm 8693 }, 8694 { // GR32_ABCD_and_GR32_TC 8695 44, // sub_8bit -> GR32_ABCD_and_GR32_TC 8696 44, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC 8697 0, // sub_8bit_hi_phony 8698 44, // sub_16bit -> GR32_ABCD_and_GR32_TC 8699 0, // sub_16bit_hi 8700 0, // sub_32bit 8701 0, // sub_mask_0 8702 0, // sub_mask_1 8703 0, // sub_xmm 8704 0, // sub_ymm 8705 }, 8706 { // GR32_AD 8707 45, // sub_8bit -> GR32_AD 8708 45, // sub_8bit_hi -> GR32_AD 8709 0, // sub_8bit_hi_phony 8710 45, // sub_16bit -> GR32_AD 8711 0, // sub_16bit_hi 8712 0, // sub_32bit 8713 0, // sub_mask_0 8714 0, // sub_mask_1 8715 0, // sub_xmm 8716 0, // sub_ymm 8717 }, 8718 { // GR32_BPSP 8719 46, // sub_8bit -> GR32_BPSP 8720 0, // sub_8bit_hi 8721 0, // sub_8bit_hi_phony 8722 46, // sub_16bit -> GR32_BPSP 8723 0, // sub_16bit_hi 8724 0, // sub_32bit 8725 0, // sub_mask_0 8726 0, // sub_mask_1 8727 0, // sub_xmm 8728 0, // sub_ymm 8729 }, 8730 { // GR32_BSI 8731 47, // sub_8bit -> GR32_BSI 8732 55, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI 8733 0, // sub_8bit_hi_phony 8734 47, // sub_16bit -> GR32_BSI 8735 0, // sub_16bit_hi 8736 0, // sub_32bit 8737 0, // sub_mask_0 8738 0, // sub_mask_1 8739 0, // sub_xmm 8740 0, // sub_ymm 8741 }, 8742 { // GR32_CB 8743 48, // sub_8bit -> GR32_CB 8744 48, // sub_8bit_hi -> GR32_CB 8745 0, // sub_8bit_hi_phony 8746 48, // sub_16bit -> GR32_CB 8747 0, // sub_16bit_hi 8748 0, // sub_32bit 8749 0, // sub_mask_0 8750 0, // sub_mask_1 8751 0, // sub_xmm 8752 0, // sub_ymm 8753 }, 8754 { // GR32_DC 8755 49, // sub_8bit -> GR32_DC 8756 49, // sub_8bit_hi -> GR32_DC 8757 0, // sub_8bit_hi_phony 8758 49, // sub_16bit -> GR32_DC 8759 0, // sub_16bit_hi 8760 0, // sub_32bit 8761 0, // sub_mask_0 8762 0, // sub_mask_1 8763 0, // sub_xmm 8764 0, // sub_ymm 8765 }, 8766 { // GR32_DIBP 8767 50, // sub_8bit -> GR32_DIBP 8768 0, // sub_8bit_hi 8769 0, // sub_8bit_hi_phony 8770 50, // sub_16bit -> GR32_DIBP 8771 0, // sub_16bit_hi 8772 0, // sub_32bit 8773 0, // sub_mask_0 8774 0, // sub_mask_1 8775 0, // sub_xmm 8776 0, // sub_ymm 8777 }, 8778 { // GR32_SIDI 8779 51, // sub_8bit -> GR32_SIDI 8780 0, // sub_8bit_hi 8781 0, // sub_8bit_hi_phony 8782 51, // sub_16bit -> GR32_SIDI 8783 0, // sub_16bit_hi 8784 0, // sub_32bit 8785 0, // sub_mask_0 8786 0, // sub_mask_1 8787 0, // sub_xmm 8788 0, // sub_ymm 8789 }, 8790 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit 8791 62, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8792 0, // sub_8bit_hi 8793 0, // sub_8bit_hi_phony 8794 52, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit 8795 0, // sub_16bit_hi 8796 52, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit 8797 0, // sub_mask_0 8798 0, // sub_mask_1 8799 0, // sub_xmm 8800 0, // sub_ymm 8801 }, 8802 { // CCR 8803 0, // sub_8bit 8804 0, // sub_8bit_hi 8805 0, // sub_8bit_hi_phony 8806 0, // sub_16bit 8807 0, // sub_16bit_hi 8808 0, // sub_32bit 8809 0, // sub_mask_0 8810 0, // sub_mask_1 8811 0, // sub_xmm 8812 0, // sub_ymm 8813 }, 8814 { // DFCCR 8815 0, // sub_8bit 8816 0, // sub_8bit_hi 8817 0, // sub_8bit_hi_phony 8818 0, // sub_16bit 8819 0, // sub_16bit_hi 8820 0, // sub_32bit 8821 0, // sub_mask_0 8822 0, // sub_mask_1 8823 0, // sub_xmm 8824 0, // sub_ymm 8825 }, 8826 { // GR32_ABCD_and_GR32_BSI 8827 55, // sub_8bit -> GR32_ABCD_and_GR32_BSI 8828 55, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI 8829 0, // sub_8bit_hi_phony 8830 55, // sub_16bit -> GR32_ABCD_and_GR32_BSI 8831 0, // sub_16bit_hi 8832 0, // sub_32bit 8833 0, // sub_mask_0 8834 0, // sub_mask_1 8835 0, // sub_xmm 8836 0, // sub_ymm 8837 }, 8838 { // GR32_AD_and_GR32_DC 8839 56, // sub_8bit -> GR32_AD_and_GR32_DC 8840 56, // sub_8bit_hi -> GR32_AD_and_GR32_DC 8841 0, // sub_8bit_hi_phony 8842 56, // sub_16bit -> GR32_AD_and_GR32_DC 8843 0, // sub_16bit_hi 8844 0, // sub_32bit 8845 0, // sub_mask_0 8846 0, // sub_mask_1 8847 0, // sub_xmm 8848 0, // sub_ymm 8849 }, 8850 { // GR32_BPSP_and_GR32_DIBP 8851 57, // sub_8bit -> GR32_BPSP_and_GR32_DIBP 8852 0, // sub_8bit_hi 8853 0, // sub_8bit_hi_phony 8854 57, // sub_16bit -> GR32_BPSP_and_GR32_DIBP 8855 0, // sub_16bit_hi 8856 0, // sub_32bit 8857 0, // sub_mask_0 8858 0, // sub_mask_1 8859 0, // sub_xmm 8860 0, // sub_ymm 8861 }, 8862 { // GR32_BPSP_and_GR32_TC 8863 58, // sub_8bit -> GR32_BPSP_and_GR32_TC 8864 0, // sub_8bit_hi 8865 0, // sub_8bit_hi_phony 8866 58, // sub_16bit -> GR32_BPSP_and_GR32_TC 8867 0, // sub_16bit_hi 8868 0, // sub_32bit 8869 0, // sub_mask_0 8870 0, // sub_mask_1 8871 0, // sub_xmm 8872 0, // sub_ymm 8873 }, 8874 { // GR32_BSI_and_GR32_SIDI 8875 59, // sub_8bit -> GR32_BSI_and_GR32_SIDI 8876 0, // sub_8bit_hi 8877 0, // sub_8bit_hi_phony 8878 59, // sub_16bit -> GR32_BSI_and_GR32_SIDI 8879 0, // sub_16bit_hi 8880 0, // sub_32bit 8881 0, // sub_mask_0 8882 0, // sub_mask_1 8883 0, // sub_xmm 8884 0, // sub_ymm 8885 }, 8886 { // GR32_CB_and_GR32_DC 8887 60, // sub_8bit -> GR32_CB_and_GR32_DC 8888 60, // sub_8bit_hi -> GR32_CB_and_GR32_DC 8889 0, // sub_8bit_hi_phony 8890 60, // sub_16bit -> GR32_CB_and_GR32_DC 8891 0, // sub_16bit_hi 8892 0, // sub_32bit 8893 0, // sub_mask_0 8894 0, // sub_mask_1 8895 0, // sub_xmm 8896 0, // sub_ymm 8897 }, 8898 { // GR32_DIBP_and_GR32_SIDI 8899 61, // sub_8bit -> GR32_DIBP_and_GR32_SIDI 8900 0, // sub_8bit_hi 8901 0, // sub_8bit_hi_phony 8902 61, // sub_16bit -> GR32_DIBP_and_GR32_SIDI 8903 0, // sub_16bit_hi 8904 0, // sub_32bit 8905 0, // sub_mask_0 8906 0, // sub_mask_1 8907 0, // sub_xmm 8908 0, // sub_ymm 8909 }, 8910 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8911 62, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8912 0, // sub_8bit_hi 8913 0, // sub_8bit_hi_phony 8914 62, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8915 0, // sub_16bit_hi 8916 62, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 8917 0, // sub_mask_0 8918 0, // sub_mask_1 8919 0, // sub_xmm 8920 0, // sub_ymm 8921 }, 8922 { // LOW32_ADDR_ACCESS_with_sub_32bit 8923 0, // sub_8bit 8924 0, // sub_8bit_hi 8925 0, // sub_8bit_hi_phony 8926 63, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit 8927 0, // sub_16bit_hi 8928 63, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit 8929 0, // sub_mask_0 8930 0, // sub_mask_1 8931 0, // sub_xmm 8932 0, // sub_ymm 8933 }, 8934 { // RFP64 8935 0, // sub_8bit 8936 0, // sub_8bit_hi 8937 0, // sub_8bit_hi_phony 8938 0, // sub_16bit 8939 0, // sub_16bit_hi 8940 0, // sub_32bit 8941 0, // sub_mask_0 8942 0, // sub_mask_1 8943 0, // sub_xmm 8944 0, // sub_ymm 8945 }, 8946 { // FR64X 8947 0, // sub_8bit 8948 0, // sub_8bit_hi 8949 0, // sub_8bit_hi_phony 8950 0, // sub_16bit 8951 0, // sub_16bit_hi 8952 0, // sub_32bit 8953 0, // sub_mask_0 8954 0, // sub_mask_1 8955 0, // sub_xmm 8956 0, // sub_ymm 8957 }, 8958 { // GR64 8959 69, // sub_8bit -> GR64_with_sub_8bit 8960 90, // sub_8bit_hi -> GR64_ABCD 8961 0, // sub_8bit_hi_phony 8962 66, // sub_16bit -> GR64 8963 0, // sub_16bit_hi 8964 66, // sub_32bit -> GR64 8965 0, // sub_mask_0 8966 0, // sub_mask_1 8967 0, // sub_xmm 8968 0, // sub_ymm 8969 }, 8970 { // CONTROL_REG 8971 0, // sub_8bit 8972 0, // sub_8bit_hi 8973 0, // sub_8bit_hi_phony 8974 0, // sub_16bit 8975 0, // sub_16bit_hi 8976 0, // sub_32bit 8977 0, // sub_mask_0 8978 0, // sub_mask_1 8979 0, // sub_xmm 8980 0, // sub_ymm 8981 }, 8982 { // FR64 8983 0, // sub_8bit 8984 0, // sub_8bit_hi 8985 0, // sub_8bit_hi_phony 8986 0, // sub_16bit 8987 0, // sub_16bit_hi 8988 0, // sub_32bit 8989 0, // sub_mask_0 8990 0, // sub_mask_1 8991 0, // sub_xmm 8992 0, // sub_ymm 8993 }, 8994 { // GR64_with_sub_8bit 8995 69, // sub_8bit -> GR64_with_sub_8bit 8996 90, // sub_8bit_hi -> GR64_ABCD 8997 0, // sub_8bit_hi_phony 8998 69, // sub_16bit -> GR64_with_sub_8bit 8999 0, // sub_16bit_hi 9000 69, // sub_32bit -> GR64_with_sub_8bit 9001 0, // sub_mask_0 9002 0, // sub_mask_1 9003 0, // sub_xmm 9004 0, // sub_ymm 9005 }, 9006 { // GR64_NOSP 9007 70, // sub_8bit -> GR64_NOSP 9008 90, // sub_8bit_hi -> GR64_ABCD 9009 0, // sub_8bit_hi_phony 9010 70, // sub_16bit -> GR64_NOSP 9011 0, // sub_16bit_hi 9012 70, // sub_32bit -> GR64_NOSP 9013 0, // sub_mask_0 9014 0, // sub_mask_1 9015 0, // sub_xmm 9016 0, // sub_ymm 9017 }, 9018 { // GR64_TC 9019 74, // sub_8bit -> GR64_TC_with_sub_8bit 9020 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9021 0, // sub_8bit_hi_phony 9022 71, // sub_16bit -> GR64_TC 9023 0, // sub_16bit_hi 9024 71, // sub_32bit -> GR64_TC 9025 0, // sub_mask_0 9026 0, // sub_mask_1 9027 0, // sub_xmm 9028 0, // sub_ymm 9029 }, 9030 { // GR64_NOREX 9031 78, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX 9032 90, // sub_8bit_hi -> GR64_ABCD 9033 0, // sub_8bit_hi_phony 9034 72, // sub_16bit -> GR64_NOREX 9035 0, // sub_16bit_hi 9036 72, // sub_32bit -> GR64_NOREX 9037 0, // sub_mask_0 9038 0, // sub_mask_1 9039 0, // sub_xmm 9040 0, // sub_ymm 9041 }, 9042 { // GR64_TCW64 9043 76, // sub_8bit -> GR64_TCW64_with_sub_8bit 9044 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9045 0, // sub_8bit_hi_phony 9046 73, // sub_16bit -> GR64_TCW64 9047 0, // sub_16bit_hi 9048 73, // sub_32bit -> GR64_TCW64 9049 0, // sub_mask_0 9050 0, // sub_mask_1 9051 0, // sub_xmm 9052 0, // sub_ymm 9053 }, 9054 { // GR64_TC_with_sub_8bit 9055 74, // sub_8bit -> GR64_TC_with_sub_8bit 9056 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9057 0, // sub_8bit_hi_phony 9058 74, // sub_16bit -> GR64_TC_with_sub_8bit 9059 0, // sub_16bit_hi 9060 74, // sub_32bit -> GR64_TC_with_sub_8bit 9061 0, // sub_mask_0 9062 0, // sub_mask_1 9063 0, // sub_xmm 9064 0, // sub_ymm 9065 }, 9066 { // GR64_NOSP_and_GR64_TC 9067 75, // sub_8bit -> GR64_NOSP_and_GR64_TC 9068 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9069 0, // sub_8bit_hi_phony 9070 75, // sub_16bit -> GR64_NOSP_and_GR64_TC 9071 0, // sub_16bit_hi 9072 75, // sub_32bit -> GR64_NOSP_and_GR64_TC 9073 0, // sub_mask_0 9074 0, // sub_mask_1 9075 0, // sub_xmm 9076 0, // sub_ymm 9077 }, 9078 { // GR64_TCW64_with_sub_8bit 9079 76, // sub_8bit -> GR64_TCW64_with_sub_8bit 9080 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9081 0, // sub_8bit_hi_phony 9082 76, // sub_16bit -> GR64_TCW64_with_sub_8bit 9083 0, // sub_16bit_hi 9084 76, // sub_32bit -> GR64_TCW64_with_sub_8bit 9085 0, // sub_mask_0 9086 0, // sub_mask_1 9087 0, // sub_xmm 9088 0, // sub_ymm 9089 }, 9090 { // GR64_TC_and_GR64_TCW64 9091 84, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit 9092 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9093 0, // sub_8bit_hi_phony 9094 77, // sub_16bit -> GR64_TC_and_GR64_TCW64 9095 0, // sub_16bit_hi 9096 77, // sub_32bit -> GR64_TC_and_GR64_TCW64 9097 0, // sub_mask_0 9098 0, // sub_mask_1 9099 0, // sub_xmm 9100 0, // sub_ymm 9101 }, 9102 { // GR64_with_sub_16bit_in_GR16_NOREX 9103 78, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX 9104 90, // sub_8bit_hi -> GR64_ABCD 9105 0, // sub_8bit_hi_phony 9106 78, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX 9107 0, // sub_16bit_hi 9108 78, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX 9109 0, // sub_mask_0 9110 0, // sub_mask_1 9111 0, // sub_xmm 9112 0, // sub_ymm 9113 }, 9114 { // VK64 9115 0, // sub_8bit 9116 0, // sub_8bit_hi 9117 0, // sub_8bit_hi_phony 9118 0, // sub_16bit 9119 0, // sub_16bit_hi 9120 0, // sub_32bit 9121 0, // sub_mask_0 9122 0, // sub_mask_1 9123 0, // sub_xmm 9124 0, // sub_ymm 9125 }, 9126 { // VR64 9127 0, // sub_8bit 9128 0, // sub_8bit_hi 9129 0, // sub_8bit_hi_phony 9130 0, // sub_16bit 9131 0, // sub_16bit_hi 9132 0, // sub_32bit 9133 0, // sub_mask_0 9134 0, // sub_mask_1 9135 0, // sub_xmm 9136 0, // sub_ymm 9137 }, 9138 { // GR64_NOREX_NOSP 9139 81, // sub_8bit -> GR64_NOREX_NOSP 9140 90, // sub_8bit_hi -> GR64_ABCD 9141 0, // sub_8bit_hi_phony 9142 81, // sub_16bit -> GR64_NOREX_NOSP 9143 0, // sub_16bit_hi 9144 81, // sub_32bit -> GR64_NOREX_NOSP 9145 0, // sub_mask_0 9146 0, // sub_mask_1 9147 0, // sub_xmm 9148 0, // sub_ymm 9149 }, 9150 { // GR64_NOREX_and_GR64_TC 9151 87, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9152 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9153 0, // sub_8bit_hi_phony 9154 82, // sub_16bit -> GR64_NOREX_and_GR64_TC 9155 0, // sub_16bit_hi 9156 82, // sub_32bit -> GR64_NOREX_and_GR64_TC 9157 0, // sub_mask_0 9158 0, // sub_mask_1 9159 0, // sub_xmm 9160 0, // sub_ymm 9161 }, 9162 { // GR64_NOSP_and_GR64_TCW64 9163 83, // sub_8bit -> GR64_NOSP_and_GR64_TCW64 9164 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9165 0, // sub_8bit_hi_phony 9166 83, // sub_16bit -> GR64_NOSP_and_GR64_TCW64 9167 0, // sub_16bit_hi 9168 83, // sub_32bit -> GR64_NOSP_and_GR64_TCW64 9169 0, // sub_mask_0 9170 0, // sub_mask_1 9171 0, // sub_xmm 9172 0, // sub_ymm 9173 }, 9174 { // GR64_TCW64_and_GR64_TC_with_sub_8bit 9175 84, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit 9176 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9177 0, // sub_8bit_hi_phony 9178 84, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit 9179 0, // sub_16bit_hi 9180 84, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit 9181 0, // sub_mask_0 9182 0, // sub_mask_1 9183 0, // sub_xmm 9184 0, // sub_ymm 9185 }, 9186 { // VK64WM 9187 0, // sub_8bit 9188 0, // sub_8bit_hi 9189 0, // sub_8bit_hi_phony 9190 0, // sub_16bit 9191 0, // sub_16bit_hi 9192 0, // sub_32bit 9193 0, // sub_mask_0 9194 0, // sub_mask_1 9195 0, // sub_xmm 9196 0, // sub_ymm 9197 }, 9198 { // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 9199 86, // sub_8bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64 9200 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9201 0, // sub_8bit_hi_phony 9202 86, // sub_16bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64 9203 0, // sub_16bit_hi 9204 86, // sub_32bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64 9205 0, // sub_mask_0 9206 0, // sub_mask_1 9207 0, // sub_xmm 9208 0, // sub_ymm 9209 }, 9210 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9211 87, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9212 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9213 0, // sub_8bit_hi_phony 9214 87, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9215 0, // sub_16bit_hi 9216 87, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9217 0, // sub_mask_0 9218 0, // sub_mask_1 9219 0, // sub_xmm 9220 0, // sub_ymm 9221 }, 9222 { // GR64_NOREX_NOSP_and_GR64_TC 9223 88, // sub_8bit -> GR64_NOREX_NOSP_and_GR64_TC 9224 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9225 0, // sub_8bit_hi_phony 9226 88, // sub_16bit -> GR64_NOREX_NOSP_and_GR64_TC 9227 0, // sub_16bit_hi 9228 88, // sub_32bit -> GR64_NOREX_NOSP_and_GR64_TC 9229 0, // sub_mask_0 9230 0, // sub_mask_1 9231 0, // sub_xmm 9232 0, // sub_ymm 9233 }, 9234 { // GR64_NOREX_and_GR64_TCW64 9235 91, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC 9236 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9237 0, // sub_8bit_hi_phony 9238 89, // sub_16bit -> GR64_NOREX_and_GR64_TCW64 9239 0, // sub_16bit_hi 9240 89, // sub_32bit -> GR64_NOREX_and_GR64_TCW64 9241 0, // sub_mask_0 9242 0, // sub_mask_1 9243 0, // sub_xmm 9244 0, // sub_ymm 9245 }, 9246 { // GR64_ABCD 9247 90, // sub_8bit -> GR64_ABCD 9248 90, // sub_8bit_hi -> GR64_ABCD 9249 0, // sub_8bit_hi_phony 9250 90, // sub_16bit -> GR64_ABCD 9251 0, // sub_16bit_hi 9252 90, // sub_32bit -> GR64_ABCD 9253 0, // sub_mask_0 9254 0, // sub_mask_1 9255 0, // sub_xmm 9256 0, // sub_ymm 9257 }, 9258 { // GR64_with_sub_32bit_in_GR32_TC 9259 91, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC 9260 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9261 0, // sub_8bit_hi_phony 9262 91, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC 9263 0, // sub_16bit_hi 9264 91, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC 9265 0, // sub_mask_0 9266 0, // sub_mask_1 9267 0, // sub_xmm 9268 0, // sub_ymm 9269 }, 9270 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9271 92, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9272 92, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9273 0, // sub_8bit_hi_phony 9274 92, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9275 0, // sub_16bit_hi 9276 92, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9277 0, // sub_mask_0 9278 0, // sub_mask_1 9279 0, // sub_xmm 9280 0, // sub_ymm 9281 }, 9282 { // GR64_AD 9283 93, // sub_8bit -> GR64_AD 9284 93, // sub_8bit_hi -> GR64_AD 9285 0, // sub_8bit_hi_phony 9286 93, // sub_16bit -> GR64_AD 9287 0, // sub_16bit_hi 9288 93, // sub_32bit -> GR64_AD 9289 0, // sub_mask_0 9290 0, // sub_mask_1 9291 0, // sub_xmm 9292 0, // sub_ymm 9293 }, 9294 { // GR64_and_LOW32_ADDR_ACCESS_RBP 9295 104, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9296 0, // sub_8bit_hi 9297 0, // sub_8bit_hi_phony 9298 94, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP 9299 0, // sub_16bit_hi 9300 94, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP 9301 0, // sub_mask_0 9302 0, // sub_mask_1 9303 0, // sub_xmm 9304 0, // sub_ymm 9305 }, 9306 { // GR64_with_sub_32bit_in_GR32_BPSP 9307 95, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP 9308 0, // sub_8bit_hi 9309 0, // sub_8bit_hi_phony 9310 95, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP 9311 0, // sub_16bit_hi 9312 95, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP 9313 0, // sub_mask_0 9314 0, // sub_mask_1 9315 0, // sub_xmm 9316 0, // sub_ymm 9317 }, 9318 { // GR64_with_sub_32bit_in_GR32_BSI 9319 96, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI 9320 102, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9321 0, // sub_8bit_hi_phony 9322 96, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI 9323 0, // sub_16bit_hi 9324 96, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI 9325 0, // sub_mask_0 9326 0, // sub_mask_1 9327 0, // sub_xmm 9328 0, // sub_ymm 9329 }, 9330 { // GR64_with_sub_32bit_in_GR32_CB 9331 97, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB 9332 97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB 9333 0, // sub_8bit_hi_phony 9334 97, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB 9335 0, // sub_16bit_hi 9336 97, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB 9337 0, // sub_mask_0 9338 0, // sub_mask_1 9339 0, // sub_xmm 9340 0, // sub_ymm 9341 }, 9342 { // GR64_with_sub_32bit_in_GR32_DC 9343 98, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DC 9344 98, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_DC 9345 0, // sub_8bit_hi_phony 9346 98, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DC 9347 0, // sub_16bit_hi 9348 98, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DC 9349 0, // sub_mask_0 9350 0, // sub_mask_1 9351 0, // sub_xmm 9352 0, // sub_ymm 9353 }, 9354 { // GR64_with_sub_32bit_in_GR32_DIBP 9355 99, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP 9356 0, // sub_8bit_hi 9357 0, // sub_8bit_hi_phony 9358 99, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP 9359 0, // sub_16bit_hi 9360 99, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP 9361 0, // sub_mask_0 9362 0, // sub_mask_1 9363 0, // sub_xmm 9364 0, // sub_ymm 9365 }, 9366 { // GR64_with_sub_32bit_in_GR32_SIDI 9367 100, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI 9368 0, // sub_8bit_hi 9369 0, // sub_8bit_hi_phony 9370 100, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI 9371 0, // sub_16bit_hi 9372 100, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI 9373 0, // sub_mask_0 9374 0, // sub_mask_1 9375 0, // sub_xmm 9376 0, // sub_ymm 9377 }, 9378 { // GR64_and_LOW32_ADDR_ACCESS 9379 0, // sub_8bit 9380 0, // sub_8bit_hi 9381 0, // sub_8bit_hi_phony 9382 101, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS 9383 0, // sub_16bit_hi 9384 101, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS 9385 0, // sub_mask_0 9386 0, // sub_mask_1 9387 0, // sub_xmm 9388 0, // sub_ymm 9389 }, 9390 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9391 102, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9392 102, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9393 0, // sub_8bit_hi_phony 9394 102, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9395 0, // sub_16bit_hi 9396 102, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9397 0, // sub_mask_0 9398 0, // sub_mask_1 9399 0, // sub_xmm 9400 0, // sub_ymm 9401 }, 9402 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9403 103, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9404 103, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9405 0, // sub_8bit_hi_phony 9406 103, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9407 0, // sub_16bit_hi 9408 103, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9409 0, // sub_mask_0 9410 0, // sub_mask_1 9411 0, // sub_xmm 9412 0, // sub_ymm 9413 }, 9414 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9415 104, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9416 0, // sub_8bit_hi 9417 0, // sub_8bit_hi_phony 9418 104, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9419 0, // sub_16bit_hi 9420 104, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9421 0, // sub_mask_0 9422 0, // sub_mask_1 9423 0, // sub_xmm 9424 0, // sub_ymm 9425 }, 9426 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 9427 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 9428 0, // sub_8bit_hi 9429 0, // sub_8bit_hi_phony 9430 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 9431 0, // sub_16bit_hi 9432 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 9433 0, // sub_mask_0 9434 0, // sub_mask_1 9435 0, // sub_xmm 9436 0, // sub_ymm 9437 }, 9438 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 9439 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 9440 0, // sub_8bit_hi 9441 0, // sub_8bit_hi_phony 9442 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 9443 0, // sub_16bit_hi 9444 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 9445 0, // sub_mask_0 9446 0, // sub_mask_1 9447 0, // sub_xmm 9448 0, // sub_ymm 9449 }, 9450 { // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9451 107, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9452 107, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9453 0, // sub_8bit_hi_phony 9454 107, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9455 0, // sub_16bit_hi 9456 107, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9457 0, // sub_mask_0 9458 0, // sub_mask_1 9459 0, // sub_xmm 9460 0, // sub_ymm 9461 }, 9462 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 9463 108, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 9464 0, // sub_8bit_hi 9465 0, // sub_8bit_hi_phony 9466 108, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 9467 0, // sub_16bit_hi 9468 108, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 9469 0, // sub_mask_0 9470 0, // sub_mask_1 9471 0, // sub_xmm 9472 0, // sub_ymm 9473 }, 9474 { // RST 9475 0, // sub_8bit 9476 0, // sub_8bit_hi 9477 0, // sub_8bit_hi_phony 9478 0, // sub_16bit 9479 0, // sub_16bit_hi 9480 0, // sub_32bit 9481 0, // sub_mask_0 9482 0, // sub_mask_1 9483 0, // sub_xmm 9484 0, // sub_ymm 9485 }, 9486 { // RFP80 9487 0, // sub_8bit 9488 0, // sub_8bit_hi 9489 0, // sub_8bit_hi_phony 9490 0, // sub_16bit 9491 0, // sub_16bit_hi 9492 0, // sub_32bit 9493 0, // sub_mask_0 9494 0, // sub_mask_1 9495 0, // sub_xmm 9496 0, // sub_ymm 9497 }, 9498 { // RFP80_7 9499 0, // sub_8bit 9500 0, // sub_8bit_hi 9501 0, // sub_8bit_hi_phony 9502 0, // sub_16bit 9503 0, // sub_16bit_hi 9504 0, // sub_32bit 9505 0, // sub_mask_0 9506 0, // sub_mask_1 9507 0, // sub_xmm 9508 0, // sub_ymm 9509 }, 9510 { // VR128X 9511 0, // sub_8bit 9512 0, // sub_8bit_hi 9513 0, // sub_8bit_hi_phony 9514 0, // sub_16bit 9515 0, // sub_16bit_hi 9516 0, // sub_32bit 9517 0, // sub_mask_0 9518 0, // sub_mask_1 9519 0, // sub_xmm 9520 0, // sub_ymm 9521 }, 9522 { // VR128 9523 0, // sub_8bit 9524 0, // sub_8bit_hi 9525 0, // sub_8bit_hi_phony 9526 0, // sub_16bit 9527 0, // sub_16bit_hi 9528 0, // sub_32bit 9529 0, // sub_mask_0 9530 0, // sub_mask_1 9531 0, // sub_xmm 9532 0, // sub_ymm 9533 }, 9534 { // BNDR 9535 0, // sub_8bit 9536 0, // sub_8bit_hi 9537 0, // sub_8bit_hi_phony 9538 0, // sub_16bit 9539 0, // sub_16bit_hi 9540 0, // sub_32bit 9541 0, // sub_mask_0 9542 0, // sub_mask_1 9543 0, // sub_xmm 9544 0, // sub_ymm 9545 }, 9546 { // VR256X 9547 0, // sub_8bit 9548 0, // sub_8bit_hi 9549 0, // sub_8bit_hi_phony 9550 0, // sub_16bit 9551 0, // sub_16bit_hi 9552 0, // sub_32bit 9553 0, // sub_mask_0 9554 0, // sub_mask_1 9555 115, // sub_xmm -> VR256X 9556 0, // sub_ymm 9557 }, 9558 { // VR256 9559 0, // sub_8bit 9560 0, // sub_8bit_hi 9561 0, // sub_8bit_hi_phony 9562 0, // sub_16bit 9563 0, // sub_16bit_hi 9564 0, // sub_32bit 9565 0, // sub_mask_0 9566 0, // sub_mask_1 9567 116, // sub_xmm -> VR256 9568 0, // sub_ymm 9569 }, 9570 { // VR512 9571 0, // sub_8bit 9572 0, // sub_8bit_hi 9573 0, // sub_8bit_hi_phony 9574 0, // sub_16bit 9575 0, // sub_16bit_hi 9576 0, // sub_32bit 9577 0, // sub_mask_0 9578 0, // sub_mask_1 9579 117, // sub_xmm -> VR512 9580 117, // sub_ymm -> VR512 9581 }, 9582 { // VR512_0_15 9583 0, // sub_8bit 9584 0, // sub_8bit_hi 9585 0, // sub_8bit_hi_phony 9586 0, // sub_16bit 9587 0, // sub_16bit_hi 9588 0, // sub_32bit 9589 0, // sub_mask_0 9590 0, // sub_mask_1 9591 118, // sub_xmm -> VR512_0_15 9592 118, // sub_ymm -> VR512_0_15 9593 }, 9594 }; 9595 assert(RC && "Missing regclass"); 9596 if (!Idx) return RC; 9597 --Idx; 9598 assert(Idx < 10 && "Bad subreg"); 9599 unsigned TV = Table[RC->getID()][Idx]; 9600 return TV ? getRegClass(TV - 1) : nullptr; 9601} 9602 9603/// Get the weight in units of pressure for this register class. 9604const RegClassWeight &X86GenRegisterInfo:: 9605getRegClassWeight(const TargetRegisterClass *RC) const { 9606 static const RegClassWeight RCWeightTable[] = { 9607 {1, 20}, // GR8 9608 {0, 0}, // GRH8 9609 {1, 8}, // GR8_NOREX 9610 {1, 4}, // GR8_ABCD_H 9611 {1, 4}, // GR8_ABCD_L 9612 {0, 0}, // GRH16 9613 {2, 32}, // GR16 9614 {2, 16}, // GR16_NOREX 9615 {1, 8}, // VK1 9616 {1, 8}, // VK16 9617 {1, 8}, // VK2 9618 {1, 8}, // VK4 9619 {1, 8}, // VK8 9620 {1, 7}, // VK16WM 9621 {1, 7}, // VK1WM 9622 {1, 7}, // VK2WM 9623 {1, 7}, // VK4WM 9624 {1, 7}, // VK8WM 9625 {1, 6}, // SEGMENT_REG 9626 {2, 8}, // GR16_ABCD 9627 {0, 0}, // FPCCR 9628 {2, 8}, // VK16PAIR 9629 {2, 8}, // VK1PAIR 9630 {2, 8}, // VK2PAIR 9631 {2, 8}, // VK4PAIR 9632 {2, 8}, // VK8PAIR 9633 {2, 6}, // VK16PAIR_with_sub_mask_0_in_VK16WM 9634 {1, 32}, // FR32X 9635 {2, 34}, // LOW32_ADDR_ACCESS_RBP 9636 {2, 34}, // LOW32_ADDR_ACCESS 9637 {2, 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit 9638 {1, 16}, // DEBUG_REG 9639 {1, 16}, // FR32 9640 {2, 32}, // GR32 9641 {2, 30}, // GR32_NOSP 9642 {2, 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 9643 {2, 16}, // GR32_NOREX 9644 {1, 8}, // VK32 9645 {2, 14}, // GR32_NOREX_NOSP 9646 {1, 7}, // RFP32 9647 {1, 7}, // VK32WM 9648 {2, 8}, // GR32_ABCD 9649 {2, 8}, // GR32_TC 9650 {2, 6}, // GR32_ABCD_and_GR32_TC 9651 {2, 4}, // GR32_AD 9652 {2, 4}, // GR32_BPSP 9653 {2, 4}, // GR32_BSI 9654 {2, 4}, // GR32_CB 9655 {2, 4}, // GR32_DC 9656 {2, 4}, // GR32_DIBP 9657 {2, 4}, // GR32_SIDI 9658 {2, 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit 9659 {0, 0}, // CCR 9660 {0, 0}, // DFCCR 9661 {2, 2}, // GR32_ABCD_and_GR32_BSI 9662 {2, 2}, // GR32_AD_and_GR32_DC 9663 {2, 2}, // GR32_BPSP_and_GR32_DIBP 9664 {2, 2}, // GR32_BPSP_and_GR32_TC 9665 {2, 2}, // GR32_BSI_and_GR32_SIDI 9666 {2, 2}, // GR32_CB_and_GR32_DC 9667 {2, 2}, // GR32_DIBP_and_GR32_SIDI 9668 {2, 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 9669 {2, 2}, // LOW32_ADDR_ACCESS_with_sub_32bit 9670 {1, 7}, // RFP64 9671 {1, 32}, // FR64X 9672 {2, 34}, // GR64 9673 {1, 16}, // CONTROL_REG 9674 {1, 16}, // FR64 9675 {2, 32}, // GR64_with_sub_8bit 9676 {2, 30}, // GR64_NOSP 9677 {2, 20}, // GR64_TC 9678 {2, 18}, // GR64_NOREX 9679 {2, 18}, // GR64_TCW64 9680 {2, 18}, // GR64_TC_with_sub_8bit 9681 {2, 16}, // GR64_NOSP_and_GR64_TC 9682 {2, 16}, // GR64_TCW64_with_sub_8bit 9683 {2, 16}, // GR64_TC_and_GR64_TCW64 9684 {2, 16}, // GR64_with_sub_16bit_in_GR16_NOREX 9685 {1, 8}, // VK64 9686 {1, 8}, // VR64 9687 {2, 14}, // GR64_NOREX_NOSP 9688 {2, 14}, // GR64_NOREX_and_GR64_TC 9689 {2, 14}, // GR64_NOSP_and_GR64_TCW64 9690 {2, 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit 9691 {1, 7}, // VK64WM 9692 {2, 12}, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 9693 {2, 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 9694 {2, 10}, // GR64_NOREX_NOSP_and_GR64_TC 9695 {2, 10}, // GR64_NOREX_and_GR64_TCW64 9696 {2, 8}, // GR64_ABCD 9697 {2, 8}, // GR64_with_sub_32bit_in_GR32_TC 9698 {2, 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 9699 {2, 4}, // GR64_AD 9700 {2, 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP 9701 {2, 4}, // GR64_with_sub_32bit_in_GR32_BPSP 9702 {2, 4}, // GR64_with_sub_32bit_in_GR32_BSI 9703 {2, 4}, // GR64_with_sub_32bit_in_GR32_CB 9704 {2, 4}, // GR64_with_sub_32bit_in_GR32_DC 9705 {2, 4}, // GR64_with_sub_32bit_in_GR32_DIBP 9706 {2, 4}, // GR64_with_sub_32bit_in_GR32_SIDI 9707 {2, 2}, // GR64_and_LOW32_ADDR_ACCESS 9708 {2, 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 9709 {2, 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC 9710 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 9711 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 9712 {2, 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 9713 {2, 2}, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC 9714 {2, 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 9715 {0, 0}, // RST 9716 {1, 7}, // RFP80 9717 {0, 0}, // RFP80_7 9718 {1, 32}, // VR128X 9719 {1, 16}, // VR128 9720 {1, 4}, // BNDR 9721 {1, 32}, // VR256X 9722 {1, 16}, // VR256 9723 {1, 32}, // VR512 9724 {1, 16}, // VR512_0_15 9725 }; 9726 return RCWeightTable[RC->getID()]; 9727} 9728 9729/// Get the weight in units of pressure for this register unit. 9730unsigned X86GenRegisterInfo:: 9731getRegUnitWeight(unsigned RegUnit) const { 9732 assert(RegUnit < 164 && "invalid register unit"); 9733 // All register units have unit weight. 9734 return 1; 9735} 9736 9737 9738// Get the number of dimensions of register pressure. 9739unsigned X86GenRegisterInfo::getNumRegPressureSets() const { 9740 return 33; 9741} 9742 9743// Get the name of this register unit pressure set. 9744const char *X86GenRegisterInfo:: 9745getRegPressureSetName(unsigned Idx) const { 9746 static const char *const PressureNameTable[] = { 9747 "BNDR", 9748 "SEGMENT_REG", 9749 "GR32_BPSP", 9750 "LOW32_ADDR_ACCESS_with_sub_32bit", 9751 "GR32_BSI", 9752 "GR32_SIDI", 9753 "GR32_DIBP+GR32_SIDI", 9754 "GR32_DIBP+LOW32_ADDR_ACCESS_with_sub_32bit", 9755 "RFP32", 9756 "GR8_ABCD_H+GR32_BSI", 9757 "GR8_ABCD_L+GR32_BSI", 9758 "VK1", 9759 "VR64", 9760 "GR8_NOREX", 9761 "GR32_TC", 9762 "GR32_BPSP+GR32_TC", 9763 "DEBUG_REG", 9764 "FR32", 9765 "CONTROL_REG", 9766 "GR64_NOREX", 9767 "GR64_TCW64", 9768 "GR32_BPSP+GR64_TCW64", 9769 "GR8", 9770 "GR8+GR32_DIBP", 9771 "GR8+GR32_BSI", 9772 "GR64_TC+GR64_TCW64", 9773 "GR8+LOW32_ADDR_ACCESS_with_sub_32bit", 9774 "GR8+GR64_NOREX", 9775 "GR64_TC", 9776 "GR8+GR64_TCW64", 9777 "GR8+GR64_TC", 9778 "FR32X", 9779 "GR16", 9780 }; 9781 return PressureNameTable[Idx]; 9782} 9783 9784// Get the register unit pressure limit for this dimension. 9785// This limit must be adjusted dynamically for reserved registers. 9786unsigned X86GenRegisterInfo:: 9787getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { 9788 static const uint8_t PressureLimitTable[] = { 9789 4, // 0: BNDR 9790 6, // 1: SEGMENT_REG 9791 6, // 2: GR32_BPSP 9792 6, // 3: LOW32_ADDR_ACCESS_with_sub_32bit 9793 6, // 4: GR32_BSI 9794 6, // 5: GR32_SIDI 9795 6, // 6: GR32_DIBP+GR32_SIDI 9796 6, // 7: GR32_DIBP+LOW32_ADDR_ACCESS_with_sub_32bit 9797 7, // 8: RFP32 9798 7, // 9: GR8_ABCD_H+GR32_BSI 9799 7, // 10: GR8_ABCD_L+GR32_BSI 9800 8, // 11: VK1 9801 8, // 12: VR64 9802 10, // 13: GR8_NOREX 9803 12, // 14: GR32_TC 9804 12, // 15: GR32_BPSP+GR32_TC 9805 16, // 16: DEBUG_REG 9806 16, // 17: FR32 9807 16, // 18: CONTROL_REG 9808 18, // 19: GR64_NOREX 9809 20, // 20: GR64_TCW64 9810 20, // 21: GR32_BPSP+GR64_TCW64 9811 22, // 22: GR8 9812 22, // 23: GR8+GR32_DIBP 9813 22, // 24: GR8+GR32_BSI 9814 22, // 25: GR64_TC+GR64_TCW64 9815 23, // 26: GR8+LOW32_ADDR_ACCESS_with_sub_32bit 9816 26, // 27: GR8+GR64_NOREX 9817 26, // 28: GR64_TC 9818 27, // 29: GR8+GR64_TCW64 9819 28, // 30: GR8+GR64_TC 9820 32, // 31: FR32X 9821 34, // 32: GR16 9822 }; 9823 return PressureLimitTable[Idx]; 9824} 9825 9826/// Table of pressure sets per register class or unit. 9827static const int RCSetsTable[] = { 9828 /* 0 */ 0, -1, 9829 /* 2 */ 1, -1, 9830 /* 4 */ 8, -1, 9831 /* 6 */ 11, -1, 9832 /* 8 */ 12, -1, 9833 /* 10 */ 16, -1, 9834 /* 12 */ 18, -1, 9835 /* 14 */ 17, 31, -1, 9836 /* 17 */ 19, 27, 28, 32, -1, 9837 /* 22 */ 2, 3, 15, 19, 21, 22, 27, 28, 32, -1, 9838 /* 32 */ 2, 6, 7, 19, 23, 27, 28, 32, -1, 9839 /* 41 */ 3, 7, 15, 19, 21, 26, 27, 28, 32, -1, 9840 /* 51 */ 2, 3, 6, 7, 15, 19, 21, 22, 23, 26, 27, 28, 32, -1, 9841 /* 65 */ 20, 21, 25, 28, 29, 32, -1, 9842 /* 72 */ 25, 28, 30, 32, -1, 9843 /* 77 */ 4, 5, 9, 10, 13, 19, 24, 27, 28, 30, 32, -1, 9844 /* 89 */ 19, 25, 27, 28, 30, 32, -1, 9845 /* 96 */ 5, 6, 19, 24, 25, 27, 28, 30, 32, -1, 9846 /* 106 */ 4, 5, 6, 9, 10, 13, 19, 24, 25, 27, 28, 30, 32, -1, 9847 /* 120 */ 2, 5, 6, 7, 19, 23, 24, 25, 27, 28, 30, 32, -1, 9848 /* 133 */ 22, 23, 24, 26, 27, 29, 30, 32, -1, 9849 /* 142 */ 20, 21, 25, 28, 29, 30, 32, -1, 9850 /* 150 */ 14, 15, 19, 20, 21, 25, 27, 28, 29, 30, 32, -1, 9851 /* 162 */ 2, 3, 14, 15, 19, 20, 21, 22, 25, 27, 28, 29, 30, 32, -1, 9852 /* 177 */ 4, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1, 9853 /* 192 */ 9, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1, 9854 /* 207 */ 4, 5, 9, 10, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1, 9855 /* 225 */ 2, 3, 6, 7, 15, 19, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1, 9856 /* 242 */ 3, 7, 14, 15, 19, 20, 21, 25, 26, 27, 28, 29, 30, 32, -1, 9857 /* 257 */ 2, 5, 6, 7, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9858 /* 273 */ 4, 5, 6, 9, 10, 13, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9859 /* 291 */ 2, 3, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9860 /* 309 */ 4, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9861 /* 327 */ 4, 9, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9862 /* 346 */ 4, 10, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1, 9863}; 9864 9865/// Get the dimensions of register pressure impacted by this register class. 9866/// Returns a -1 terminated array of pressure set IDs 9867const int* X86GenRegisterInfo:: 9868getRegClassPressureSets(const TargetRegisterClass *RC) const { 9869 static const uint16_t RCSetStartTable[] = { 9870 133,1,178,192,210,1,20,17,6,6,6,6,6,6,6,6,6,6,2,178,1,6,6,6,6,6,6,15,20,20,20,10,14,20,20,17,17,6,17,4,6,178,164,310,310,22,77,177,310,32,96,41,1,1,207,310,51,162,106,309,120,51,242,4,15,20,12,14,20,20,72,17,65,72,72,65,142,17,6,8,17,89,65,142,6,142,89,98,150,178,164,310,310,41,22,77,177,310,32,96,242,207,310,51,162,106,309,120,1,4,1,15,14,0,15,14,15,14,}; 9871 return &RCSetsTable[RCSetStartTable[RC->getID()]]; 9872} 9873 9874/// Get the dimensions of register pressure impacted by this register unit. 9875/// Returns a -1 terminated array of pressure set IDs 9876const int* X86GenRegisterInfo:: 9877getRegUnitPressureSets(unsigned RegUnit) const { 9878 assert(RegUnit < 164 && "invalid register unit"); 9879 static const uint16_t RUSetStartTable[] = { 9880 328,347,207,207,225,1,327,346,2,1,328,257,1,347,2,1,1,1,1,1,1,1,242,1,1,2,273,1,1,291,1,1,1,1,2,2,1,1,2,1,0,0,0,0,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,4,4,4,4,4,4,4,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,296,1,1,296,1,1,296,1,1,296,1,1,133,1,1,133,1,1,133,1,1,133,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,}; 9881 return &RCSetsTable[RUSetStartTable[RegUnit]]; 9882} 9883 9884extern const MCRegisterDesc X86RegDesc[]; 9885extern const MCPhysReg X86RegDiffLists[]; 9886extern const LaneBitmask X86LaneMaskLists[]; 9887extern const char X86RegStrings[]; 9888extern const char X86RegClassStrings[]; 9889extern const MCPhysReg X86RegUnitRoots[][2]; 9890extern const uint16_t X86SubRegIdxLists[]; 9891extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[]; 9892extern const uint16_t X86RegEncodingTable[]; 9893// X86 Dwarf<->LLVM register mappings. 9894extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[]; 9895extern const unsigned X86DwarfFlavour0Dwarf2LSize; 9896 9897extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[]; 9898extern const unsigned X86DwarfFlavour1Dwarf2LSize; 9899 9900extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[]; 9901extern const unsigned X86DwarfFlavour2Dwarf2LSize; 9902 9903extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[]; 9904extern const unsigned X86EHFlavour0Dwarf2LSize; 9905 9906extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[]; 9907extern const unsigned X86EHFlavour1Dwarf2LSize; 9908 9909extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[]; 9910extern const unsigned X86EHFlavour2Dwarf2LSize; 9911 9912extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[]; 9913extern const unsigned X86DwarfFlavour0L2DwarfSize; 9914 9915extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[]; 9916extern const unsigned X86DwarfFlavour1L2DwarfSize; 9917 9918extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[]; 9919extern const unsigned X86DwarfFlavour2L2DwarfSize; 9920 9921extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[]; 9922extern const unsigned X86EHFlavour0L2DwarfSize; 9923 9924extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[]; 9925extern const unsigned X86EHFlavour1L2DwarfSize; 9926 9927extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[]; 9928extern const unsigned X86EHFlavour2L2DwarfSize; 9929 9930X86GenRegisterInfo:: 9931X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, 9932 unsigned PC, unsigned HwMode) 9933 : TargetRegisterInfo(X86RegInfoDesc, RegisterClasses, RegisterClasses+118, 9934 SubRegIndexNameTable, SubRegIndexLaneMaskTable, 9935 LaneBitmask(0xFFFFFFB0), RegClassInfos, HwMode) { 9936 InitMCRegisterInfo(X86RegDesc, 283, RA, PC, 9937 X86MCRegisterClasses, 118, 9938 X86RegUnitRoots, 9939 164, 9940 X86RegDiffLists, 9941 X86LaneMaskLists, 9942 X86RegStrings, 9943 X86RegClassStrings, 9944 X86SubRegIdxLists, 9945 11, 9946 X86SubRegIdxRanges, 9947 X86RegEncodingTable); 9948 9949 switch (DwarfFlavour) { 9950 default: 9951 llvm_unreachable("Unknown DWARF flavour"); 9952 case 0: 9953 mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false); 9954 break; 9955 case 1: 9956 mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false); 9957 break; 9958 case 2: 9959 mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false); 9960 break; 9961 } 9962 switch (EHFlavour) { 9963 default: 9964 llvm_unreachable("Unknown DWARF flavour"); 9965 case 0: 9966 mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true); 9967 break; 9968 case 1: 9969 mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true); 9970 break; 9971 case 2: 9972 mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true); 9973 break; 9974 } 9975 switch (DwarfFlavour) { 9976 default: 9977 llvm_unreachable("Unknown DWARF flavour"); 9978 case 0: 9979 mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false); 9980 break; 9981 case 1: 9982 mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false); 9983 break; 9984 case 2: 9985 mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false); 9986 break; 9987 } 9988 switch (EHFlavour) { 9989 default: 9990 llvm_unreachable("Unknown DWARF flavour"); 9991 case 0: 9992 mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true); 9993 break; 9994 case 1: 9995 mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true); 9996 break; 9997 case 2: 9998 mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true); 9999 break; 10000 } 10001} 10002 10003static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 }; 10004static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0x38002581, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10005static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 }; 10006static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0x38002dc1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10007static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 }; 10008static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10009static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 }; 10010static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x007f8000, 0x007f8000, 0x00000000, 0x00000000, 0x00000000, }; 10011static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 }; 10012static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x007f8000, 0x007f8000, 0x007f8000, 0x007f8000, 0x00000000, 0x07800000, }; 10013static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 }; 10014static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x007f8000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10015static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 }; 10016static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xf8006583, 0x00000001, 0x00000000, 0x00780000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10017static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 0 }; 10018static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xf8006583, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10019static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 }; 10020static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10021static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 }; 10022static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x004e09c0, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10023static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 }; 10024static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x7fff807f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, }; 10025static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 }; 10026static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x7fff807f, 0x7fff8000, 0x00000000, 0xffff8000, 0x007fffff, }; 10027static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 }; 10028static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x807f8000, 0xffff807f, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, }; 10029static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 }; 10030static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, }; 10031static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 }; 10032static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00040080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10033static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 }; 10034static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0x3a582b01, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, }; 10035static const MCPhysReg CSR_64_HHVM_SaveList[] = { X86::R12, 0 }; 10036static const uint32_t CSR_64_HHVM_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x08080000, 0x00080808, }; 10037static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10038static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x7f800078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10039static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 }; 10040static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x7f800078, 0x7f800000, 0x00000000, 0x78780000, 0x00787878, }; 10041static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RDI, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 }; 10042static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x05070230, 0x3a282501, 0x00000000, 0x00780000, 0x80000060, 0x80007fff, 0x80007fff, 0x60607fff, 0x06606060, }; 10043static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10044static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0x3a7c2f81, 0x00000000, 0x80000000, 0x7fff807f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, }; 10045static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10046static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x7fff807b, 0x00000000, 0x00000000, 0xfbfb8000, 0x007bfbfb, }; 10047static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 }; 10048static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x7fff807b, 0x7fff8000, 0x00000000, 0xfbfb8000, 0x007bfbfb, }; 10049static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 }; 10050static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x0000007b, 0x00000000, 0x00000000, 0xfbfb8000, 0x007bfbfb, }; 10051static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 }; 10052static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x00000070, 0x00000000, 0x00000000, 0x70700000, 0x00707070, }; 10053static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 }; 10054static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0x3a5c2b81, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, }; 10055static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; 10056static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10057static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10058static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x7f800078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10059static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, 0 }; 10060static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10061static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 }; 10062static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xf8006783, 0x00000001, 0x00000000, 0x00780000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10063static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::ECX, 0 }; 10064static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xf8006783, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 10065static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10066static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10067static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 }; 10068static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00078, 0x7fe00000, 0x00000000, 0x78780000, 0x00787878, }; 10069static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 }; 10070static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00780000, 0xffe00078, 0xffe0001f, 0xffe0001f, 0x7878001f, 0x06787878, }; 10071static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 }; 10072static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, }; 10073static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10074static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x7f80007e, 0x00000000, 0x00000000, 0x7e7e0000, 0x007e7e7e, }; 10075static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 }; 10076static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x0000007e, 0x00000000, 0x00000000, 0x7e7e0000, 0x007e7e7e, }; 10077static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 }; 10078static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00070, 0x00000000, 0x00000000, 0x70700000, 0x00707070, }; 10079 10080 10081ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const { 10082 static const uint32_t *const Masks[] = { 10083 CSR_32_RegMask, 10084 CSR_32EHRet_RegMask, 10085 CSR_32_AllRegs_RegMask, 10086 CSR_32_AllRegs_AVX_RegMask, 10087 CSR_32_AllRegs_AVX512_RegMask, 10088 CSR_32_AllRegs_SSE_RegMask, 10089 CSR_32_RegCall_RegMask, 10090 CSR_32_RegCall_NoSSE_RegMask, 10091 CSR_64_RegMask, 10092 CSR_64EHRet_RegMask, 10093 CSR_64_AllRegs_RegMask, 10094 CSR_64_AllRegs_AVX_RegMask, 10095 CSR_64_AllRegs_AVX512_RegMask, 10096 CSR_64_AllRegs_NoSSE_RegMask, 10097 CSR_64_CXX_TLS_Darwin_PE_RegMask, 10098 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask, 10099 CSR_64_HHVM_RegMask, 10100 CSR_64_Intel_OCL_BI_RegMask, 10101 CSR_64_Intel_OCL_BI_AVX_RegMask, 10102 CSR_64_Intel_OCL_BI_AVX512_RegMask, 10103 CSR_64_MostRegs_RegMask, 10104 CSR_64_RT_AllRegs_RegMask, 10105 CSR_64_RT_AllRegs_AVX_RegMask, 10106 CSR_64_RT_MostRegs_RegMask, 10107 CSR_64_SwiftError_RegMask, 10108 CSR_64_TLS_Darwin_RegMask, 10109 CSR_NoRegs_RegMask, 10110 CSR_SysV64_RegCall_RegMask, 10111 CSR_SysV64_RegCall_NoSSE_RegMask, 10112 CSR_Win32_CFGuard_Check_RegMask, 10113 CSR_Win32_CFGuard_Check_NoSSE_RegMask, 10114 CSR_Win64_RegMask, 10115 CSR_Win64_Intel_OCL_BI_AVX_RegMask, 10116 CSR_Win64_Intel_OCL_BI_AVX512_RegMask, 10117 CSR_Win64_NoSSE_RegMask, 10118 CSR_Win64_RegCall_RegMask, 10119 CSR_Win64_RegCall_NoSSE_RegMask, 10120 CSR_Win64_SwiftError_RegMask, 10121 }; 10122 return makeArrayRef(Masks); 10123} 10124 10125ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const { 10126 static const char *const Names[] = { 10127 "CSR_32", 10128 "CSR_32EHRet", 10129 "CSR_32_AllRegs", 10130 "CSR_32_AllRegs_AVX", 10131 "CSR_32_AllRegs_AVX512", 10132 "CSR_32_AllRegs_SSE", 10133 "CSR_32_RegCall", 10134 "CSR_32_RegCall_NoSSE", 10135 "CSR_64", 10136 "CSR_64EHRet", 10137 "CSR_64_AllRegs", 10138 "CSR_64_AllRegs_AVX", 10139 "CSR_64_AllRegs_AVX512", 10140 "CSR_64_AllRegs_NoSSE", 10141 "CSR_64_CXX_TLS_Darwin_PE", 10142 "CSR_64_CXX_TLS_Darwin_ViaCopy", 10143 "CSR_64_HHVM", 10144 "CSR_64_Intel_OCL_BI", 10145 "CSR_64_Intel_OCL_BI_AVX", 10146 "CSR_64_Intel_OCL_BI_AVX512", 10147 "CSR_64_MostRegs", 10148 "CSR_64_RT_AllRegs", 10149 "CSR_64_RT_AllRegs_AVX", 10150 "CSR_64_RT_MostRegs", 10151 "CSR_64_SwiftError", 10152 "CSR_64_TLS_Darwin", 10153 "CSR_NoRegs", 10154 "CSR_SysV64_RegCall", 10155 "CSR_SysV64_RegCall_NoSSE", 10156 "CSR_Win32_CFGuard_Check", 10157 "CSR_Win32_CFGuard_Check_NoSSE", 10158 "CSR_Win64", 10159 "CSR_Win64_Intel_OCL_BI_AVX", 10160 "CSR_Win64_Intel_OCL_BI_AVX512", 10161 "CSR_Win64_NoSSE", 10162 "CSR_Win64_RegCall", 10163 "CSR_Win64_RegCall_NoSSE", 10164 "CSR_Win64_SwiftError", 10165 }; 10166 return makeArrayRef(Names); 10167} 10168 10169const X86FrameLowering * 10170X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) { 10171 return static_cast<const X86FrameLowering *>( 10172 MF.getSubtarget().getFrameLowering()); 10173} 10174 10175} // end namespace llvm 10176 10177#endif // GET_REGINFO_TARGET_DESC 10178 10179