1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, please consult code owner before editing.
9//===----------------------------------------------------------------------===//
10
11class Enc_890909 : OpcodeHexagon {
12  bits <5> Rs32;
13  let Inst{20-16} = Rs32{4-0};
14  bits <5> Rd32;
15  let Inst{4-0} = Rd32{4-0};
16  bits <2> Pe4;
17  let Inst{6-5} = Pe4{1-0};
18}
19class Enc_9be1de : OpcodeHexagon {
20  bits <2> Qs4;
21  let Inst{6-5} = Qs4{1-0};
22  bits <5> Rt32;
23  let Inst{20-16} = Rt32{4-0};
24  bits <1> Mu2;
25  let Inst{13-13} = Mu2{0-0};
26  bits <5> Vv32;
27  let Inst{12-8} = Vv32{4-0};
28  bits <5> Vw32;
29  let Inst{4-0} = Vw32{4-0};
30}
31class Enc_527412 : OpcodeHexagon {
32  bits <2> Ps4;
33  let Inst{17-16} = Ps4{1-0};
34  bits <2> Pt4;
35  let Inst{9-8} = Pt4{1-0};
36  bits <5> Rd32;
37  let Inst{4-0} = Rd32{4-0};
38}
39class Enc_efaed8 : OpcodeHexagon {
40  bits <1> Ii;
41  let Inst{8-8} = Ii{0-0};
42}
43class Enc_a568d4 : OpcodeHexagon {
44  bits <5> Rt32;
45  let Inst{12-8} = Rt32{4-0};
46  bits <5> Rs32;
47  let Inst{20-16} = Rs32{4-0};
48  bits <5> Rx32;
49  let Inst{4-0} = Rx32{4-0};
50}
51class Enc_27b757 : OpcodeHexagon {
52  bits <4> Ii;
53  let Inst{13-13} = Ii{3-3};
54  let Inst{10-8} = Ii{2-0};
55  bits <2> Pv4;
56  let Inst{12-11} = Pv4{1-0};
57  bits <5> Rt32;
58  let Inst{20-16} = Rt32{4-0};
59  bits <5> Vs32;
60  let Inst{4-0} = Vs32{4-0};
61}
62class Enc_1de724 : OpcodeHexagon {
63  bits <11> Ii;
64  let Inst{21-20} = Ii{10-9};
65  let Inst{7-1} = Ii{8-2};
66  bits <4> Rs16;
67  let Inst{19-16} = Rs16{3-0};
68  bits <4> n1;
69  let Inst{28-28} = n1{3-3};
70  let Inst{24-22} = n1{2-0};
71}
72class Enc_0e41fa : OpcodeHexagon {
73  bits <5> Vuu32;
74  let Inst{12-8} = Vuu32{4-0};
75  bits <5> Rt32;
76  let Inst{20-16} = Rt32{4-0};
77  bits <5> Vd32;
78  let Inst{4-0} = Vd32{4-0};
79}
80class Enc_3d6d37 : OpcodeHexagon {
81  bits <2> Qs4;
82  let Inst{6-5} = Qs4{1-0};
83  bits <5> Rt32;
84  let Inst{20-16} = Rt32{4-0};
85  bits <1> Mu2;
86  let Inst{13-13} = Mu2{0-0};
87  bits <5> Vvv32;
88  let Inst{12-8} = Vvv32{4-0};
89  bits <5> Vw32;
90  let Inst{4-0} = Vw32{4-0};
91}
92class Enc_a641d0 : OpcodeHexagon {
93  bits <5> Rt32;
94  let Inst{20-16} = Rt32{4-0};
95  bits <1> Mu2;
96  let Inst{13-13} = Mu2{0-0};
97  bits <5> Vvv32;
98  let Inst{12-8} = Vvv32{4-0};
99  bits <5> Vw32;
100  let Inst{4-0} = Vw32{4-0};
101}
102class Enc_802dc0 : OpcodeHexagon {
103  bits <1> Ii;
104  let Inst{8-8} = Ii{0-0};
105  bits <2> Qv4;
106  let Inst{23-22} = Qv4{1-0};
107}
108class Enc_6b197f : OpcodeHexagon {
109  bits <4> Ii;
110  let Inst{8-5} = Ii{3-0};
111  bits <5> Ryy32;
112  let Inst{4-0} = Ryy32{4-0};
113  bits <5> Rx32;
114  let Inst{20-16} = Rx32{4-0};
115}
116class Enc_51436c : OpcodeHexagon {
117  bits <16> Ii;
118  let Inst{23-22} = Ii{15-14};
119  let Inst{13-0} = Ii{13-0};
120  bits <5> Rx32;
121  let Inst{20-16} = Rx32{4-0};
122}
123class Enc_c7a204 : OpcodeHexagon {
124  bits <6> II;
125  let Inst{5-0} = II{5-0};
126  bits <5> Rtt32;
127  let Inst{12-8} = Rtt32{4-0};
128  bits <5> Re32;
129  let Inst{20-16} = Re32{4-0};
130}
131class Enc_db40cd : OpcodeHexagon {
132  bits <6> Ii;
133  let Inst{6-3} = Ii{5-2};
134  bits <5> Rt32;
135  let Inst{12-8} = Rt32{4-0};
136  bits <5> Rx32;
137  let Inst{20-16} = Rx32{4-0};
138}
139class Enc_a1e29d : OpcodeHexagon {
140  bits <5> Ii;
141  let Inst{12-8} = Ii{4-0};
142  bits <5> II;
143  let Inst{22-21} = II{4-3};
144  let Inst{7-5} = II{2-0};
145  bits <5> Rs32;
146  let Inst{20-16} = Rs32{4-0};
147  bits <5> Rx32;
148  let Inst{4-0} = Rx32{4-0};
149}
150class Enc_d15d19 : OpcodeHexagon {
151  bits <1> Mu2;
152  let Inst{13-13} = Mu2{0-0};
153  bits <5> Vs32;
154  let Inst{4-0} = Vs32{4-0};
155  bits <5> Rx32;
156  let Inst{20-16} = Rx32{4-0};
157}
158class Enc_e90a15 : OpcodeHexagon {
159  bits <11> Ii;
160  let Inst{21-20} = Ii{10-9};
161  let Inst{7-1} = Ii{8-2};
162  bits <3> Ns8;
163  let Inst{18-16} = Ns8{2-0};
164  bits <4> n1;
165  let Inst{29-29} = n1{3-3};
166  let Inst{26-25} = n1{2-1};
167  let Inst{22-22} = n1{0-0};
168}
169class Enc_e0a47a : OpcodeHexagon {
170  bits <4> Ii;
171  let Inst{8-5} = Ii{3-0};
172  bits <1> Mu2;
173  let Inst{13-13} = Mu2{0-0};
174  bits <5> Rd32;
175  let Inst{4-0} = Rd32{4-0};
176  bits <5> Rx32;
177  let Inst{20-16} = Rx32{4-0};
178}
179class Enc_140c83 : OpcodeHexagon {
180  bits <10> Ii;
181  let Inst{21-21} = Ii{9-9};
182  let Inst{13-5} = Ii{8-0};
183  bits <5> Rs32;
184  let Inst{20-16} = Rs32{4-0};
185  bits <5> Rd32;
186  let Inst{4-0} = Rd32{4-0};
187}
188class Enc_7eee72 : OpcodeHexagon {
189  bits <1> Mu2;
190  let Inst{13-13} = Mu2{0-0};
191  bits <5> Rdd32;
192  let Inst{4-0} = Rdd32{4-0};
193  bits <5> Rx32;
194  let Inst{20-16} = Rx32{4-0};
195}
196class Enc_310ba1 : OpcodeHexagon {
197  bits <5> Vu32;
198  let Inst{12-8} = Vu32{4-0};
199  bits <5> Rtt32;
200  let Inst{20-16} = Rtt32{4-0};
201  bits <5> Vx32;
202  let Inst{4-0} = Vx32{4-0};
203}
204class Enc_d7dc10 : OpcodeHexagon {
205  bits <5> Rs32;
206  let Inst{20-16} = Rs32{4-0};
207  bits <5> Rtt32;
208  let Inst{12-8} = Rtt32{4-0};
209  bits <2> Pd4;
210  let Inst{1-0} = Pd4{1-0};
211}
212class Enc_6baed4 : OpcodeHexagon {
213  bits <3> Ii;
214  let Inst{10-8} = Ii{2-0};
215  bits <2> Pv4;
216  let Inst{12-11} = Pv4{1-0};
217  bits <5> Rx32;
218  let Inst{20-16} = Rx32{4-0};
219}
220class Enc_736575 : OpcodeHexagon {
221  bits <11> Ii;
222  let Inst{21-20} = Ii{10-9};
223  let Inst{7-1} = Ii{8-2};
224  bits <4> Rs16;
225  let Inst{19-16} = Rs16{3-0};
226  bits <4> n1;
227  let Inst{28-28} = n1{3-3};
228  let Inst{25-23} = n1{2-0};
229}
230class Enc_8dec2e : OpcodeHexagon {
231  bits <5> Ii;
232  let Inst{12-8} = Ii{4-0};
233  bits <5> Rss32;
234  let Inst{20-16} = Rss32{4-0};
235  bits <5> Rd32;
236  let Inst{4-0} = Rd32{4-0};
237}
238class Enc_28dcbb : OpcodeHexagon {
239  bits <5> Rt32;
240  let Inst{20-16} = Rt32{4-0};
241  bits <1> Mu2;
242  let Inst{13-13} = Mu2{0-0};
243  bits <5> Vvv32;
244  let Inst{4-0} = Vvv32{4-0};
245}
246class Enc_eaa9f8 : OpcodeHexagon {
247  bits <5> Vu32;
248  let Inst{12-8} = Vu32{4-0};
249  bits <5> Vv32;
250  let Inst{20-16} = Vv32{4-0};
251  bits <2> Qx4;
252  let Inst{1-0} = Qx4{1-0};
253}
254class Enc_509701 : OpcodeHexagon {
255  bits <19> Ii;
256  let Inst{26-25} = Ii{18-17};
257  let Inst{20-16} = Ii{16-12};
258  let Inst{13-5} = Ii{11-3};
259  bits <5> Rdd32;
260  let Inst{4-0} = Rdd32{4-0};
261}
262class Enc_830e5d : OpcodeHexagon {
263  bits <8> Ii;
264  let Inst{12-5} = Ii{7-0};
265  bits <8> II;
266  let Inst{22-16} = II{7-1};
267  let Inst{13-13} = II{0-0};
268  bits <2> Pu4;
269  let Inst{24-23} = Pu4{1-0};
270  bits <5> Rd32;
271  let Inst{4-0} = Rd32{4-0};
272}
273class Enc_79b8c8 : OpcodeHexagon {
274  bits <6> Ii;
275  let Inst{6-3} = Ii{5-2};
276  bits <1> Mu2;
277  let Inst{13-13} = Mu2{0-0};
278  bits <5> Rt32;
279  let Inst{12-8} = Rt32{4-0};
280  bits <5> Rx32;
281  let Inst{20-16} = Rx32{4-0};
282}
283class Enc_58a8bf : OpcodeHexagon {
284  bits <3> Ii;
285  let Inst{10-8} = Ii{2-0};
286  bits <2> Pv4;
287  let Inst{12-11} = Pv4{1-0};
288  bits <5> Vd32;
289  let Inst{4-0} = Vd32{4-0};
290  bits <5> Rx32;
291  let Inst{20-16} = Rx32{4-0};
292}
293class Enc_041d7b : OpcodeHexagon {
294  bits <11> Ii;
295  let Inst{21-20} = Ii{10-9};
296  let Inst{7-1} = Ii{8-2};
297  bits <4> Rs16;
298  let Inst{19-16} = Rs16{3-0};
299  bits <5> n1;
300  let Inst{28-28} = n1{4-4};
301  let Inst{24-23} = n1{3-2};
302  let Inst{13-13} = n1{1-1};
303  let Inst{8-8} = n1{0-0};
304}
305class Enc_f44229 : OpcodeHexagon {
306  bits <7> Ii;
307  let Inst{13-13} = Ii{6-6};
308  let Inst{7-3} = Ii{5-1};
309  bits <2> Pv4;
310  let Inst{1-0} = Pv4{1-0};
311  bits <5> Rs32;
312  let Inst{20-16} = Rs32{4-0};
313  bits <3> Nt8;
314  let Inst{10-8} = Nt8{2-0};
315}
316class Enc_aad80c : OpcodeHexagon {
317  bits <5> Vuu32;
318  let Inst{12-8} = Vuu32{4-0};
319  bits <5> Rt32;
320  let Inst{20-16} = Rt32{4-0};
321  bits <5> Vdd32;
322  let Inst{4-0} = Vdd32{4-0};
323}
324class Enc_87c142 : OpcodeHexagon {
325  bits <7> Ii;
326  let Inst{8-4} = Ii{6-2};
327  bits <4> Rt16;
328  let Inst{3-0} = Rt16{3-0};
329}
330class Enc_86a14b : OpcodeHexagon {
331  bits <8> Ii;
332  let Inst{7-3} = Ii{7-3};
333  bits <3> Rdd8;
334  let Inst{2-0} = Rdd8{2-0};
335}
336class Enc_9a33d5 : OpcodeHexagon {
337  bits <7> Ii;
338  let Inst{6-3} = Ii{6-3};
339  bits <2> Pv4;
340  let Inst{1-0} = Pv4{1-0};
341  bits <5> Rtt32;
342  let Inst{12-8} = Rtt32{4-0};
343  bits <5> Rx32;
344  let Inst{20-16} = Rx32{4-0};
345}
346class Enc_a56825 : OpcodeHexagon {
347  bits <5> Rss32;
348  let Inst{20-16} = Rss32{4-0};
349  bits <5> Rtt32;
350  let Inst{12-8} = Rtt32{4-0};
351  bits <5> Rdd32;
352  let Inst{4-0} = Rdd32{4-0};
353}
354class Enc_9ea4cf : OpcodeHexagon {
355  bits <2> Ii;
356  let Inst{13-13} = Ii{1-1};
357  let Inst{6-6} = Ii{0-0};
358  bits <6> II;
359  let Inst{5-0} = II{5-0};
360  bits <5> Ru32;
361  let Inst{20-16} = Ru32{4-0};
362  bits <5> Rt32;
363  let Inst{12-8} = Rt32{4-0};
364}
365class Enc_ee5ed0 : OpcodeHexagon {
366  bits <4> Rs16;
367  let Inst{7-4} = Rs16{3-0};
368  bits <4> Rd16;
369  let Inst{3-0} = Rd16{3-0};
370  bits <2> n1;
371  let Inst{9-8} = n1{1-0};
372}
373class Enc_bddee3 : OpcodeHexagon {
374  bits <5> Vu32;
375  let Inst{12-8} = Vu32{4-0};
376  bits <5> Vyyyy32;
377  let Inst{4-0} = Vyyyy32{4-0};
378  bits <3> Rx8;
379  let Inst{18-16} = Rx8{2-0};
380}
381class Enc_935d9b : OpcodeHexagon {
382  bits <5> Ii;
383  let Inst{6-3} = Ii{4-1};
384  bits <1> Mu2;
385  let Inst{13-13} = Mu2{0-0};
386  bits <5> Rt32;
387  let Inst{12-8} = Rt32{4-0};
388  bits <5> Rx32;
389  let Inst{20-16} = Rx32{4-0};
390}
391class Enc_61f0b0 : OpcodeHexagon {
392  bits <5> Rs32;
393  let Inst{20-16} = Rs32{4-0};
394  bits <5> Rt32;
395  let Inst{12-8} = Rt32{4-0};
396  bits <5> Rxx32;
397  let Inst{4-0} = Rxx32{4-0};
398}
399class Enc_bd6011 : OpcodeHexagon {
400  bits <5> Rt32;
401  let Inst{12-8} = Rt32{4-0};
402  bits <5> Rs32;
403  let Inst{20-16} = Rs32{4-0};
404  bits <5> Rd32;
405  let Inst{4-0} = Rd32{4-0};
406}
407class Enc_65d691 : OpcodeHexagon {
408  bits <2> Ps4;
409  let Inst{17-16} = Ps4{1-0};
410  bits <2> Pd4;
411  let Inst{1-0} = Pd4{1-0};
412}
413class Enc_e8c45e : OpcodeHexagon {
414  bits <7> Ii;
415  let Inst{13-13} = Ii{6-6};
416  let Inst{7-3} = Ii{5-1};
417  bits <2> Pv4;
418  let Inst{1-0} = Pv4{1-0};
419  bits <5> Rs32;
420  let Inst{20-16} = Rs32{4-0};
421  bits <5> Rt32;
422  let Inst{12-8} = Rt32{4-0};
423}
424class Enc_ca3887 : OpcodeHexagon {
425  bits <5> Rs32;
426  let Inst{20-16} = Rs32{4-0};
427  bits <5> Rt32;
428  let Inst{12-8} = Rt32{4-0};
429}
430class Enc_a94f3b : OpcodeHexagon {
431  bits <5> Rs32;
432  let Inst{20-16} = Rs32{4-0};
433  bits <5> Rt32;
434  let Inst{12-8} = Rt32{4-0};
435  bits <5> Rd32;
436  let Inst{4-0} = Rd32{4-0};
437  bits <2> Pe4;
438  let Inst{6-5} = Pe4{1-0};
439}
440class Enc_625deb : OpcodeHexagon {
441  bits <4> Ii;
442  let Inst{10-8} = Ii{3-1};
443  bits <4> Rs16;
444  let Inst{7-4} = Rs16{3-0};
445  bits <4> Rt16;
446  let Inst{3-0} = Rt16{3-0};
447}
448class Enc_1f5ba6 : OpcodeHexagon {
449  bits <4> Rd16;
450  let Inst{3-0} = Rd16{3-0};
451}
452class Enc_cd82bc : OpcodeHexagon {
453  bits <4> Ii;
454  let Inst{21-21} = Ii{3-3};
455  let Inst{7-5} = Ii{2-0};
456  bits <6> II;
457  let Inst{13-8} = II{5-0};
458  bits <5> Rs32;
459  let Inst{20-16} = Rs32{4-0};
460  bits <5> Rx32;
461  let Inst{4-0} = Rx32{4-0};
462}
463class Enc_399e12 : OpcodeHexagon {
464  bits <4> Rs16;
465  let Inst{7-4} = Rs16{3-0};
466  bits <3> Rdd8;
467  let Inst{2-0} = Rdd8{2-0};
468}
469class Enc_d7a65e : OpcodeHexagon {
470  bits <6> Ii;
471  let Inst{12-7} = Ii{5-0};
472  bits <6> II;
473  let Inst{13-13} = II{5-5};
474  let Inst{4-0} = II{4-0};
475  bits <2> Pv4;
476  let Inst{6-5} = Pv4{1-0};
477  bits <5> Rs32;
478  let Inst{20-16} = Rs32{4-0};
479}
480class Enc_607661 : OpcodeHexagon {
481  bits <6> Ii;
482  let Inst{12-7} = Ii{5-0};
483  bits <5> Rd32;
484  let Inst{4-0} = Rd32{4-0};
485}
486class Enc_6a5972 : OpcodeHexagon {
487  bits <11> Ii;
488  let Inst{21-20} = Ii{10-9};
489  let Inst{7-1} = Ii{8-2};
490  bits <4> Rs16;
491  let Inst{19-16} = Rs16{3-0};
492  bits <4> Rt16;
493  let Inst{11-8} = Rt16{3-0};
494}
495class Enc_ff3442 : OpcodeHexagon {
496  bits <4> Ii;
497  let Inst{13-13} = Ii{3-3};
498  let Inst{10-8} = Ii{2-0};
499  bits <5> Rt32;
500  let Inst{20-16} = Rt32{4-0};
501}
502class Enc_53dca9 : OpcodeHexagon {
503  bits <6> Ii;
504  let Inst{11-8} = Ii{5-2};
505  bits <4> Rs16;
506  let Inst{7-4} = Rs16{3-0};
507  bits <4> Rd16;
508  let Inst{3-0} = Rd16{3-0};
509}
510class Enc_27fd0e : OpcodeHexagon {
511  bits <6> Ii;
512  let Inst{8-5} = Ii{5-2};
513  bits <1> Mu2;
514  let Inst{13-13} = Mu2{0-0};
515  bits <5> Rd32;
516  let Inst{4-0} = Rd32{4-0};
517  bits <5> Rx32;
518  let Inst{20-16} = Rx32{4-0};
519}
520class Enc_d7bc34 : OpcodeHexagon {
521  bits <5> Vu32;
522  let Inst{12-8} = Vu32{4-0};
523  bits <3> Rt8;
524  let Inst{18-16} = Rt8{2-0};
525  bits <5> Vyyyy32;
526  let Inst{4-0} = Vyyyy32{4-0};
527}
528class Enc_93af4c : OpcodeHexagon {
529  bits <7> Ii;
530  let Inst{10-4} = Ii{6-0};
531  bits <4> Rx16;
532  let Inst{3-0} = Rx16{3-0};
533}
534class Enc_621fba : OpcodeHexagon {
535  bits <5> Rs32;
536  let Inst{20-16} = Rs32{4-0};
537  bits <5> Gd32;
538  let Inst{4-0} = Gd32{4-0};
539}
540class Enc_5bdd42 : OpcodeHexagon {
541  bits <7> Ii;
542  let Inst{8-5} = Ii{6-3};
543  bits <5> Rdd32;
544  let Inst{4-0} = Rdd32{4-0};
545  bits <5> Rx32;
546  let Inst{20-16} = Rx32{4-0};
547}
548class Enc_ad9bef : OpcodeHexagon {
549  bits <5> Vu32;
550  let Inst{12-8} = Vu32{4-0};
551  bits <5> Rtt32;
552  let Inst{20-16} = Rtt32{4-0};
553  bits <5> Vxx32;
554  let Inst{4-0} = Vxx32{4-0};
555}
556class Enc_71f1b4 : OpcodeHexagon {
557  bits <6> Ii;
558  let Inst{8-5} = Ii{5-2};
559  bits <5> Rdd32;
560  let Inst{4-0} = Rdd32{4-0};
561  bits <5> Rx32;
562  let Inst{20-16} = Rx32{4-0};
563}
564class Enc_14640c : OpcodeHexagon {
565  bits <11> Ii;
566  let Inst{21-20} = Ii{10-9};
567  let Inst{7-1} = Ii{8-2};
568  bits <4> Rs16;
569  let Inst{19-16} = Rs16{3-0};
570  bits <5> n1;
571  let Inst{28-28} = n1{4-4};
572  let Inst{24-22} = n1{3-1};
573  let Inst{13-13} = n1{0-0};
574}
575class Enc_31db33 : OpcodeHexagon {
576  bits <2> Qt4;
577  let Inst{6-5} = Qt4{1-0};
578  bits <5> Vu32;
579  let Inst{12-8} = Vu32{4-0};
580  bits <5> Vv32;
581  let Inst{20-16} = Vv32{4-0};
582  bits <5> Vd32;
583  let Inst{4-0} = Vd32{4-0};
584}
585class Enc_65f095 : OpcodeHexagon {
586  bits <6> Ii;
587  let Inst{6-3} = Ii{5-2};
588  bits <2> Pv4;
589  let Inst{1-0} = Pv4{1-0};
590  bits <3> Nt8;
591  let Inst{10-8} = Nt8{2-0};
592  bits <5> Rx32;
593  let Inst{20-16} = Rx32{4-0};
594}
595class Enc_784502 : OpcodeHexagon {
596  bits <3> Ii;
597  let Inst{10-8} = Ii{2-0};
598  bits <2> Pv4;
599  let Inst{12-11} = Pv4{1-0};
600  bits <3> Os8;
601  let Inst{2-0} = Os8{2-0};
602  bits <5> Rx32;
603  let Inst{20-16} = Rx32{4-0};
604}
605class Enc_6413b6 : OpcodeHexagon {
606  bits <11> Ii;
607  let Inst{21-20} = Ii{10-9};
608  let Inst{7-1} = Ii{8-2};
609  bits <3> Ns8;
610  let Inst{18-16} = Ns8{2-0};
611  bits <5> n1;
612  let Inst{29-29} = n1{4-4};
613  let Inst{26-25} = n1{3-2};
614  let Inst{23-23} = n1{1-1};
615  let Inst{13-13} = n1{0-0};
616}
617class Enc_7a0ea6 : OpcodeHexagon {
618  bits <4> Rd16;
619  let Inst{3-0} = Rd16{3-0};
620  bits <1> n1;
621  let Inst{9-9} = n1{0-0};
622}
623class Enc_84bff1 : OpcodeHexagon {
624  bits <2> Ii;
625  let Inst{13-13} = Ii{1-1};
626  let Inst{7-7} = Ii{0-0};
627  bits <5> Rs32;
628  let Inst{20-16} = Rs32{4-0};
629  bits <5> Rt32;
630  let Inst{12-8} = Rt32{4-0};
631  bits <5> Rdd32;
632  let Inst{4-0} = Rdd32{4-0};
633}
634class Enc_f4413a : OpcodeHexagon {
635  bits <4> Ii;
636  let Inst{8-5} = Ii{3-0};
637  bits <2> Pt4;
638  let Inst{10-9} = Pt4{1-0};
639  bits <5> Rd32;
640  let Inst{4-0} = Rd32{4-0};
641  bits <5> Rx32;
642  let Inst{20-16} = Rx32{4-0};
643}
644class Enc_78e566 : OpcodeHexagon {
645  bits <2> Pt4;
646  let Inst{9-8} = Pt4{1-0};
647  bits <5> Rdd32;
648  let Inst{4-0} = Rdd32{4-0};
649}
650class Enc_437f33 : OpcodeHexagon {
651  bits <5> Rs32;
652  let Inst{20-16} = Rs32{4-0};
653  bits <5> Rt32;
654  let Inst{12-8} = Rt32{4-0};
655  bits <2> Pu4;
656  let Inst{6-5} = Pu4{1-0};
657  bits <5> Rx32;
658  let Inst{4-0} = Rx32{4-0};
659}
660class Enc_0527db : OpcodeHexagon {
661  bits <4> Rs16;
662  let Inst{7-4} = Rs16{3-0};
663  bits <4> Rx16;
664  let Inst{3-0} = Rx16{3-0};
665}
666class Enc_420cf3 : OpcodeHexagon {
667  bits <6> Ii;
668  let Inst{22-21} = Ii{5-4};
669  let Inst{13-13} = Ii{3-3};
670  let Inst{7-5} = Ii{2-0};
671  bits <5> Ru32;
672  let Inst{4-0} = Ru32{4-0};
673  bits <5> Rs32;
674  let Inst{20-16} = Rs32{4-0};
675  bits <5> Rd32;
676  let Inst{12-8} = Rd32{4-0};
677}
678class Enc_e39bb2 : OpcodeHexagon {
679  bits <6> Ii;
680  let Inst{9-4} = Ii{5-0};
681  bits <4> Rd16;
682  let Inst{3-0} = Rd16{3-0};
683}
684class Enc_1b64fb : OpcodeHexagon {
685  bits <16> Ii;
686  let Inst{26-25} = Ii{15-14};
687  let Inst{20-16} = Ii{13-9};
688  let Inst{13-13} = Ii{8-8};
689  let Inst{7-0} = Ii{7-0};
690  bits <5> Rt32;
691  let Inst{12-8} = Rt32{4-0};
692}
693class Enc_c1d806 : OpcodeHexagon {
694  bits <5> Vu32;
695  let Inst{12-8} = Vu32{4-0};
696  bits <5> Vv32;
697  let Inst{20-16} = Vv32{4-0};
698  bits <5> Vd32;
699  let Inst{4-0} = Vd32{4-0};
700  bits <2> Qe4;
701  let Inst{6-5} = Qe4{1-0};
702}
703class Enc_c6220b : OpcodeHexagon {
704  bits <2> Ii;
705  let Inst{13-13} = Ii{1-1};
706  let Inst{7-7} = Ii{0-0};
707  bits <5> Rs32;
708  let Inst{20-16} = Rs32{4-0};
709  bits <5> Ru32;
710  let Inst{12-8} = Ru32{4-0};
711  bits <3> Nt8;
712  let Inst{2-0} = Nt8{2-0};
713}
714class Enc_322e1b : OpcodeHexagon {
715  bits <6> Ii;
716  let Inst{22-21} = Ii{5-4};
717  let Inst{13-13} = Ii{3-3};
718  let Inst{7-5} = Ii{2-0};
719  bits <6> II;
720  let Inst{23-23} = II{5-5};
721  let Inst{4-0} = II{4-0};
722  bits <5> Rs32;
723  let Inst{20-16} = Rs32{4-0};
724  bits <5> Rd32;
725  let Inst{12-8} = Rd32{4-0};
726}
727class Enc_989021 : OpcodeHexagon {
728  bits <5> Rt32;
729  let Inst{20-16} = Rt32{4-0};
730  bits <5> Vy32;
731  let Inst{12-8} = Vy32{4-0};
732  bits <5> Vx32;
733  let Inst{4-0} = Vx32{4-0};
734}
735class Enc_178717 : OpcodeHexagon {
736  bits <11> Ii;
737  let Inst{21-20} = Ii{10-9};
738  let Inst{7-1} = Ii{8-2};
739  bits <4> Rs16;
740  let Inst{19-16} = Rs16{3-0};
741  bits <6> n1;
742  let Inst{28-28} = n1{5-5};
743  let Inst{25-23} = n1{4-2};
744  let Inst{13-13} = n1{1-1};
745  let Inst{8-8} = n1{0-0};
746}
747class Enc_78cbf0 : OpcodeHexagon {
748  bits <18> Ii;
749  let Inst{26-25} = Ii{17-16};
750  let Inst{20-16} = Ii{15-11};
751  let Inst{13-13} = Ii{10-10};
752  let Inst{7-0} = Ii{9-2};
753  bits <3> Nt8;
754  let Inst{10-8} = Nt8{2-0};
755}
756class Enc_052c7d : OpcodeHexagon {
757  bits <5> Ii;
758  let Inst{6-3} = Ii{4-1};
759  bits <5> Rt32;
760  let Inst{12-8} = Rt32{4-0};
761  bits <5> Rx32;
762  let Inst{20-16} = Rx32{4-0};
763}
764class Enc_fcf7a7 : OpcodeHexagon {
765  bits <5> Rss32;
766  let Inst{20-16} = Rss32{4-0};
767  bits <5> Rtt32;
768  let Inst{12-8} = Rtt32{4-0};
769  bits <2> Pd4;
770  let Inst{1-0} = Pd4{1-0};
771}
772class Enc_55355c : OpcodeHexagon {
773  bits <2> Ii;
774  let Inst{13-13} = Ii{1-1};
775  let Inst{7-7} = Ii{0-0};
776  bits <5> Rs32;
777  let Inst{20-16} = Rs32{4-0};
778  bits <5> Ru32;
779  let Inst{12-8} = Ru32{4-0};
780  bits <5> Rtt32;
781  let Inst{4-0} = Rtt32{4-0};
782}
783class Enc_211aaa : OpcodeHexagon {
784  bits <11> Ii;
785  let Inst{26-25} = Ii{10-9};
786  let Inst{13-5} = Ii{8-0};
787  bits <5> Rs32;
788  let Inst{20-16} = Rs32{4-0};
789  bits <5> Rd32;
790  let Inst{4-0} = Rd32{4-0};
791}
792class Enc_6185fe : OpcodeHexagon {
793  bits <2> Ii;
794  let Inst{13-13} = Ii{1-1};
795  let Inst{7-7} = Ii{0-0};
796  bits <6> II;
797  let Inst{11-8} = II{5-2};
798  let Inst{6-5} = II{1-0};
799  bits <5> Rt32;
800  let Inst{20-16} = Rt32{4-0};
801  bits <5> Rdd32;
802  let Inst{4-0} = Rdd32{4-0};
803}
804class Enc_74aef2 : OpcodeHexagon {
805  bits <4> Ii;
806  let Inst{8-5} = Ii{3-0};
807  bits <1> Mu2;
808  let Inst{13-13} = Mu2{0-0};
809  bits <5> Ryy32;
810  let Inst{4-0} = Ryy32{4-0};
811  bits <5> Rx32;
812  let Inst{20-16} = Rx32{4-0};
813}
814class Enc_cd4705 : OpcodeHexagon {
815  bits <3> Ii;
816  let Inst{7-5} = Ii{2-0};
817  bits <5> Vu32;
818  let Inst{12-8} = Vu32{4-0};
819  bits <5> Vv32;
820  let Inst{20-16} = Vv32{4-0};
821  bits <5> Vx32;
822  let Inst{4-0} = Vx32{4-0};
823}
824class Enc_2ebe3b : OpcodeHexagon {
825  bits <1> Mu2;
826  let Inst{13-13} = Mu2{0-0};
827  bits <5> Vd32;
828  let Inst{4-0} = Vd32{4-0};
829  bits <5> Rx32;
830  let Inst{20-16} = Rx32{4-0};
831}
832class Enc_3d5b28 : OpcodeHexagon {
833  bits <5> Rss32;
834  let Inst{20-16} = Rss32{4-0};
835  bits <5> Rt32;
836  let Inst{12-8} = Rt32{4-0};
837  bits <5> Rd32;
838  let Inst{4-0} = Rd32{4-0};
839}
840class Enc_5ab2be : OpcodeHexagon {
841  bits <5> Rs32;
842  let Inst{20-16} = Rs32{4-0};
843  bits <5> Rt32;
844  let Inst{12-8} = Rt32{4-0};
845  bits <5> Rd32;
846  let Inst{4-0} = Rd32{4-0};
847}
848class Enc_fef969 : OpcodeHexagon {
849  bits <6> Ii;
850  let Inst{20-16} = Ii{5-1};
851  let Inst{5-5} = Ii{0-0};
852  bits <5> Rt32;
853  let Inst{12-8} = Rt32{4-0};
854  bits <5> Rd32;
855  let Inst{4-0} = Rd32{4-0};
856}
857class Enc_63eaeb : OpcodeHexagon {
858  bits <2> Ii;
859  let Inst{1-0} = Ii{1-0};
860  bits <4> Rs16;
861  let Inst{7-4} = Rs16{3-0};
862}
863class Enc_95441f : OpcodeHexagon {
864  bits <5> Vu32;
865  let Inst{12-8} = Vu32{4-0};
866  bits <5> Vv32;
867  let Inst{20-16} = Vv32{4-0};
868  bits <2> Qd4;
869  let Inst{1-0} = Qd4{1-0};
870}
871class Enc_372c9d : OpcodeHexagon {
872  bits <2> Pv4;
873  let Inst{12-11} = Pv4{1-0};
874  bits <1> Mu2;
875  let Inst{13-13} = Mu2{0-0};
876  bits <3> Os8;
877  let Inst{2-0} = Os8{2-0};
878  bits <5> Rx32;
879  let Inst{20-16} = Rx32{4-0};
880}
881class Enc_4dff07 : OpcodeHexagon {
882  bits <2> Qv4;
883  let Inst{12-11} = Qv4{1-0};
884  bits <1> Mu2;
885  let Inst{13-13} = Mu2{0-0};
886  bits <5> Vs32;
887  let Inst{4-0} = Vs32{4-0};
888  bits <5> Rx32;
889  let Inst{20-16} = Rx32{4-0};
890}
891class Enc_04c959 : OpcodeHexagon {
892  bits <2> Ii;
893  let Inst{13-13} = Ii{1-1};
894  let Inst{7-7} = Ii{0-0};
895  bits <6> II;
896  let Inst{11-8} = II{5-2};
897  let Inst{6-5} = II{1-0};
898  bits <5> Rt32;
899  let Inst{20-16} = Rt32{4-0};
900  bits <5> Ryy32;
901  let Inst{4-0} = Ryy32{4-0};
902}
903class Enc_b62ef7 : OpcodeHexagon {
904  bits <3> Ii;
905  let Inst{10-8} = Ii{2-0};
906  bits <5> Vs32;
907  let Inst{4-0} = Vs32{4-0};
908  bits <5> Rx32;
909  let Inst{20-16} = Rx32{4-0};
910}
911class Enc_2b518f : OpcodeHexagon {
912  bits <32> Ii;
913  let Inst{27-16} = Ii{31-20};
914  let Inst{13-0} = Ii{19-6};
915}
916class Enc_b388cf : OpcodeHexagon {
917  bits <5> Ii;
918  let Inst{12-8} = Ii{4-0};
919  bits <5> II;
920  let Inst{22-21} = II{4-3};
921  let Inst{7-5} = II{2-0};
922  bits <5> Rs32;
923  let Inst{20-16} = Rs32{4-0};
924  bits <5> Rd32;
925  let Inst{4-0} = Rd32{4-0};
926}
927class Enc_ad1c74 : OpcodeHexagon {
928  bits <11> Ii;
929  let Inst{21-20} = Ii{10-9};
930  let Inst{7-1} = Ii{8-2};
931  bits <4> Rs16;
932  let Inst{19-16} = Rs16{3-0};
933}
934class Enc_74d4e5 : OpcodeHexagon {
935  bits <1> Mu2;
936  let Inst{13-13} = Mu2{0-0};
937  bits <5> Rd32;
938  let Inst{4-0} = Rd32{4-0};
939  bits <5> Rx32;
940  let Inst{20-16} = Rx32{4-0};
941}
942class Enc_c90aca : OpcodeHexagon {
943  bits <8> Ii;
944  let Inst{12-5} = Ii{7-0};
945  bits <5> Rs32;
946  let Inst{20-16} = Rs32{4-0};
947  bits <5> Rx32;
948  let Inst{4-0} = Rx32{4-0};
949}
950class Enc_222336 : OpcodeHexagon {
951  bits <4> Ii;
952  let Inst{8-5} = Ii{3-0};
953  bits <5> Rd32;
954  let Inst{4-0} = Rd32{4-0};
955  bits <5> Rx32;
956  let Inst{20-16} = Rx32{4-0};
957}
958class Enc_5e87ce : OpcodeHexagon {
959  bits <16> Ii;
960  let Inst{23-22} = Ii{15-14};
961  let Inst{20-16} = Ii{13-9};
962  let Inst{13-5} = Ii{8-0};
963  bits <5> Rd32;
964  let Inst{4-0} = Rd32{4-0};
965}
966class Enc_158beb : OpcodeHexagon {
967  bits <2> Qs4;
968  let Inst{6-5} = Qs4{1-0};
969  bits <5> Rt32;
970  let Inst{20-16} = Rt32{4-0};
971  bits <1> Mu2;
972  let Inst{13-13} = Mu2{0-0};
973  bits <5> Vv32;
974  let Inst{4-0} = Vv32{4-0};
975}
976class Enc_f7ea77 : OpcodeHexagon {
977  bits <11> Ii;
978  let Inst{21-20} = Ii{10-9};
979  let Inst{7-1} = Ii{8-2};
980  bits <3> Ns8;
981  let Inst{18-16} = Ns8{2-0};
982  bits <4> n1;
983  let Inst{29-29} = n1{3-3};
984  let Inst{26-25} = n1{2-1};
985  let Inst{13-13} = n1{0-0};
986}
987class Enc_245865 : OpcodeHexagon {
988  bits <5> Vu32;
989  let Inst{12-8} = Vu32{4-0};
990  bits <5> Vv32;
991  let Inst{23-19} = Vv32{4-0};
992  bits <3> Rt8;
993  let Inst{18-16} = Rt8{2-0};
994  bits <5> Vx32;
995  let Inst{4-0} = Vx32{4-0};
996}
997class Enc_88d4d9 : OpcodeHexagon {
998  bits <2> Pu4;
999  let Inst{9-8} = Pu4{1-0};
1000  bits <5> Rs32;
1001  let Inst{20-16} = Rs32{4-0};
1002}
1003class Enc_226535 : OpcodeHexagon {
1004  bits <8> Ii;
1005  let Inst{12-7} = Ii{7-2};
1006  bits <5> Rs32;
1007  let Inst{20-16} = Rs32{4-0};
1008  bits <5> Rt32;
1009  let Inst{4-0} = Rt32{4-0};
1010}
1011class Enc_31aa6a : OpcodeHexagon {
1012  bits <5> Ii;
1013  let Inst{6-3} = Ii{4-1};
1014  bits <2> Pv4;
1015  let Inst{1-0} = Pv4{1-0};
1016  bits <3> Nt8;
1017  let Inst{10-8} = Nt8{2-0};
1018  bits <5> Rx32;
1019  let Inst{20-16} = Rx32{4-0};
1020}
1021class Enc_397f23 : OpcodeHexagon {
1022  bits <8> Ii;
1023  let Inst{13-13} = Ii{7-7};
1024  let Inst{7-3} = Ii{6-2};
1025  bits <2> Pv4;
1026  let Inst{1-0} = Pv4{1-0};
1027  bits <5> Rs32;
1028  let Inst{20-16} = Rs32{4-0};
1029  bits <5> Rt32;
1030  let Inst{12-8} = Rt32{4-0};
1031}
1032class Enc_865390 : OpcodeHexagon {
1033  bits <3> Ii;
1034  let Inst{10-8} = Ii{2-0};
1035  bits <2> Pv4;
1036  let Inst{12-11} = Pv4{1-0};
1037  bits <5> Vs32;
1038  let Inst{4-0} = Vs32{4-0};
1039  bits <5> Rx32;
1040  let Inst{20-16} = Rx32{4-0};
1041}
1042class Enc_98c0b8 : OpcodeHexagon {
1043  bits <2> Ii;
1044  let Inst{13-13} = Ii{1-1};
1045  let Inst{7-7} = Ii{0-0};
1046  bits <2> Pv4;
1047  let Inst{6-5} = Pv4{1-0};
1048  bits <5> Rs32;
1049  let Inst{20-16} = Rs32{4-0};
1050  bits <5> Rt32;
1051  let Inst{12-8} = Rt32{4-0};
1052  bits <5> Rdd32;
1053  let Inst{4-0} = Rdd32{4-0};
1054}
1055class Enc_bfbf03 : OpcodeHexagon {
1056  bits <2> Qs4;
1057  let Inst{9-8} = Qs4{1-0};
1058  bits <2> Qd4;
1059  let Inst{1-0} = Qd4{1-0};
1060}
1061class Enc_ecbcc8 : OpcodeHexagon {
1062  bits <5> Rs32;
1063  let Inst{20-16} = Rs32{4-0};
1064}
1065class Enc_f5e933 : OpcodeHexagon {
1066  bits <2> Ps4;
1067  let Inst{17-16} = Ps4{1-0};
1068  bits <5> Rd32;
1069  let Inst{4-0} = Rd32{4-0};
1070}
1071class Enc_3fc427 : OpcodeHexagon {
1072  bits <5> Vu32;
1073  let Inst{12-8} = Vu32{4-0};
1074  bits <5> Vv32;
1075  let Inst{20-16} = Vv32{4-0};
1076  bits <5> Vxx32;
1077  let Inst{4-0} = Vxx32{4-0};
1078}
1079class Enc_01d3d0 : OpcodeHexagon {
1080  bits <5> Vu32;
1081  let Inst{12-8} = Vu32{4-0};
1082  bits <5> Rt32;
1083  let Inst{20-16} = Rt32{4-0};
1084  bits <5> Vdd32;
1085  let Inst{4-0} = Vdd32{4-0};
1086}
1087class Enc_b0e9d8 : OpcodeHexagon {
1088  bits <10> Ii;
1089  let Inst{21-21} = Ii{9-9};
1090  let Inst{13-5} = Ii{8-0};
1091  bits <5> Rs32;
1092  let Inst{20-16} = Rs32{4-0};
1093  bits <5> Rx32;
1094  let Inst{4-0} = Rx32{4-0};
1095}
1096class Enc_1bd127 : OpcodeHexagon {
1097  bits <5> Vu32;
1098  let Inst{12-8} = Vu32{4-0};
1099  bits <3> Rt8;
1100  let Inst{18-16} = Rt8{2-0};
1101  bits <5> Vdddd32;
1102  let Inst{4-0} = Vdddd32{4-0};
1103}
1104class Enc_3694bd : OpcodeHexagon {
1105  bits <11> Ii;
1106  let Inst{21-20} = Ii{10-9};
1107  let Inst{7-1} = Ii{8-2};
1108  bits <3> Ns8;
1109  let Inst{18-16} = Ns8{2-0};
1110  bits <5> n1;
1111  let Inst{29-29} = n1{4-4};
1112  let Inst{26-25} = n1{3-2};
1113  let Inst{23-22} = n1{1-0};
1114}
1115class Enc_a42857 : OpcodeHexagon {
1116  bits <11> Ii;
1117  let Inst{21-20} = Ii{10-9};
1118  let Inst{7-1} = Ii{8-2};
1119  bits <4> Rs16;
1120  let Inst{19-16} = Rs16{3-0};
1121  bits <5> n1;
1122  let Inst{28-28} = n1{4-4};
1123  let Inst{24-22} = n1{3-1};
1124  let Inst{8-8} = n1{0-0};
1125}
1126class Enc_b7fad3 : OpcodeHexagon {
1127  bits <2> Pv4;
1128  let Inst{9-8} = Pv4{1-0};
1129  bits <5> Rs32;
1130  let Inst{20-16} = Rs32{4-0};
1131  bits <5> Rdd32;
1132  let Inst{4-0} = Rdd32{4-0};
1133}
1134class Enc_223005 : OpcodeHexagon {
1135  bits <6> Ii;
1136  let Inst{6-3} = Ii{5-2};
1137  bits <3> Nt8;
1138  let Inst{10-8} = Nt8{2-0};
1139  bits <5> Rx32;
1140  let Inst{20-16} = Rx32{4-0};
1141}
1142class Enc_9e4c3f : OpcodeHexagon {
1143  bits <6> II;
1144  let Inst{13-8} = II{5-0};
1145  bits <11> Ii;
1146  let Inst{21-20} = Ii{10-9};
1147  let Inst{7-1} = Ii{8-2};
1148  bits <4> Rd16;
1149  let Inst{19-16} = Rd16{3-0};
1150}
1151class Enc_8b8d61 : OpcodeHexagon {
1152  bits <6> Ii;
1153  let Inst{22-21} = Ii{5-4};
1154  let Inst{13-13} = Ii{3-3};
1155  let Inst{7-5} = Ii{2-0};
1156  bits <5> Rs32;
1157  let Inst{20-16} = Rs32{4-0};
1158  bits <5> Ru32;
1159  let Inst{4-0} = Ru32{4-0};
1160  bits <5> Rd32;
1161  let Inst{12-8} = Rd32{4-0};
1162}
1163class Enc_88c16c : OpcodeHexagon {
1164  bits <5> Rss32;
1165  let Inst{20-16} = Rss32{4-0};
1166  bits <5> Rtt32;
1167  let Inst{12-8} = Rtt32{4-0};
1168  bits <5> Rxx32;
1169  let Inst{4-0} = Rxx32{4-0};
1170}
1171class Enc_770858 : OpcodeHexagon {
1172  bits <2> Ps4;
1173  let Inst{6-5} = Ps4{1-0};
1174  bits <5> Vu32;
1175  let Inst{12-8} = Vu32{4-0};
1176  bits <5> Vd32;
1177  let Inst{4-0} = Vd32{4-0};
1178}
1179class Enc_bd811a : OpcodeHexagon {
1180  bits <5> Rs32;
1181  let Inst{20-16} = Rs32{4-0};
1182  bits <5> Cd32;
1183  let Inst{4-0} = Cd32{4-0};
1184}
1185class Enc_b05839 : OpcodeHexagon {
1186  bits <7> Ii;
1187  let Inst{8-5} = Ii{6-3};
1188  bits <1> Mu2;
1189  let Inst{13-13} = Mu2{0-0};
1190  bits <5> Rdd32;
1191  let Inst{4-0} = Rdd32{4-0};
1192  bits <5> Rx32;
1193  let Inst{20-16} = Rx32{4-0};
1194}
1195class Enc_bc03e5 : OpcodeHexagon {
1196  bits <17> Ii;
1197  let Inst{26-25} = Ii{16-15};
1198  let Inst{20-16} = Ii{14-10};
1199  let Inst{13-13} = Ii{9-9};
1200  let Inst{7-0} = Ii{8-1};
1201  bits <3> Nt8;
1202  let Inst{10-8} = Nt8{2-0};
1203}
1204class Enc_412ff0 : OpcodeHexagon {
1205  bits <5> Rss32;
1206  let Inst{20-16} = Rss32{4-0};
1207  bits <5> Ru32;
1208  let Inst{4-0} = Ru32{4-0};
1209  bits <5> Rxx32;
1210  let Inst{12-8} = Rxx32{4-0};
1211}
1212class Enc_ef601b : OpcodeHexagon {
1213  bits <4> Ii;
1214  let Inst{13-13} = Ii{3-3};
1215  let Inst{10-8} = Ii{2-0};
1216  bits <2> Pv4;
1217  let Inst{12-11} = Pv4{1-0};
1218  bits <5> Rt32;
1219  let Inst{20-16} = Rt32{4-0};
1220}
1221class Enc_c9a18e : OpcodeHexagon {
1222  bits <11> Ii;
1223  let Inst{21-20} = Ii{10-9};
1224  let Inst{7-1} = Ii{8-2};
1225  bits <3> Ns8;
1226  let Inst{18-16} = Ns8{2-0};
1227  bits <5> Rt32;
1228  let Inst{12-8} = Rt32{4-0};
1229}
1230class Enc_be32a5 : OpcodeHexagon {
1231  bits <5> Rs32;
1232  let Inst{20-16} = Rs32{4-0};
1233  bits <5> Rt32;
1234  let Inst{12-8} = Rt32{4-0};
1235  bits <5> Rdd32;
1236  let Inst{4-0} = Rdd32{4-0};
1237}
1238class Enc_e6abcf : OpcodeHexagon {
1239  bits <5> Rs32;
1240  let Inst{20-16} = Rs32{4-0};
1241  bits <5> Rtt32;
1242  let Inst{12-8} = Rtt32{4-0};
1243}
1244class Enc_d6990d : OpcodeHexagon {
1245  bits <5> Vuu32;
1246  let Inst{12-8} = Vuu32{4-0};
1247  bits <5> Rt32;
1248  let Inst{20-16} = Rt32{4-0};
1249  bits <5> Vxx32;
1250  let Inst{4-0} = Vxx32{4-0};
1251}
1252class Enc_6c9440 : OpcodeHexagon {
1253  bits <10> Ii;
1254  let Inst{21-21} = Ii{9-9};
1255  let Inst{13-5} = Ii{8-0};
1256  bits <5> Rd32;
1257  let Inst{4-0} = Rd32{4-0};
1258}
1259class Enc_0d8adb : OpcodeHexagon {
1260  bits <8> Ii;
1261  let Inst{12-5} = Ii{7-0};
1262  bits <5> Rss32;
1263  let Inst{20-16} = Rss32{4-0};
1264  bits <2> Pd4;
1265  let Inst{1-0} = Pd4{1-0};
1266}
1267class Enc_50e578 : OpcodeHexagon {
1268  bits <5> Vu32;
1269  let Inst{12-8} = Vu32{4-0};
1270  bits <5> Rs32;
1271  let Inst{20-16} = Rs32{4-0};
1272  bits <5> Rd32;
1273  let Inst{4-0} = Rd32{4-0};
1274}
1275class Enc_1cf4ca : OpcodeHexagon {
1276  bits <6> Ii;
1277  let Inst{17-16} = Ii{5-4};
1278  let Inst{6-3} = Ii{3-0};
1279  bits <2> Pv4;
1280  let Inst{1-0} = Pv4{1-0};
1281  bits <5> Rt32;
1282  let Inst{12-8} = Rt32{4-0};
1283}
1284class Enc_48b75f : OpcodeHexagon {
1285  bits <5> Rs32;
1286  let Inst{20-16} = Rs32{4-0};
1287  bits <2> Pd4;
1288  let Inst{1-0} = Pd4{1-0};
1289}
1290class Enc_b97f71 : OpcodeHexagon {
1291  bits <6> Ii;
1292  let Inst{8-5} = Ii{5-2};
1293  bits <2> Pt4;
1294  let Inst{10-9} = Pt4{1-0};
1295  bits <5> Rd32;
1296  let Inst{4-0} = Rd32{4-0};
1297  bits <5> Rx32;
1298  let Inst{20-16} = Rx32{4-0};
1299}
1300class Enc_9d1247 : OpcodeHexagon {
1301  bits <7> Ii;
1302  let Inst{8-5} = Ii{6-3};
1303  bits <2> Pt4;
1304  let Inst{10-9} = Pt4{1-0};
1305  bits <5> Rdd32;
1306  let Inst{4-0} = Rdd32{4-0};
1307  bits <5> Rx32;
1308  let Inst{20-16} = Rx32{4-0};
1309}
1310class Enc_7b7ba8 : OpcodeHexagon {
1311  bits <2> Qu4;
1312  let Inst{9-8} = Qu4{1-0};
1313  bits <5> Rt32;
1314  let Inst{20-16} = Rt32{4-0};
1315  bits <5> Vd32;
1316  let Inst{4-0} = Vd32{4-0};
1317}
1318class Enc_f7430e : OpcodeHexagon {
1319  bits <4> Ii;
1320  let Inst{13-13} = Ii{3-3};
1321  let Inst{10-8} = Ii{2-0};
1322  bits <2> Pv4;
1323  let Inst{12-11} = Pv4{1-0};
1324  bits <5> Rt32;
1325  let Inst{20-16} = Rt32{4-0};
1326  bits <3> Os8;
1327  let Inst{2-0} = Os8{2-0};
1328}
1329class Enc_e7581c : OpcodeHexagon {
1330  bits <5> Vu32;
1331  let Inst{12-8} = Vu32{4-0};
1332  bits <5> Vd32;
1333  let Inst{4-0} = Vd32{4-0};
1334}
1335class Enc_2301d6 : OpcodeHexagon {
1336  bits <6> Ii;
1337  let Inst{20-16} = Ii{5-1};
1338  let Inst{8-8} = Ii{0-0};
1339  bits <2> Pt4;
1340  let Inst{10-9} = Pt4{1-0};
1341  bits <5> Rd32;
1342  let Inst{4-0} = Rd32{4-0};
1343}
1344class Enc_c31910 : OpcodeHexagon {
1345  bits <8> Ii;
1346  let Inst{23-21} = Ii{7-5};
1347  let Inst{13-13} = Ii{4-4};
1348  let Inst{7-5} = Ii{3-1};
1349  let Inst{3-3} = Ii{0-0};
1350  bits <5> II;
1351  let Inst{12-8} = II{4-0};
1352  bits <5> Rx32;
1353  let Inst{20-16} = Rx32{4-0};
1354}
1355class Enc_2f2f04 : OpcodeHexagon {
1356  bits <1> Ii;
1357  let Inst{5-5} = Ii{0-0};
1358  bits <5> Vuu32;
1359  let Inst{12-8} = Vuu32{4-0};
1360  bits <5> Rt32;
1361  let Inst{20-16} = Rt32{4-0};
1362  bits <5> Vdd32;
1363  let Inst{4-0} = Vdd32{4-0};
1364}
1365class Enc_8d8a30 : OpcodeHexagon {
1366  bits <4> Ii;
1367  let Inst{13-13} = Ii{3-3};
1368  let Inst{10-8} = Ii{2-0};
1369  bits <2> Pv4;
1370  let Inst{12-11} = Pv4{1-0};
1371  bits <5> Rt32;
1372  let Inst{20-16} = Rt32{4-0};
1373  bits <5> Vd32;
1374  let Inst{4-0} = Vd32{4-0};
1375}
1376class Enc_2d7491 : OpcodeHexagon {
1377  bits <13> Ii;
1378  let Inst{26-25} = Ii{12-11};
1379  let Inst{13-5} = Ii{10-2};
1380  bits <5> Rs32;
1381  let Inst{20-16} = Rs32{4-0};
1382  bits <5> Rdd32;
1383  let Inst{4-0} = Rdd32{4-0};
1384}
1385class Enc_a803e0 : OpcodeHexagon {
1386  bits <7> Ii;
1387  let Inst{12-7} = Ii{6-1};
1388  bits <8> II;
1389  let Inst{13-13} = II{7-7};
1390  let Inst{6-0} = II{6-0};
1391  bits <5> Rs32;
1392  let Inst{20-16} = Rs32{4-0};
1393}
1394class Enc_45364e : OpcodeHexagon {
1395  bits <5> Vu32;
1396  let Inst{12-8} = Vu32{4-0};
1397  bits <5> Vv32;
1398  let Inst{20-16} = Vv32{4-0};
1399  bits <5> Vd32;
1400  let Inst{4-0} = Vd32{4-0};
1401}
1402class Enc_b909d2 : OpcodeHexagon {
1403  bits <11> Ii;
1404  let Inst{21-20} = Ii{10-9};
1405  let Inst{7-1} = Ii{8-2};
1406  bits <4> Rs16;
1407  let Inst{19-16} = Rs16{3-0};
1408  bits <7> n1;
1409  let Inst{28-28} = n1{6-6};
1410  let Inst{25-22} = n1{5-2};
1411  let Inst{13-13} = n1{1-1};
1412  let Inst{8-8} = n1{0-0};
1413}
1414class Enc_e6c957 : OpcodeHexagon {
1415  bits <10> Ii;
1416  let Inst{21-21} = Ii{9-9};
1417  let Inst{13-5} = Ii{8-0};
1418  bits <5> Rdd32;
1419  let Inst{4-0} = Rdd32{4-0};
1420}
1421class Enc_0d8870 : OpcodeHexagon {
1422  bits <12> Ii;
1423  let Inst{26-25} = Ii{11-10};
1424  let Inst{13-13} = Ii{9-9};
1425  let Inst{7-0} = Ii{8-1};
1426  bits <5> Rs32;
1427  let Inst{20-16} = Rs32{4-0};
1428  bits <3> Nt8;
1429  let Inst{10-8} = Nt8{2-0};
1430}
1431class Enc_9fae8a : OpcodeHexagon {
1432  bits <6> Ii;
1433  let Inst{13-8} = Ii{5-0};
1434  bits <5> Rs32;
1435  let Inst{20-16} = Rs32{4-0};
1436  bits <5> Rd32;
1437  let Inst{4-0} = Rd32{4-0};
1438}
1439class Enc_18c338 : OpcodeHexagon {
1440  bits <8> Ii;
1441  let Inst{12-5} = Ii{7-0};
1442  bits <8> II;
1443  let Inst{22-16} = II{7-1};
1444  let Inst{13-13} = II{0-0};
1445  bits <5> Rdd32;
1446  let Inst{4-0} = Rdd32{4-0};
1447}
1448class Enc_5ccba9 : OpcodeHexagon {
1449  bits <8> Ii;
1450  let Inst{12-7} = Ii{7-2};
1451  bits <6> II;
1452  let Inst{13-13} = II{5-5};
1453  let Inst{4-0} = II{4-0};
1454  bits <2> Pv4;
1455  let Inst{6-5} = Pv4{1-0};
1456  bits <5> Rs32;
1457  let Inst{20-16} = Rs32{4-0};
1458}
1459class Enc_0ed752 : OpcodeHexagon {
1460  bits <5> Rss32;
1461  let Inst{20-16} = Rss32{4-0};
1462  bits <5> Cdd32;
1463  let Inst{4-0} = Cdd32{4-0};
1464}
1465class Enc_143445 : OpcodeHexagon {
1466  bits <13> Ii;
1467  let Inst{26-25} = Ii{12-11};
1468  let Inst{13-13} = Ii{10-10};
1469  let Inst{7-0} = Ii{9-2};
1470  bits <5> Rs32;
1471  let Inst{20-16} = Rs32{4-0};
1472  bits <5> Rt32;
1473  let Inst{12-8} = Rt32{4-0};
1474}
1475class Enc_3a3d62 : OpcodeHexagon {
1476  bits <5> Rs32;
1477  let Inst{20-16} = Rs32{4-0};
1478  bits <5> Rdd32;
1479  let Inst{4-0} = Rdd32{4-0};
1480}
1481class Enc_3e3989 : OpcodeHexagon {
1482  bits <11> Ii;
1483  let Inst{21-20} = Ii{10-9};
1484  let Inst{7-1} = Ii{8-2};
1485  bits <4> Rs16;
1486  let Inst{19-16} = Rs16{3-0};
1487  bits <6> n1;
1488  let Inst{28-28} = n1{5-5};
1489  let Inst{25-22} = n1{4-1};
1490  let Inst{8-8} = n1{0-0};
1491}
1492class Enc_152467 : OpcodeHexagon {
1493  bits <5> Ii;
1494  let Inst{8-5} = Ii{4-1};
1495  bits <5> Rd32;
1496  let Inst{4-0} = Rd32{4-0};
1497  bits <5> Rx32;
1498  let Inst{20-16} = Rx32{4-0};
1499}
1500class Enc_9ac432 : OpcodeHexagon {
1501  bits <2> Ps4;
1502  let Inst{17-16} = Ps4{1-0};
1503  bits <2> Pt4;
1504  let Inst{9-8} = Pt4{1-0};
1505  bits <2> Pu4;
1506  let Inst{7-6} = Pu4{1-0};
1507  bits <2> Pd4;
1508  let Inst{1-0} = Pd4{1-0};
1509}
1510class Enc_a90628 : OpcodeHexagon {
1511  bits <2> Qv4;
1512  let Inst{23-22} = Qv4{1-0};
1513  bits <5> Vu32;
1514  let Inst{12-8} = Vu32{4-0};
1515  bits <5> Vx32;
1516  let Inst{4-0} = Vx32{4-0};
1517}
1518class Enc_f37377 : OpcodeHexagon {
1519  bits <8> Ii;
1520  let Inst{12-7} = Ii{7-2};
1521  bits <8> II;
1522  let Inst{13-13} = II{7-7};
1523  let Inst{6-0} = II{6-0};
1524  bits <5> Rs32;
1525  let Inst{20-16} = Rs32{4-0};
1526}
1527class Enc_a198f6 : OpcodeHexagon {
1528  bits <7> Ii;
1529  let Inst{10-5} = Ii{6-1};
1530  bits <2> Pt4;
1531  let Inst{12-11} = Pt4{1-0};
1532  bits <5> Rs32;
1533  let Inst{20-16} = Rs32{4-0};
1534  bits <5> Rd32;
1535  let Inst{4-0} = Rd32{4-0};
1536}
1537class Enc_4e4a80 : OpcodeHexagon {
1538  bits <2> Qs4;
1539  let Inst{6-5} = Qs4{1-0};
1540  bits <5> Rt32;
1541  let Inst{20-16} = Rt32{4-0};
1542  bits <1> Mu2;
1543  let Inst{13-13} = Mu2{0-0};
1544  bits <5> Vvv32;
1545  let Inst{4-0} = Vvv32{4-0};
1546}
1547class Enc_3dac0b : OpcodeHexagon {
1548  bits <2> Qt4;
1549  let Inst{6-5} = Qt4{1-0};
1550  bits <5> Vu32;
1551  let Inst{12-8} = Vu32{4-0};
1552  bits <5> Vv32;
1553  let Inst{20-16} = Vv32{4-0};
1554  bits <5> Vdd32;
1555  let Inst{4-0} = Vdd32{4-0};
1556}
1557class Enc_e38e1f : OpcodeHexagon {
1558  bits <8> Ii;
1559  let Inst{12-5} = Ii{7-0};
1560  bits <2> Pu4;
1561  let Inst{22-21} = Pu4{1-0};
1562  bits <5> Rs32;
1563  let Inst{20-16} = Rs32{4-0};
1564  bits <5> Rd32;
1565  let Inst{4-0} = Rd32{4-0};
1566}
1567class Enc_f8ecf9 : OpcodeHexagon {
1568  bits <5> Vuu32;
1569  let Inst{12-8} = Vuu32{4-0};
1570  bits <5> Vvv32;
1571  let Inst{20-16} = Vvv32{4-0};
1572  bits <5> Vdd32;
1573  let Inst{4-0} = Vdd32{4-0};
1574}
1575class Enc_7f1a05 : OpcodeHexagon {
1576  bits <5> Ru32;
1577  let Inst{4-0} = Ru32{4-0};
1578  bits <5> Rs32;
1579  let Inst{20-16} = Rs32{4-0};
1580  bits <5> Ry32;
1581  let Inst{12-8} = Ry32{4-0};
1582}
1583class Enc_2df31d : OpcodeHexagon {
1584  bits <8> Ii;
1585  let Inst{9-4} = Ii{7-2};
1586  bits <4> Rd16;
1587  let Inst{3-0} = Rd16{3-0};
1588}
1589class Enc_25bef0 : OpcodeHexagon {
1590  bits <16> Ii;
1591  let Inst{26-25} = Ii{15-14};
1592  let Inst{20-16} = Ii{13-9};
1593  let Inst{13-5} = Ii{8-0};
1594  bits <5> Rd32;
1595  let Inst{4-0} = Rd32{4-0};
1596}
1597class Enc_f82302 : OpcodeHexagon {
1598  bits <11> Ii;
1599  let Inst{21-20} = Ii{10-9};
1600  let Inst{7-1} = Ii{8-2};
1601  bits <3> Ns8;
1602  let Inst{18-16} = Ns8{2-0};
1603  bits <4> n1;
1604  let Inst{29-29} = n1{3-3};
1605  let Inst{26-25} = n1{2-1};
1606  let Inst{23-23} = n1{0-0};
1607}
1608class Enc_44271f : OpcodeHexagon {
1609  bits <5> Gs32;
1610  let Inst{20-16} = Gs32{4-0};
1611  bits <5> Rd32;
1612  let Inst{4-0} = Rd32{4-0};
1613}
1614class Enc_83ee64 : OpcodeHexagon {
1615  bits <5> Ii;
1616  let Inst{12-8} = Ii{4-0};
1617  bits <5> Rs32;
1618  let Inst{20-16} = Rs32{4-0};
1619  bits <2> Pd4;
1620  let Inst{1-0} = Pd4{1-0};
1621}
1622class Enc_adf111 : OpcodeHexagon {
1623  bits <5> Vu32;
1624  let Inst{12-8} = Vu32{4-0};
1625  bits <5> Rt32;
1626  let Inst{20-16} = Rt32{4-0};
1627  bits <2> Qx4;
1628  let Inst{1-0} = Qx4{1-0};
1629}
1630class Enc_46c951 : OpcodeHexagon {
1631  bits <6> Ii;
1632  let Inst{12-7} = Ii{5-0};
1633  bits <5> II;
1634  let Inst{4-0} = II{4-0};
1635  bits <5> Rs32;
1636  let Inst{20-16} = Rs32{4-0};
1637}
1638class Enc_5d6c34 : OpcodeHexagon {
1639  bits <6> Ii;
1640  let Inst{13-8} = Ii{5-0};
1641  bits <5> Rs32;
1642  let Inst{20-16} = Rs32{4-0};
1643  bits <2> Pd4;
1644  let Inst{1-0} = Pd4{1-0};
1645}
1646class Enc_4df4e9 : OpcodeHexagon {
1647  bits <11> Ii;
1648  let Inst{26-25} = Ii{10-9};
1649  let Inst{13-13} = Ii{8-8};
1650  let Inst{7-0} = Ii{7-0};
1651  bits <5> Rs32;
1652  let Inst{20-16} = Rs32{4-0};
1653  bits <3> Nt8;
1654  let Inst{10-8} = Nt8{2-0};
1655}
1656class Enc_263841 : OpcodeHexagon {
1657  bits <5> Vu32;
1658  let Inst{12-8} = Vu32{4-0};
1659  bits <5> Rtt32;
1660  let Inst{20-16} = Rtt32{4-0};
1661  bits <5> Vd32;
1662  let Inst{4-0} = Vd32{4-0};
1663}
1664class Enc_91b9fe : OpcodeHexagon {
1665  bits <5> Ii;
1666  let Inst{6-3} = Ii{4-1};
1667  bits <1> Mu2;
1668  let Inst{13-13} = Mu2{0-0};
1669  bits <3> Nt8;
1670  let Inst{10-8} = Nt8{2-0};
1671  bits <5> Rx32;
1672  let Inst{20-16} = Rx32{4-0};
1673}
1674class Enc_a7b8e8 : OpcodeHexagon {
1675  bits <6> Ii;
1676  let Inst{22-21} = Ii{5-4};
1677  let Inst{13-13} = Ii{3-3};
1678  let Inst{7-5} = Ii{2-0};
1679  bits <5> Rs32;
1680  let Inst{20-16} = Rs32{4-0};
1681  bits <5> Rt32;
1682  let Inst{12-8} = Rt32{4-0};
1683  bits <5> Rd32;
1684  let Inst{4-0} = Rd32{4-0};
1685}
1686class Enc_2b3f60 : OpcodeHexagon {
1687  bits <5> Rss32;
1688  let Inst{20-16} = Rss32{4-0};
1689  bits <5> Rtt32;
1690  let Inst{12-8} = Rtt32{4-0};
1691  bits <5> Rdd32;
1692  let Inst{4-0} = Rdd32{4-0};
1693  bits <2> Px4;
1694  let Inst{6-5} = Px4{1-0};
1695}
1696class Enc_bd1cbc : OpcodeHexagon {
1697  bits <5> Ii;
1698  let Inst{8-5} = Ii{4-1};
1699  bits <5> Ryy32;
1700  let Inst{4-0} = Ryy32{4-0};
1701  bits <5> Rx32;
1702  let Inst{20-16} = Rx32{4-0};
1703}
1704class Enc_c85e2a : OpcodeHexagon {
1705  bits <5> Ii;
1706  let Inst{12-8} = Ii{4-0};
1707  bits <5> II;
1708  let Inst{22-21} = II{4-3};
1709  let Inst{7-5} = II{2-0};
1710  bits <5> Rd32;
1711  let Inst{4-0} = Rd32{4-0};
1712}
1713class Enc_a30110 : OpcodeHexagon {
1714  bits <5> Vu32;
1715  let Inst{12-8} = Vu32{4-0};
1716  bits <5> Vv32;
1717  let Inst{23-19} = Vv32{4-0};
1718  bits <3> Rt8;
1719  let Inst{18-16} = Rt8{2-0};
1720  bits <5> Vd32;
1721  let Inst{4-0} = Vd32{4-0};
1722}
1723class Enc_33f8ba : OpcodeHexagon {
1724  bits <8> Ii;
1725  let Inst{12-8} = Ii{7-3};
1726  let Inst{4-2} = Ii{2-0};
1727  bits <5> Rx32;
1728  let Inst{20-16} = Rx32{4-0};
1729}
1730class Enc_690862 : OpcodeHexagon {
1731  bits <13> Ii;
1732  let Inst{26-25} = Ii{12-11};
1733  let Inst{13-13} = Ii{10-10};
1734  let Inst{7-0} = Ii{9-2};
1735  bits <5> Rs32;
1736  let Inst{20-16} = Rs32{4-0};
1737  bits <3> Nt8;
1738  let Inst{10-8} = Nt8{2-0};
1739}
1740class Enc_2a3787 : OpcodeHexagon {
1741  bits <13> Ii;
1742  let Inst{26-25} = Ii{12-11};
1743  let Inst{13-5} = Ii{10-2};
1744  bits <5> Rs32;
1745  let Inst{20-16} = Rs32{4-0};
1746  bits <5> Rd32;
1747  let Inst{4-0} = Rd32{4-0};
1748}
1749class Enc_d5c73f : OpcodeHexagon {
1750  bits <1> Mu2;
1751  let Inst{13-13} = Mu2{0-0};
1752  bits <5> Rt32;
1753  let Inst{12-8} = Rt32{4-0};
1754  bits <5> Rx32;
1755  let Inst{20-16} = Rx32{4-0};
1756}
1757class Enc_3f97c8 : OpcodeHexagon {
1758  bits <6> Ii;
1759  let Inst{6-3} = Ii{5-2};
1760  bits <1> Mu2;
1761  let Inst{13-13} = Mu2{0-0};
1762  bits <3> Nt8;
1763  let Inst{10-8} = Nt8{2-0};
1764  bits <5> Rx32;
1765  let Inst{20-16} = Rx32{4-0};
1766}
1767class Enc_d50cd3 : OpcodeHexagon {
1768  bits <3> Ii;
1769  let Inst{7-5} = Ii{2-0};
1770  bits <5> Rss32;
1771  let Inst{20-16} = Rss32{4-0};
1772  bits <5> Rtt32;
1773  let Inst{12-8} = Rtt32{4-0};
1774  bits <5> Rdd32;
1775  let Inst{4-0} = Rdd32{4-0};
1776}
1777class Enc_729ff7 : OpcodeHexagon {
1778  bits <3> Ii;
1779  let Inst{7-5} = Ii{2-0};
1780  bits <5> Rtt32;
1781  let Inst{12-8} = Rtt32{4-0};
1782  bits <5> Rss32;
1783  let Inst{20-16} = Rss32{4-0};
1784  bits <5> Rdd32;
1785  let Inst{4-0} = Rdd32{4-0};
1786}
1787class Enc_217147 : OpcodeHexagon {
1788  bits <2> Qv4;
1789  let Inst{23-22} = Qv4{1-0};
1790}
1791class Enc_b9c5fb : OpcodeHexagon {
1792  bits <5> Rss32;
1793  let Inst{20-16} = Rss32{4-0};
1794  bits <5> Rdd32;
1795  let Inst{4-0} = Rdd32{4-0};
1796}
1797class Enc_f394d3 : OpcodeHexagon {
1798  bits <6> II;
1799  let Inst{11-8} = II{5-2};
1800  let Inst{6-5} = II{1-0};
1801  bits <5> Ryy32;
1802  let Inst{4-0} = Ryy32{4-0};
1803  bits <5> Re32;
1804  let Inst{20-16} = Re32{4-0};
1805}
1806class Enc_0cb018 : OpcodeHexagon {
1807  bits <5> Cs32;
1808  let Inst{20-16} = Cs32{4-0};
1809  bits <5> Rd32;
1810  let Inst{4-0} = Rd32{4-0};
1811}
1812class Enc_541f26 : OpcodeHexagon {
1813  bits <18> Ii;
1814  let Inst{26-25} = Ii{17-16};
1815  let Inst{20-16} = Ii{15-11};
1816  let Inst{13-13} = Ii{10-10};
1817  let Inst{7-0} = Ii{9-2};
1818  bits <5> Rt32;
1819  let Inst{12-8} = Rt32{4-0};
1820}
1821class Enc_724154 : OpcodeHexagon {
1822  bits <6> II;
1823  let Inst{5-0} = II{5-0};
1824  bits <3> Nt8;
1825  let Inst{10-8} = Nt8{2-0};
1826  bits <5> Re32;
1827  let Inst{20-16} = Re32{4-0};
1828}
1829class Enc_179b35 : OpcodeHexagon {
1830  bits <5> Rs32;
1831  let Inst{20-16} = Rs32{4-0};
1832  bits <5> Rtt32;
1833  let Inst{12-8} = Rtt32{4-0};
1834  bits <5> Rx32;
1835  let Inst{4-0} = Rx32{4-0};
1836}
1837class Enc_585242 : OpcodeHexagon {
1838  bits <6> Ii;
1839  let Inst{13-13} = Ii{5-5};
1840  let Inst{7-3} = Ii{4-0};
1841  bits <2> Pv4;
1842  let Inst{1-0} = Pv4{1-0};
1843  bits <5> Rs32;
1844  let Inst{20-16} = Rs32{4-0};
1845  bits <3> Nt8;
1846  let Inst{10-8} = Nt8{2-0};
1847}
1848class Enc_cf1927 : OpcodeHexagon {
1849  bits <1> Mu2;
1850  let Inst{13-13} = Mu2{0-0};
1851  bits <3> Os8;
1852  let Inst{2-0} = Os8{2-0};
1853  bits <5> Rx32;
1854  let Inst{20-16} = Rx32{4-0};
1855}
1856class Enc_b84c4c : OpcodeHexagon {
1857  bits <6> Ii;
1858  let Inst{13-8} = Ii{5-0};
1859  bits <6> II;
1860  let Inst{23-21} = II{5-3};
1861  let Inst{7-5} = II{2-0};
1862  bits <5> Rss32;
1863  let Inst{20-16} = Rss32{4-0};
1864  bits <5> Rdd32;
1865  let Inst{4-0} = Rdd32{4-0};
1866}
1867class Enc_8203bb : OpcodeHexagon {
1868  bits <6> Ii;
1869  let Inst{12-7} = Ii{5-0};
1870  bits <8> II;
1871  let Inst{13-13} = II{7-7};
1872  let Inst{6-0} = II{6-0};
1873  bits <5> Rs32;
1874  let Inst{20-16} = Rs32{4-0};
1875}
1876class Enc_e66a97 : OpcodeHexagon {
1877  bits <7> Ii;
1878  let Inst{12-7} = Ii{6-1};
1879  bits <5> II;
1880  let Inst{4-0} = II{4-0};
1881  bits <5> Rs32;
1882  let Inst{20-16} = Rs32{4-0};
1883}
1884class Enc_8c2412 : OpcodeHexagon {
1885  bits <2> Ps4;
1886  let Inst{6-5} = Ps4{1-0};
1887  bits <5> Vu32;
1888  let Inst{12-8} = Vu32{4-0};
1889  bits <5> Vv32;
1890  let Inst{20-16} = Vv32{4-0};
1891  bits <5> Vdd32;
1892  let Inst{4-0} = Vdd32{4-0};
1893}
1894class Enc_284ebb : OpcodeHexagon {
1895  bits <2> Ps4;
1896  let Inst{17-16} = Ps4{1-0};
1897  bits <2> Pt4;
1898  let Inst{9-8} = Pt4{1-0};
1899  bits <2> Pd4;
1900  let Inst{1-0} = Pd4{1-0};
1901}
1902class Enc_733b27 : OpcodeHexagon {
1903  bits <5> Ii;
1904  let Inst{8-5} = Ii{4-1};
1905  bits <2> Pt4;
1906  let Inst{10-9} = Pt4{1-0};
1907  bits <5> Rd32;
1908  let Inst{4-0} = Rd32{4-0};
1909  bits <5> Rx32;
1910  let Inst{20-16} = Rx32{4-0};
1911}
1912class Enc_22c845 : OpcodeHexagon {
1913  bits <14> Ii;
1914  let Inst{10-0} = Ii{13-3};
1915  bits <5> Rx32;
1916  let Inst{20-16} = Rx32{4-0};
1917}
1918class Enc_ed5027 : OpcodeHexagon {
1919  bits <5> Rss32;
1920  let Inst{20-16} = Rss32{4-0};
1921  bits <5> Gdd32;
1922  let Inst{4-0} = Gdd32{4-0};
1923}
1924class Enc_9b0bc1 : OpcodeHexagon {
1925  bits <2> Pu4;
1926  let Inst{6-5} = Pu4{1-0};
1927  bits <5> Rt32;
1928  let Inst{12-8} = Rt32{4-0};
1929  bits <5> Rs32;
1930  let Inst{20-16} = Rs32{4-0};
1931  bits <5> Rd32;
1932  let Inst{4-0} = Rd32{4-0};
1933}
1934class Enc_ea4c54 : OpcodeHexagon {
1935  bits <2> Pu4;
1936  let Inst{6-5} = Pu4{1-0};
1937  bits <5> Rs32;
1938  let Inst{20-16} = Rs32{4-0};
1939  bits <5> Rt32;
1940  let Inst{12-8} = Rt32{4-0};
1941  bits <5> Rd32;
1942  let Inst{4-0} = Rd32{4-0};
1943}
1944class Enc_b72622 : OpcodeHexagon {
1945  bits <2> Ii;
1946  let Inst{13-13} = Ii{1-1};
1947  let Inst{5-5} = Ii{0-0};
1948  bits <5> Rss32;
1949  let Inst{20-16} = Rss32{4-0};
1950  bits <5> Rt32;
1951  let Inst{12-8} = Rt32{4-0};
1952  bits <5> Rxx32;
1953  let Inst{4-0} = Rxx32{4-0};
1954}
1955class Enc_569cfe : OpcodeHexagon {
1956  bits <5> Rt32;
1957  let Inst{20-16} = Rt32{4-0};
1958  bits <5> Vx32;
1959  let Inst{4-0} = Vx32{4-0};
1960}
1961class Enc_96ce4f : OpcodeHexagon {
1962  bits <4> Ii;
1963  let Inst{6-3} = Ii{3-0};
1964  bits <1> Mu2;
1965  let Inst{13-13} = Mu2{0-0};
1966  bits <3> Nt8;
1967  let Inst{10-8} = Nt8{2-0};
1968  bits <5> Rx32;
1969  let Inst{20-16} = Rx32{4-0};
1970}
1971class Enc_143a3c : OpcodeHexagon {
1972  bits <6> Ii;
1973  let Inst{13-8} = Ii{5-0};
1974  bits <6> II;
1975  let Inst{23-21} = II{5-3};
1976  let Inst{7-5} = II{2-0};
1977  bits <5> Rss32;
1978  let Inst{20-16} = Rss32{4-0};
1979  bits <5> Rxx32;
1980  let Inst{4-0} = Rxx32{4-0};
1981}
1982class Enc_57a33e : OpcodeHexagon {
1983  bits <9> Ii;
1984  let Inst{13-13} = Ii{8-8};
1985  let Inst{7-3} = Ii{7-3};
1986  bits <2> Pv4;
1987  let Inst{1-0} = Pv4{1-0};
1988  bits <5> Rs32;
1989  let Inst{20-16} = Rs32{4-0};
1990  bits <5> Rtt32;
1991  let Inst{12-8} = Rtt32{4-0};
1992}
1993class Enc_311abd : OpcodeHexagon {
1994  bits <5> Ii;
1995  let Inst{12-8} = Ii{4-0};
1996  bits <5> Rs32;
1997  let Inst{20-16} = Rs32{4-0};
1998  bits <5> Rdd32;
1999  let Inst{4-0} = Rdd32{4-0};
2000}
2001class Enc_a1640c : OpcodeHexagon {
2002  bits <6> Ii;
2003  let Inst{13-8} = Ii{5-0};
2004  bits <5> Rss32;
2005  let Inst{20-16} = Rss32{4-0};
2006  bits <5> Rd32;
2007  let Inst{4-0} = Rd32{4-0};
2008}
2009class Enc_de0214 : OpcodeHexagon {
2010  bits <12> Ii;
2011  let Inst{26-25} = Ii{11-10};
2012  let Inst{13-5} = Ii{9-1};
2013  bits <5> Rs32;
2014  let Inst{20-16} = Rs32{4-0};
2015  bits <5> Rd32;
2016  let Inst{4-0} = Rd32{4-0};
2017}
2018class Enc_daea09 : OpcodeHexagon {
2019  bits <17> Ii;
2020  let Inst{23-22} = Ii{16-15};
2021  let Inst{20-16} = Ii{14-10};
2022  let Inst{13-13} = Ii{9-9};
2023  let Inst{7-1} = Ii{8-2};
2024  bits <2> Pu4;
2025  let Inst{9-8} = Pu4{1-0};
2026}
2027class Enc_fda92c : OpcodeHexagon {
2028  bits <17> Ii;
2029  let Inst{26-25} = Ii{16-15};
2030  let Inst{20-16} = Ii{14-10};
2031  let Inst{13-13} = Ii{9-9};
2032  let Inst{7-0} = Ii{8-1};
2033  bits <5> Rt32;
2034  let Inst{12-8} = Rt32{4-0};
2035}
2036class Enc_831a7d : OpcodeHexagon {
2037  bits <5> Rss32;
2038  let Inst{20-16} = Rss32{4-0};
2039  bits <5> Rtt32;
2040  let Inst{12-8} = Rtt32{4-0};
2041  bits <5> Rxx32;
2042  let Inst{4-0} = Rxx32{4-0};
2043  bits <2> Pe4;
2044  let Inst{6-5} = Pe4{1-0};
2045}
2046class Enc_11a146 : OpcodeHexagon {
2047  bits <4> Ii;
2048  let Inst{11-8} = Ii{3-0};
2049  bits <5> Rss32;
2050  let Inst{20-16} = Rss32{4-0};
2051  bits <5> Rd32;
2052  let Inst{4-0} = Rd32{4-0};
2053}
2054class Enc_b15941 : OpcodeHexagon {
2055  bits <4> Ii;
2056  let Inst{6-3} = Ii{3-0};
2057  bits <1> Mu2;
2058  let Inst{13-13} = Mu2{0-0};
2059  bits <5> Rt32;
2060  let Inst{12-8} = Rt32{4-0};
2061  bits <5> Rx32;
2062  let Inst{20-16} = Rx32{4-0};
2063}
2064class Enc_b78edd : OpcodeHexagon {
2065  bits <11> Ii;
2066  let Inst{21-20} = Ii{10-9};
2067  let Inst{7-1} = Ii{8-2};
2068  bits <4> Rs16;
2069  let Inst{19-16} = Rs16{3-0};
2070  bits <4> n1;
2071  let Inst{28-28} = n1{3-3};
2072  let Inst{24-23} = n1{2-1};
2073  let Inst{8-8} = n1{0-0};
2074}
2075class Enc_a27588 : OpcodeHexagon {
2076  bits <11> Ii;
2077  let Inst{26-25} = Ii{10-9};
2078  let Inst{13-5} = Ii{8-0};
2079  bits <5> Rs32;
2080  let Inst{20-16} = Rs32{4-0};
2081  bits <5> Ryy32;
2082  let Inst{4-0} = Ryy32{4-0};
2083}
2084class Enc_2a7b91 : OpcodeHexagon {
2085  bits <6> Ii;
2086  let Inst{20-16} = Ii{5-1};
2087  let Inst{8-8} = Ii{0-0};
2088  bits <2> Pt4;
2089  let Inst{10-9} = Pt4{1-0};
2090  bits <5> Rdd32;
2091  let Inst{4-0} = Rdd32{4-0};
2092}
2093class Enc_b43b67 : OpcodeHexagon {
2094  bits <5> Vu32;
2095  let Inst{12-8} = Vu32{4-0};
2096  bits <5> Vv32;
2097  let Inst{20-16} = Vv32{4-0};
2098  bits <5> Vd32;
2099  let Inst{4-0} = Vd32{4-0};
2100  bits <2> Qx4;
2101  let Inst{6-5} = Qx4{1-0};
2102}
2103class Enc_4aca3a : OpcodeHexagon {
2104  bits <11> Ii;
2105  let Inst{21-20} = Ii{10-9};
2106  let Inst{7-1} = Ii{8-2};
2107  bits <3> Ns8;
2108  let Inst{18-16} = Ns8{2-0};
2109  bits <3> n1;
2110  let Inst{29-29} = n1{2-2};
2111  let Inst{26-25} = n1{1-0};
2112}
2113class Enc_b38ffc : OpcodeHexagon {
2114  bits <4> Ii;
2115  let Inst{11-8} = Ii{3-0};
2116  bits <4> Rs16;
2117  let Inst{7-4} = Rs16{3-0};
2118  bits <4> Rt16;
2119  let Inst{3-0} = Rt16{3-0};
2120}
2121class Enc_cda00a : OpcodeHexagon {
2122  bits <12> Ii;
2123  let Inst{19-16} = Ii{11-8};
2124  let Inst{12-5} = Ii{7-0};
2125  bits <2> Pu4;
2126  let Inst{22-21} = Pu4{1-0};
2127  bits <5> Rd32;
2128  let Inst{4-0} = Rd32{4-0};
2129}
2130class Enc_2fbf3c : OpcodeHexagon {
2131  bits <3> Ii;
2132  let Inst{10-8} = Ii{2-0};
2133  bits <4> Rs16;
2134  let Inst{7-4} = Rs16{3-0};
2135  bits <4> Rd16;
2136  let Inst{3-0} = Rd16{3-0};
2137}
2138class Enc_70b24b : OpcodeHexagon {
2139  bits <6> Ii;
2140  let Inst{8-5} = Ii{5-2};
2141  bits <1> Mu2;
2142  let Inst{13-13} = Mu2{0-0};
2143  bits <5> Rdd32;
2144  let Inst{4-0} = Rdd32{4-0};
2145  bits <5> Rx32;
2146  let Inst{20-16} = Rx32{4-0};
2147}
2148class Enc_2ae154 : OpcodeHexagon {
2149  bits <5> Rs32;
2150  let Inst{20-16} = Rs32{4-0};
2151  bits <5> Rt32;
2152  let Inst{12-8} = Rt32{4-0};
2153  bits <5> Rx32;
2154  let Inst{4-0} = Rx32{4-0};
2155}
2156class Enc_50b5ac : OpcodeHexagon {
2157  bits <6> Ii;
2158  let Inst{17-16} = Ii{5-4};
2159  let Inst{6-3} = Ii{3-0};
2160  bits <2> Pv4;
2161  let Inst{1-0} = Pv4{1-0};
2162  bits <5> Rtt32;
2163  let Inst{12-8} = Rtt32{4-0};
2164}
2165class Enc_2ea740 : OpcodeHexagon {
2166  bits <4> Ii;
2167  let Inst{13-13} = Ii{3-3};
2168  let Inst{10-8} = Ii{2-0};
2169  bits <2> Qv4;
2170  let Inst{12-11} = Qv4{1-0};
2171  bits <5> Rt32;
2172  let Inst{20-16} = Rt32{4-0};
2173  bits <5> Vs32;
2174  let Inst{4-0} = Vs32{4-0};
2175}
2176class Enc_08d755 : OpcodeHexagon {
2177  bits <8> Ii;
2178  let Inst{12-5} = Ii{7-0};
2179  bits <5> Rs32;
2180  let Inst{20-16} = Rs32{4-0};
2181  bits <2> Pd4;
2182  let Inst{1-0} = Pd4{1-0};
2183}
2184class Enc_1178da : OpcodeHexagon {
2185  bits <3> Ii;
2186  let Inst{7-5} = Ii{2-0};
2187  bits <5> Vu32;
2188  let Inst{12-8} = Vu32{4-0};
2189  bits <5> Vv32;
2190  let Inst{20-16} = Vv32{4-0};
2191  bits <5> Vxx32;
2192  let Inst{4-0} = Vxx32{4-0};
2193}
2194class Enc_8dbe85 : OpcodeHexagon {
2195  bits <1> Mu2;
2196  let Inst{13-13} = Mu2{0-0};
2197  bits <3> Nt8;
2198  let Inst{10-8} = Nt8{2-0};
2199  bits <5> Rx32;
2200  let Inst{20-16} = Rx32{4-0};
2201}
2202class Enc_5a18b3 : OpcodeHexagon {
2203  bits <11> Ii;
2204  let Inst{21-20} = Ii{10-9};
2205  let Inst{7-1} = Ii{8-2};
2206  bits <3> Ns8;
2207  let Inst{18-16} = Ns8{2-0};
2208  bits <5> n1;
2209  let Inst{29-29} = n1{4-4};
2210  let Inst{26-25} = n1{3-2};
2211  let Inst{22-22} = n1{1-1};
2212  let Inst{13-13} = n1{0-0};
2213}
2214class Enc_14d27a : OpcodeHexagon {
2215  bits <5> II;
2216  let Inst{12-8} = II{4-0};
2217  bits <11> Ii;
2218  let Inst{21-20} = Ii{10-9};
2219  let Inst{7-1} = Ii{8-2};
2220  bits <4> Rs16;
2221  let Inst{19-16} = Rs16{3-0};
2222}
2223class Enc_a05677 : OpcodeHexagon {
2224  bits <5> Ii;
2225  let Inst{12-8} = Ii{4-0};
2226  bits <5> Rs32;
2227  let Inst{20-16} = Rs32{4-0};
2228  bits <5> Rd32;
2229  let Inst{4-0} = Rd32{4-0};
2230}
2231class Enc_f0cca7 : OpcodeHexagon {
2232  bits <8> Ii;
2233  let Inst{12-5} = Ii{7-0};
2234  bits <6> II;
2235  let Inst{20-16} = II{5-1};
2236  let Inst{13-13} = II{0-0};
2237  bits <5> Rdd32;
2238  let Inst{4-0} = Rdd32{4-0};
2239}
2240class Enc_500cb0 : OpcodeHexagon {
2241  bits <5> Vu32;
2242  let Inst{12-8} = Vu32{4-0};
2243  bits <5> Vxx32;
2244  let Inst{4-0} = Vxx32{4-0};
2245}
2246class Enc_7e5a82 : OpcodeHexagon {
2247  bits <5> Ii;
2248  let Inst{12-8} = Ii{4-0};
2249  bits <5> Rss32;
2250  let Inst{20-16} = Rss32{4-0};
2251  bits <5> Rdd32;
2252  let Inst{4-0} = Rdd32{4-0};
2253}
2254class Enc_12b6e9 : OpcodeHexagon {
2255  bits <4> Ii;
2256  let Inst{11-8} = Ii{3-0};
2257  bits <5> Rss32;
2258  let Inst{20-16} = Rss32{4-0};
2259  bits <5> Rdd32;
2260  let Inst{4-0} = Rdd32{4-0};
2261}
2262class Enc_6f70ca : OpcodeHexagon {
2263  bits <8> Ii;
2264  let Inst{8-4} = Ii{7-3};
2265}
2266class Enc_7222b7 : OpcodeHexagon {
2267  bits <5> Rt32;
2268  let Inst{20-16} = Rt32{4-0};
2269  bits <2> Qd4;
2270  let Inst{1-0} = Qd4{1-0};
2271}
2272class Enc_e3b0c4 : OpcodeHexagon {
2273
2274}
2275class Enc_a255dc : OpcodeHexagon {
2276  bits <3> Ii;
2277  let Inst{10-8} = Ii{2-0};
2278  bits <5> Vd32;
2279  let Inst{4-0} = Vd32{4-0};
2280  bits <5> Rx32;
2281  let Inst{20-16} = Rx32{4-0};
2282}
2283class Enc_cb785b : OpcodeHexagon {
2284  bits <5> Vu32;
2285  let Inst{12-8} = Vu32{4-0};
2286  bits <5> Rtt32;
2287  let Inst{20-16} = Rtt32{4-0};
2288  bits <5> Vdd32;
2289  let Inst{4-0} = Vdd32{4-0};
2290}
2291class Enc_cb4b4e : OpcodeHexagon {
2292  bits <2> Pu4;
2293  let Inst{6-5} = Pu4{1-0};
2294  bits <5> Rs32;
2295  let Inst{20-16} = Rs32{4-0};
2296  bits <5> Rt32;
2297  let Inst{12-8} = Rt32{4-0};
2298  bits <5> Rdd32;
2299  let Inst{4-0} = Rdd32{4-0};
2300}
2301class Enc_1f5d8f : OpcodeHexagon {
2302  bits <1> Mu2;
2303  let Inst{13-13} = Mu2{0-0};
2304  bits <5> Ryy32;
2305  let Inst{4-0} = Ryy32{4-0};
2306  bits <5> Rx32;
2307  let Inst{20-16} = Rx32{4-0};
2308}
2309class Enc_9cdba7 : OpcodeHexagon {
2310  bits <8> Ii;
2311  let Inst{12-5} = Ii{7-0};
2312  bits <5> Rs32;
2313  let Inst{20-16} = Rs32{4-0};
2314  bits <5> Rdd32;
2315  let Inst{4-0} = Rdd32{4-0};
2316}
2317class Enc_5cd7e9 : OpcodeHexagon {
2318  bits <12> Ii;
2319  let Inst{26-25} = Ii{11-10};
2320  let Inst{13-5} = Ii{9-1};
2321  bits <5> Rs32;
2322  let Inst{20-16} = Rs32{4-0};
2323  bits <5> Ryy32;
2324  let Inst{4-0} = Ryy32{4-0};
2325}
2326class Enc_454a26 : OpcodeHexagon {
2327  bits <2> Pt4;
2328  let Inst{9-8} = Pt4{1-0};
2329  bits <2> Ps4;
2330  let Inst{17-16} = Ps4{1-0};
2331  bits <2> Pd4;
2332  let Inst{1-0} = Pd4{1-0};
2333}
2334class Enc_a6853f : OpcodeHexagon {
2335  bits <11> Ii;
2336  let Inst{21-20} = Ii{10-9};
2337  let Inst{7-1} = Ii{8-2};
2338  bits <3> Ns8;
2339  let Inst{18-16} = Ns8{2-0};
2340  bits <6> n1;
2341  let Inst{29-29} = n1{5-5};
2342  let Inst{26-25} = n1{4-3};
2343  let Inst{23-22} = n1{2-1};
2344  let Inst{13-13} = n1{0-0};
2345}
2346class Enc_c175d0 : OpcodeHexagon {
2347  bits <4> Ii;
2348  let Inst{11-8} = Ii{3-0};
2349  bits <4> Rs16;
2350  let Inst{7-4} = Rs16{3-0};
2351  bits <4> Rd16;
2352  let Inst{3-0} = Rd16{3-0};
2353}
2354class Enc_16c48b : OpcodeHexagon {
2355  bits <5> Rt32;
2356  let Inst{20-16} = Rt32{4-0};
2357  bits <1> Mu2;
2358  let Inst{13-13} = Mu2{0-0};
2359  bits <5> Vv32;
2360  let Inst{12-8} = Vv32{4-0};
2361  bits <5> Vw32;
2362  let Inst{4-0} = Vw32{4-0};
2363}
2364class Enc_895bd9 : OpcodeHexagon {
2365  bits <2> Qu4;
2366  let Inst{9-8} = Qu4{1-0};
2367  bits <5> Rt32;
2368  let Inst{20-16} = Rt32{4-0};
2369  bits <5> Vx32;
2370  let Inst{4-0} = Vx32{4-0};
2371}
2372class Enc_ea23e4 : OpcodeHexagon {
2373  bits <5> Rtt32;
2374  let Inst{12-8} = Rtt32{4-0};
2375  bits <5> Rss32;
2376  let Inst{20-16} = Rss32{4-0};
2377  bits <5> Rdd32;
2378  let Inst{4-0} = Rdd32{4-0};
2379}
2380class Enc_4dc228 : OpcodeHexagon {
2381  bits <9> Ii;
2382  let Inst{12-8} = Ii{8-4};
2383  let Inst{4-3} = Ii{3-2};
2384  bits <10> II;
2385  let Inst{20-16} = II{9-5};
2386  let Inst{7-5} = II{4-2};
2387  let Inst{1-0} = II{1-0};
2388}
2389class Enc_10bc21 : OpcodeHexagon {
2390  bits <4> Ii;
2391  let Inst{6-3} = Ii{3-0};
2392  bits <5> Rt32;
2393  let Inst{12-8} = Rt32{4-0};
2394  bits <5> Rx32;
2395  let Inst{20-16} = Rx32{4-0};
2396}
2397class Enc_1aaec1 : OpcodeHexagon {
2398  bits <3> Ii;
2399  let Inst{10-8} = Ii{2-0};
2400  bits <3> Os8;
2401  let Inst{2-0} = Os8{2-0};
2402  bits <5> Rx32;
2403  let Inst{20-16} = Rx32{4-0};
2404}
2405class Enc_329361 : OpcodeHexagon {
2406  bits <2> Pu4;
2407  let Inst{6-5} = Pu4{1-0};
2408  bits <5> Rss32;
2409  let Inst{20-16} = Rss32{4-0};
2410  bits <5> Rtt32;
2411  let Inst{12-8} = Rtt32{4-0};
2412  bits <5> Rdd32;
2413  let Inst{4-0} = Rdd32{4-0};
2414}
2415class Enc_d2c7f1 : OpcodeHexagon {
2416  bits <5> Rtt32;
2417  let Inst{12-8} = Rtt32{4-0};
2418  bits <5> Rss32;
2419  let Inst{20-16} = Rss32{4-0};
2420  bits <5> Rdd32;
2421  let Inst{4-0} = Rdd32{4-0};
2422  bits <2> Pe4;
2423  let Inst{6-5} = Pe4{1-0};
2424}
2425class Enc_3680c2 : OpcodeHexagon {
2426  bits <7> Ii;
2427  let Inst{11-5} = Ii{6-0};
2428  bits <5> Rss32;
2429  let Inst{20-16} = Rss32{4-0};
2430  bits <2> Pd4;
2431  let Inst{1-0} = Pd4{1-0};
2432}
2433class Enc_1ef990 : OpcodeHexagon {
2434  bits <2> Pv4;
2435  let Inst{12-11} = Pv4{1-0};
2436  bits <1> Mu2;
2437  let Inst{13-13} = Mu2{0-0};
2438  bits <5> Vs32;
2439  let Inst{4-0} = Vs32{4-0};
2440  bits <5> Rx32;
2441  let Inst{20-16} = Rx32{4-0};
2442}
2443class Enc_e957fb : OpcodeHexagon {
2444  bits <12> Ii;
2445  let Inst{26-25} = Ii{11-10};
2446  let Inst{13-13} = Ii{9-9};
2447  let Inst{7-0} = Ii{8-1};
2448  bits <5> Rs32;
2449  let Inst{20-16} = Rs32{4-0};
2450  bits <5> Rt32;
2451  let Inst{12-8} = Rt32{4-0};
2452}
2453class Enc_c0cdde : OpcodeHexagon {
2454  bits <9> Ii;
2455  let Inst{13-5} = Ii{8-0};
2456  bits <5> Rs32;
2457  let Inst{20-16} = Rs32{4-0};
2458  bits <2> Pd4;
2459  let Inst{1-0} = Pd4{1-0};
2460}
2461class Enc_c9e3bc : OpcodeHexagon {
2462  bits <4> Ii;
2463  let Inst{13-13} = Ii{3-3};
2464  let Inst{10-8} = Ii{2-0};
2465  bits <5> Rt32;
2466  let Inst{20-16} = Rt32{4-0};
2467  bits <5> Vs32;
2468  let Inst{4-0} = Vs32{4-0};
2469}
2470class Enc_2e1979 : OpcodeHexagon {
2471  bits <2> Ii;
2472  let Inst{13-13} = Ii{1-1};
2473  let Inst{7-7} = Ii{0-0};
2474  bits <2> Pv4;
2475  let Inst{6-5} = Pv4{1-0};
2476  bits <5> Rs32;
2477  let Inst{20-16} = Rs32{4-0};
2478  bits <5> Rt32;
2479  let Inst{12-8} = Rt32{4-0};
2480  bits <5> Rd32;
2481  let Inst{4-0} = Rd32{4-0};
2482}
2483class Enc_0b2e5b : OpcodeHexagon {
2484  bits <3> Ii;
2485  let Inst{7-5} = Ii{2-0};
2486  bits <5> Vu32;
2487  let Inst{12-8} = Vu32{4-0};
2488  bits <5> Vv32;
2489  let Inst{20-16} = Vv32{4-0};
2490  bits <5> Vd32;
2491  let Inst{4-0} = Vd32{4-0};
2492}
2493class Enc_6f83e7 : OpcodeHexagon {
2494  bits <2> Qv4;
2495  let Inst{23-22} = Qv4{1-0};
2496  bits <5> Vd32;
2497  let Inst{4-0} = Vd32{4-0};
2498}
2499class Enc_6339d5 : OpcodeHexagon {
2500  bits <2> Ii;
2501  let Inst{13-13} = Ii{1-1};
2502  let Inst{7-7} = Ii{0-0};
2503  bits <2> Pv4;
2504  let Inst{6-5} = Pv4{1-0};
2505  bits <5> Rs32;
2506  let Inst{20-16} = Rs32{4-0};
2507  bits <5> Ru32;
2508  let Inst{12-8} = Ru32{4-0};
2509  bits <5> Rt32;
2510  let Inst{4-0} = Rt32{4-0};
2511}
2512class Enc_d483b9 : OpcodeHexagon {
2513  bits <1> Ii;
2514  let Inst{5-5} = Ii{0-0};
2515  bits <5> Vuu32;
2516  let Inst{12-8} = Vuu32{4-0};
2517  bits <5> Rt32;
2518  let Inst{20-16} = Rt32{4-0};
2519  bits <5> Vxx32;
2520  let Inst{4-0} = Vxx32{4-0};
2521}
2522class Enc_51635c : OpcodeHexagon {
2523  bits <7> Ii;
2524  let Inst{8-4} = Ii{6-2};
2525  bits <4> Rd16;
2526  let Inst{3-0} = Rd16{3-0};
2527}
2528class Enc_e26546 : OpcodeHexagon {
2529  bits <5> Ii;
2530  let Inst{6-3} = Ii{4-1};
2531  bits <3> Nt8;
2532  let Inst{10-8} = Nt8{2-0};
2533  bits <5> Rx32;
2534  let Inst{20-16} = Rx32{4-0};
2535}
2536class Enc_70fb07 : OpcodeHexagon {
2537  bits <6> Ii;
2538  let Inst{13-8} = Ii{5-0};
2539  bits <5> Rss32;
2540  let Inst{20-16} = Rss32{4-0};
2541  bits <5> Rxx32;
2542  let Inst{4-0} = Rxx32{4-0};
2543}
2544class Enc_6c9ee0 : OpcodeHexagon {
2545  bits <3> Ii;
2546  let Inst{10-8} = Ii{2-0};
2547  bits <5> Rx32;
2548  let Inst{20-16} = Rx32{4-0};
2549}
2550class Enc_fa3ba4 : OpcodeHexagon {
2551  bits <14> Ii;
2552  let Inst{26-25} = Ii{13-12};
2553  let Inst{13-5} = Ii{11-3};
2554  bits <5> Rs32;
2555  let Inst{20-16} = Rs32{4-0};
2556  bits <5> Rdd32;
2557  let Inst{4-0} = Rdd32{4-0};
2558}
2559class Enc_44661f : OpcodeHexagon {
2560  bits <1> Mu2;
2561  let Inst{13-13} = Mu2{0-0};
2562  bits <5> Rx32;
2563  let Inst{20-16} = Rx32{4-0};
2564}
2565class Enc_277737 : OpcodeHexagon {
2566  bits <8> Ii;
2567  let Inst{22-21} = Ii{7-6};
2568  let Inst{13-13} = Ii{5-5};
2569  let Inst{7-5} = Ii{4-2};
2570  bits <5> Ru32;
2571  let Inst{4-0} = Ru32{4-0};
2572  bits <5> Rs32;
2573  let Inst{20-16} = Rs32{4-0};
2574  bits <5> Rd32;
2575  let Inst{12-8} = Rd32{4-0};
2576}
2577class Enc_5c124a : OpcodeHexagon {
2578  bits <19> Ii;
2579  let Inst{26-25} = Ii{18-17};
2580  let Inst{20-16} = Ii{16-12};
2581  let Inst{13-13} = Ii{11-11};
2582  let Inst{7-0} = Ii{10-3};
2583  bits <5> Rtt32;
2584  let Inst{12-8} = Rtt32{4-0};
2585}
2586class Enc_928ca1 : OpcodeHexagon {
2587  bits <1> Mu2;
2588  let Inst{13-13} = Mu2{0-0};
2589  bits <5> Rtt32;
2590  let Inst{12-8} = Rtt32{4-0};
2591  bits <5> Rx32;
2592  let Inst{20-16} = Rx32{4-0};
2593}
2594class Enc_da664b : OpcodeHexagon {
2595  bits <2> Ii;
2596  let Inst{13-13} = Ii{1-1};
2597  let Inst{7-7} = Ii{0-0};
2598  bits <5> Rs32;
2599  let Inst{20-16} = Rs32{4-0};
2600  bits <5> Rt32;
2601  let Inst{12-8} = Rt32{4-0};
2602  bits <5> Rd32;
2603  let Inst{4-0} = Rd32{4-0};
2604}
2605class Enc_47ee5e : OpcodeHexagon {
2606  bits <2> Ii;
2607  let Inst{13-13} = Ii{1-1};
2608  let Inst{7-7} = Ii{0-0};
2609  bits <2> Pv4;
2610  let Inst{6-5} = Pv4{1-0};
2611  bits <5> Rs32;
2612  let Inst{20-16} = Rs32{4-0};
2613  bits <5> Ru32;
2614  let Inst{12-8} = Ru32{4-0};
2615  bits <3> Nt8;
2616  let Inst{2-0} = Nt8{2-0};
2617}
2618class Enc_8bcba4 : OpcodeHexagon {
2619  bits <6> II;
2620  let Inst{5-0} = II{5-0};
2621  bits <5> Rt32;
2622  let Inst{12-8} = Rt32{4-0};
2623  bits <5> Re32;
2624  let Inst{20-16} = Re32{4-0};
2625}
2626class Enc_3a2484 : OpcodeHexagon {
2627  bits <11> Ii;
2628  let Inst{21-20} = Ii{10-9};
2629  let Inst{7-1} = Ii{8-2};
2630  bits <4> Rs16;
2631  let Inst{19-16} = Rs16{3-0};
2632  bits <4> n1;
2633  let Inst{28-28} = n1{3-3};
2634  let Inst{24-23} = n1{2-1};
2635  let Inst{13-13} = n1{0-0};
2636}
2637class Enc_a5ed8a : OpcodeHexagon {
2638  bits <5> Rt32;
2639  let Inst{20-16} = Rt32{4-0};
2640  bits <5> Vd32;
2641  let Inst{4-0} = Vd32{4-0};
2642}
2643class Enc_cb9321 : OpcodeHexagon {
2644  bits <16> Ii;
2645  let Inst{27-21} = Ii{15-9};
2646  let Inst{13-5} = Ii{8-0};
2647  bits <5> Rs32;
2648  let Inst{20-16} = Rs32{4-0};
2649  bits <5> Rd32;
2650  let Inst{4-0} = Rd32{4-0};
2651}
2652class Enc_668704 : OpcodeHexagon {
2653  bits <11> Ii;
2654  let Inst{21-20} = Ii{10-9};
2655  let Inst{7-1} = Ii{8-2};
2656  bits <4> Rs16;
2657  let Inst{19-16} = Rs16{3-0};
2658  bits <5> n1;
2659  let Inst{28-28} = n1{4-4};
2660  let Inst{25-22} = n1{3-0};
2661}
2662class Enc_a7341a : OpcodeHexagon {
2663  bits <5> Vu32;
2664  let Inst{12-8} = Vu32{4-0};
2665  bits <5> Vv32;
2666  let Inst{20-16} = Vv32{4-0};
2667  bits <5> Vx32;
2668  let Inst{4-0} = Vx32{4-0};
2669}
2670class Enc_5eac98 : OpcodeHexagon {
2671  bits <6> Ii;
2672  let Inst{13-8} = Ii{5-0};
2673  bits <5> Rss32;
2674  let Inst{20-16} = Rss32{4-0};
2675  bits <5> Rdd32;
2676  let Inst{4-0} = Rdd32{4-0};
2677}
2678class Enc_02553a : OpcodeHexagon {
2679  bits <7> Ii;
2680  let Inst{11-5} = Ii{6-0};
2681  bits <5> Rs32;
2682  let Inst{20-16} = Rs32{4-0};
2683  bits <2> Pd4;
2684  let Inst{1-0} = Pd4{1-0};
2685}
2686class Enc_acd6ed : OpcodeHexagon {
2687  bits <9> Ii;
2688  let Inst{10-5} = Ii{8-3};
2689  bits <2> Pt4;
2690  let Inst{12-11} = Pt4{1-0};
2691  bits <5> Rs32;
2692  let Inst{20-16} = Rs32{4-0};
2693  bits <5> Rdd32;
2694  let Inst{4-0} = Rdd32{4-0};
2695}
2696class Enc_8e583a : OpcodeHexagon {
2697  bits <11> Ii;
2698  let Inst{21-20} = Ii{10-9};
2699  let Inst{7-1} = Ii{8-2};
2700  bits <4> Rs16;
2701  let Inst{19-16} = Rs16{3-0};
2702  bits <5> n1;
2703  let Inst{28-28} = n1{4-4};
2704  let Inst{25-23} = n1{3-1};
2705  let Inst{13-13} = n1{0-0};
2706}
2707class Enc_b886fd : OpcodeHexagon {
2708  bits <5> Ii;
2709  let Inst{6-3} = Ii{4-1};
2710  bits <2> Pv4;
2711  let Inst{1-0} = Pv4{1-0};
2712  bits <5> Rt32;
2713  let Inst{12-8} = Rt32{4-0};
2714  bits <5> Rx32;
2715  let Inst{20-16} = Rx32{4-0};
2716}
2717class Enc_24a7dc : OpcodeHexagon {
2718  bits <5> Vu32;
2719  let Inst{12-8} = Vu32{4-0};
2720  bits <5> Vv32;
2721  let Inst{23-19} = Vv32{4-0};
2722  bits <3> Rt8;
2723  let Inst{18-16} = Rt8{2-0};
2724  bits <5> Vdd32;
2725  let Inst{4-0} = Vdd32{4-0};
2726}
2727class Enc_2d829e : OpcodeHexagon {
2728  bits <14> Ii;
2729  let Inst{10-0} = Ii{13-3};
2730  bits <5> Rs32;
2731  let Inst{20-16} = Rs32{4-0};
2732}
2733class Enc_4f4ed7 : OpcodeHexagon {
2734  bits <18> Ii;
2735  let Inst{26-25} = Ii{17-16};
2736  let Inst{20-16} = Ii{15-11};
2737  let Inst{13-5} = Ii{10-2};
2738  bits <5> Rd32;
2739  let Inst{4-0} = Rd32{4-0};
2740}
2741class Enc_84b2cd : OpcodeHexagon {
2742  bits <8> Ii;
2743  let Inst{12-7} = Ii{7-2};
2744  bits <5> II;
2745  let Inst{4-0} = II{4-0};
2746  bits <5> Rs32;
2747  let Inst{20-16} = Rs32{4-0};
2748}
2749class Enc_8dbdfe : OpcodeHexagon {
2750  bits <8> Ii;
2751  let Inst{13-13} = Ii{7-7};
2752  let Inst{7-3} = Ii{6-2};
2753  bits <2> Pv4;
2754  let Inst{1-0} = Pv4{1-0};
2755  bits <5> Rs32;
2756  let Inst{20-16} = Rs32{4-0};
2757  bits <3> Nt8;
2758  let Inst{10-8} = Nt8{2-0};
2759}
2760class Enc_90cd8b : OpcodeHexagon {
2761  bits <5> Rss32;
2762  let Inst{20-16} = Rss32{4-0};
2763  bits <5> Rd32;
2764  let Inst{4-0} = Rd32{4-0};
2765}
2766class Enc_bd0b33 : OpcodeHexagon {
2767  bits <10> Ii;
2768  let Inst{21-21} = Ii{9-9};
2769  let Inst{13-5} = Ii{8-0};
2770  bits <5> Rs32;
2771  let Inst{20-16} = Rs32{4-0};
2772  bits <2> Pd4;
2773  let Inst{1-0} = Pd4{1-0};
2774}
2775class Enc_8b8927 : OpcodeHexagon {
2776  bits <5> Rt32;
2777  let Inst{20-16} = Rt32{4-0};
2778  bits <1> Mu2;
2779  let Inst{13-13} = Mu2{0-0};
2780  bits <5> Vv32;
2781  let Inst{4-0} = Vv32{4-0};
2782}
2783class Enc_c7cd90 : OpcodeHexagon {
2784  bits <4> Ii;
2785  let Inst{6-3} = Ii{3-0};
2786  bits <3> Nt8;
2787  let Inst{10-8} = Nt8{2-0};
2788  bits <5> Rx32;
2789  let Inst{20-16} = Rx32{4-0};
2790}
2791class Enc_405228 : OpcodeHexagon {
2792  bits <11> Ii;
2793  let Inst{21-20} = Ii{10-9};
2794  let Inst{7-1} = Ii{8-2};
2795  bits <4> Rs16;
2796  let Inst{19-16} = Rs16{3-0};
2797  bits <3> n1;
2798  let Inst{28-28} = n1{2-2};
2799  let Inst{24-23} = n1{1-0};
2800}
2801class Enc_81ac1d : OpcodeHexagon {
2802  bits <24> Ii;
2803  let Inst{24-16} = Ii{23-15};
2804  let Inst{13-1} = Ii{14-2};
2805}
2806class Enc_395cc4 : OpcodeHexagon {
2807  bits <7> Ii;
2808  let Inst{6-3} = Ii{6-3};
2809  bits <1> Mu2;
2810  let Inst{13-13} = Mu2{0-0};
2811  bits <5> Rtt32;
2812  let Inst{12-8} = Rtt32{4-0};
2813  bits <5> Rx32;
2814  let Inst{20-16} = Rx32{4-0};
2815}
2816class Enc_a51a9a : OpcodeHexagon {
2817  bits <8> Ii;
2818  let Inst{12-8} = Ii{7-3};
2819  let Inst{4-2} = Ii{2-0};
2820}
2821class Enc_d44e31 : OpcodeHexagon {
2822  bits <6> Ii;
2823  let Inst{12-7} = Ii{5-0};
2824  bits <5> Rs32;
2825  let Inst{20-16} = Rs32{4-0};
2826  bits <5> Rt32;
2827  let Inst{4-0} = Rt32{4-0};
2828}
2829class Enc_f77fbc : OpcodeHexagon {
2830  bits <4> Ii;
2831  let Inst{13-13} = Ii{3-3};
2832  let Inst{10-8} = Ii{2-0};
2833  bits <5> Rt32;
2834  let Inst{20-16} = Rt32{4-0};
2835  bits <3> Os8;
2836  let Inst{2-0} = Os8{2-0};
2837}
2838class Enc_d2216a : OpcodeHexagon {
2839  bits <5> Rss32;
2840  let Inst{20-16} = Rss32{4-0};
2841  bits <5> Rtt32;
2842  let Inst{12-8} = Rtt32{4-0};
2843  bits <5> Rd32;
2844  let Inst{4-0} = Rd32{4-0};
2845}
2846class Enc_85bf58 : OpcodeHexagon {
2847  bits <7> Ii;
2848  let Inst{6-3} = Ii{6-3};
2849  bits <5> Rtt32;
2850  let Inst{12-8} = Rtt32{4-0};
2851  bits <5> Rx32;
2852  let Inst{20-16} = Rx32{4-0};
2853}
2854class Enc_71bb9b : OpcodeHexagon {
2855  bits <5> Vu32;
2856  let Inst{12-8} = Vu32{4-0};
2857  bits <5> Vv32;
2858  let Inst{20-16} = Vv32{4-0};
2859  bits <5> Vdd32;
2860  let Inst{4-0} = Vdd32{4-0};
2861}
2862class Enc_52a5dd : OpcodeHexagon {
2863  bits <4> Ii;
2864  let Inst{6-3} = Ii{3-0};
2865  bits <2> Pv4;
2866  let Inst{1-0} = Pv4{1-0};
2867  bits <3> Nt8;
2868  let Inst{10-8} = Nt8{2-0};
2869  bits <5> Rx32;
2870  let Inst{20-16} = Rx32{4-0};
2871}
2872class Enc_5e2823 : OpcodeHexagon {
2873  bits <5> Rs32;
2874  let Inst{20-16} = Rs32{4-0};
2875  bits <5> Rd32;
2876  let Inst{4-0} = Rd32{4-0};
2877}
2878class Enc_28a2dc : OpcodeHexagon {
2879  bits <5> Ii;
2880  let Inst{12-8} = Ii{4-0};
2881  bits <5> Rs32;
2882  let Inst{20-16} = Rs32{4-0};
2883  bits <5> Rx32;
2884  let Inst{4-0} = Rx32{4-0};
2885}
2886class Enc_5138b3 : OpcodeHexagon {
2887  bits <5> Vu32;
2888  let Inst{12-8} = Vu32{4-0};
2889  bits <5> Rt32;
2890  let Inst{20-16} = Rt32{4-0};
2891  bits <5> Vx32;
2892  let Inst{4-0} = Vx32{4-0};
2893}
2894class Enc_84d359 : OpcodeHexagon {
2895  bits <4> Ii;
2896  let Inst{3-0} = Ii{3-0};
2897  bits <4> Rs16;
2898  let Inst{7-4} = Rs16{3-0};
2899}
2900class Enc_e07374 : OpcodeHexagon {
2901  bits <5> Rs32;
2902  let Inst{20-16} = Rs32{4-0};
2903  bits <5> Rtt32;
2904  let Inst{12-8} = Rtt32{4-0};
2905  bits <5> Rd32;
2906  let Inst{4-0} = Rd32{4-0};
2907}
2908class Enc_e0820b : OpcodeHexagon {
2909  bits <5> Vu32;
2910  let Inst{12-8} = Vu32{4-0};
2911  bits <5> Vv32;
2912  let Inst{20-16} = Vv32{4-0};
2913  bits <2> Qs4;
2914  let Inst{6-5} = Qs4{1-0};
2915  bits <5> Vd32;
2916  let Inst{4-0} = Vd32{4-0};
2917}
2918class Enc_323f2d : OpcodeHexagon {
2919  bits <6> II;
2920  let Inst{11-8} = II{5-2};
2921  let Inst{6-5} = II{1-0};
2922  bits <5> Rd32;
2923  let Inst{4-0} = Rd32{4-0};
2924  bits <5> Re32;
2925  let Inst{20-16} = Re32{4-0};
2926}
2927class Enc_1a9974 : OpcodeHexagon {
2928  bits <2> Ii;
2929  let Inst{13-13} = Ii{1-1};
2930  let Inst{7-7} = Ii{0-0};
2931  bits <2> Pv4;
2932  let Inst{6-5} = Pv4{1-0};
2933  bits <5> Rs32;
2934  let Inst{20-16} = Rs32{4-0};
2935  bits <5> Ru32;
2936  let Inst{12-8} = Ru32{4-0};
2937  bits <5> Rtt32;
2938  let Inst{4-0} = Rtt32{4-0};
2939}
2940class Enc_5de85f : OpcodeHexagon {
2941  bits <11> Ii;
2942  let Inst{21-20} = Ii{10-9};
2943  let Inst{7-1} = Ii{8-2};
2944  bits <5> Rt32;
2945  let Inst{12-8} = Rt32{4-0};
2946  bits <3> Ns8;
2947  let Inst{18-16} = Ns8{2-0};
2948}
2949class Enc_dd766a : OpcodeHexagon {
2950  bits <5> Vu32;
2951  let Inst{12-8} = Vu32{4-0};
2952  bits <5> Vdd32;
2953  let Inst{4-0} = Vdd32{4-0};
2954}
2955class Enc_0b51ce : OpcodeHexagon {
2956  bits <3> Ii;
2957  let Inst{10-8} = Ii{2-0};
2958  bits <2> Qv4;
2959  let Inst{12-11} = Qv4{1-0};
2960  bits <5> Vs32;
2961  let Inst{4-0} = Vs32{4-0};
2962  bits <5> Rx32;
2963  let Inst{20-16} = Rx32{4-0};
2964}
2965class Enc_b4e6cf : OpcodeHexagon {
2966  bits <10> Ii;
2967  let Inst{21-21} = Ii{9-9};
2968  let Inst{13-5} = Ii{8-0};
2969  bits <5> Ru32;
2970  let Inst{4-0} = Ru32{4-0};
2971  bits <5> Rx32;
2972  let Inst{20-16} = Rx32{4-0};
2973}
2974class Enc_44215c : OpcodeHexagon {
2975  bits <6> Ii;
2976  let Inst{17-16} = Ii{5-4};
2977  let Inst{6-3} = Ii{3-0};
2978  bits <2> Pv4;
2979  let Inst{1-0} = Pv4{1-0};
2980  bits <3> Nt8;
2981  let Inst{10-8} = Nt8{2-0};
2982}
2983class Enc_0aa344 : OpcodeHexagon {
2984  bits <5> Gss32;
2985  let Inst{20-16} = Gss32{4-0};
2986  bits <5> Rdd32;
2987  let Inst{4-0} = Rdd32{4-0};
2988}
2989class Enc_a21d47 : OpcodeHexagon {
2990  bits <6> Ii;
2991  let Inst{10-5} = Ii{5-0};
2992  bits <2> Pt4;
2993  let Inst{12-11} = Pt4{1-0};
2994  bits <5> Rs32;
2995  let Inst{20-16} = Rs32{4-0};
2996  bits <5> Rd32;
2997  let Inst{4-0} = Rd32{4-0};
2998}
2999class Enc_cc449f : OpcodeHexagon {
3000  bits <4> Ii;
3001  let Inst{6-3} = Ii{3-0};
3002  bits <2> Pv4;
3003  let Inst{1-0} = Pv4{1-0};
3004  bits <5> Rt32;
3005  let Inst{12-8} = Rt32{4-0};
3006  bits <5> Rx32;
3007  let Inst{20-16} = Rx32{4-0};
3008}
3009class Enc_645d54 : OpcodeHexagon {
3010  bits <2> Ii;
3011  let Inst{13-13} = Ii{1-1};
3012  let Inst{5-5} = Ii{0-0};
3013  bits <5> Rss32;
3014  let Inst{20-16} = Rss32{4-0};
3015  bits <5> Rt32;
3016  let Inst{12-8} = Rt32{4-0};
3017  bits <5> Rdd32;
3018  let Inst{4-0} = Rdd32{4-0};
3019}
3020class Enc_667b39 : OpcodeHexagon {
3021  bits <5> Css32;
3022  let Inst{20-16} = Css32{4-0};
3023  bits <5> Rdd32;
3024  let Inst{4-0} = Rdd32{4-0};
3025}
3026class Enc_927852 : OpcodeHexagon {
3027  bits <5> Rss32;
3028  let Inst{20-16} = Rss32{4-0};
3029  bits <5> Rt32;
3030  let Inst{12-8} = Rt32{4-0};
3031  bits <5> Rdd32;
3032  let Inst{4-0} = Rdd32{4-0};
3033}
3034class Enc_163a3c : OpcodeHexagon {
3035  bits <7> Ii;
3036  let Inst{12-7} = Ii{6-1};
3037  bits <5> Rs32;
3038  let Inst{20-16} = Rs32{4-0};
3039  bits <5> Rt32;
3040  let Inst{4-0} = Rt32{4-0};
3041}
3042class Enc_a75aa6 : OpcodeHexagon {
3043  bits <5> Rs32;
3044  let Inst{20-16} = Rs32{4-0};
3045  bits <5> Rt32;
3046  let Inst{12-8} = Rt32{4-0};
3047  bits <1> Mu2;
3048  let Inst{13-13} = Mu2{0-0};
3049}
3050class Enc_b087ac : OpcodeHexagon {
3051  bits <5> Vu32;
3052  let Inst{12-8} = Vu32{4-0};
3053  bits <5> Rt32;
3054  let Inst{20-16} = Rt32{4-0};
3055  bits <5> Vd32;
3056  let Inst{4-0} = Vd32{4-0};
3057}
3058class Enc_691712 : OpcodeHexagon {
3059  bits <2> Pv4;
3060  let Inst{12-11} = Pv4{1-0};
3061  bits <1> Mu2;
3062  let Inst{13-13} = Mu2{0-0};
3063  bits <5> Rx32;
3064  let Inst{20-16} = Rx32{4-0};
3065}
3066class Enc_b1e1fb : OpcodeHexagon {
3067  bits <11> Ii;
3068  let Inst{21-20} = Ii{10-9};
3069  let Inst{7-1} = Ii{8-2};
3070  bits <4> Rs16;
3071  let Inst{19-16} = Rs16{3-0};
3072  bits <5> n1;
3073  let Inst{28-28} = n1{4-4};
3074  let Inst{25-23} = n1{3-1};
3075  let Inst{8-8} = n1{0-0};
3076}
3077class Enc_1f19b5 : OpcodeHexagon {
3078  bits <5> Ii;
3079  let Inst{9-5} = Ii{4-0};
3080  bits <5> Rss32;
3081  let Inst{20-16} = Rss32{4-0};
3082  bits <2> Pd4;
3083  let Inst{1-0} = Pd4{1-0};
3084}
3085class Enc_b8c967 : OpcodeHexagon {
3086  bits <8> Ii;
3087  let Inst{12-5} = Ii{7-0};
3088  bits <5> Rs32;
3089  let Inst{20-16} = Rs32{4-0};
3090  bits <5> Rd32;
3091  let Inst{4-0} = Rd32{4-0};
3092}
3093class Enc_fb6577 : OpcodeHexagon {
3094  bits <2> Pu4;
3095  let Inst{9-8} = Pu4{1-0};
3096  bits <5> Rs32;
3097  let Inst{20-16} = Rs32{4-0};
3098  bits <5> Rd32;
3099  let Inst{4-0} = Rd32{4-0};
3100}
3101class Enc_2bae10 : OpcodeHexagon {
3102  bits <4> Ii;
3103  let Inst{10-8} = Ii{3-1};
3104  bits <4> Rs16;
3105  let Inst{7-4} = Rs16{3-0};
3106  bits <4> Rd16;
3107  let Inst{3-0} = Rd16{3-0};
3108}
3109class Enc_c4dc92 : OpcodeHexagon {
3110  bits <2> Qv4;
3111  let Inst{23-22} = Qv4{1-0};
3112  bits <5> Vu32;
3113  let Inst{12-8} = Vu32{4-0};
3114  bits <5> Vd32;
3115  let Inst{4-0} = Vd32{4-0};
3116}
3117class Enc_03833b : OpcodeHexagon {
3118  bits <5> Rss32;
3119  let Inst{20-16} = Rss32{4-0};
3120  bits <5> Rt32;
3121  let Inst{12-8} = Rt32{4-0};
3122  bits <2> Pd4;
3123  let Inst{1-0} = Pd4{1-0};
3124}
3125class Enc_dbd70c : OpcodeHexagon {
3126  bits <5> Rss32;
3127  let Inst{20-16} = Rss32{4-0};
3128  bits <5> Rtt32;
3129  let Inst{12-8} = Rtt32{4-0};
3130  bits <2> Pu4;
3131  let Inst{6-5} = Pu4{1-0};
3132  bits <5> Rdd32;
3133  let Inst{4-0} = Rdd32{4-0};
3134}
3135class Enc_f6fe0b : OpcodeHexagon {
3136  bits <11> Ii;
3137  let Inst{21-20} = Ii{10-9};
3138  let Inst{7-1} = Ii{8-2};
3139  bits <4> Rs16;
3140  let Inst{19-16} = Rs16{3-0};
3141  bits <6> n1;
3142  let Inst{28-28} = n1{5-5};
3143  let Inst{24-22} = n1{4-2};
3144  let Inst{13-13} = n1{1-1};
3145  let Inst{8-8} = n1{0-0};
3146}
3147class Enc_9e2e1c : OpcodeHexagon {
3148  bits <5> Ii;
3149  let Inst{8-5} = Ii{4-1};
3150  bits <1> Mu2;
3151  let Inst{13-13} = Mu2{0-0};
3152  bits <5> Ryy32;
3153  let Inst{4-0} = Ryy32{4-0};
3154  bits <5> Rx32;
3155  let Inst{20-16} = Rx32{4-0};
3156}
3157class Enc_8df4be : OpcodeHexagon {
3158  bits <17> Ii;
3159  let Inst{26-25} = Ii{16-15};
3160  let Inst{20-16} = Ii{14-10};
3161  let Inst{13-5} = Ii{9-1};
3162  bits <5> Rd32;
3163  let Inst{4-0} = Rd32{4-0};
3164}
3165class Enc_66bce1 : OpcodeHexagon {
3166  bits <11> Ii;
3167  let Inst{21-20} = Ii{10-9};
3168  let Inst{7-1} = Ii{8-2};
3169  bits <4> Rs16;
3170  let Inst{19-16} = Rs16{3-0};
3171  bits <4> Rd16;
3172  let Inst{11-8} = Rd16{3-0};
3173}
3174class Enc_b8309d : OpcodeHexagon {
3175  bits <9> Ii;
3176  let Inst{8-3} = Ii{8-3};
3177  bits <3> Rtt8;
3178  let Inst{2-0} = Rtt8{2-0};
3179}
3180class Enc_5e8512 : OpcodeHexagon {
3181  bits <5> Vu32;
3182  let Inst{12-8} = Vu32{4-0};
3183  bits <5> Rt32;
3184  let Inst{20-16} = Rt32{4-0};
3185  bits <5> Vxx32;
3186  let Inst{4-0} = Vxx32{4-0};
3187}
3188class Enc_4f677b : OpcodeHexagon {
3189  bits <2> Ii;
3190  let Inst{13-13} = Ii{1-1};
3191  let Inst{7-7} = Ii{0-0};
3192  bits <6> II;
3193  let Inst{11-8} = II{5-2};
3194  let Inst{6-5} = II{1-0};
3195  bits <5> Rt32;
3196  let Inst{20-16} = Rt32{4-0};
3197  bits <5> Rd32;
3198  let Inst{4-0} = Rd32{4-0};
3199}
3200class Enc_3d920a : OpcodeHexagon {
3201  bits <6> Ii;
3202  let Inst{8-5} = Ii{5-2};
3203  bits <5> Rd32;
3204  let Inst{4-0} = Rd32{4-0};
3205  bits <5> Rx32;
3206  let Inst{20-16} = Rx32{4-0};
3207}
3208class Enc_e83554 : OpcodeHexagon {
3209  bits <5> Ii;
3210  let Inst{8-5} = Ii{4-1};
3211  bits <1> Mu2;
3212  let Inst{13-13} = Mu2{0-0};
3213  bits <5> Rd32;
3214  let Inst{4-0} = Rd32{4-0};
3215  bits <5> Rx32;
3216  let Inst{20-16} = Rx32{4-0};
3217}
3218class Enc_ed48be : OpcodeHexagon {
3219  bits <2> Ii;
3220  let Inst{6-5} = Ii{1-0};
3221  bits <3> Rdd8;
3222  let Inst{2-0} = Rdd8{2-0};
3223}
3224class Enc_f8c1c4 : OpcodeHexagon {
3225  bits <2> Pv4;
3226  let Inst{12-11} = Pv4{1-0};
3227  bits <1> Mu2;
3228  let Inst{13-13} = Mu2{0-0};
3229  bits <5> Vd32;
3230  let Inst{4-0} = Vd32{4-0};
3231  bits <5> Rx32;
3232  let Inst{20-16} = Rx32{4-0};
3233}
3234class Enc_1aa186 : OpcodeHexagon {
3235  bits <5> Rss32;
3236  let Inst{20-16} = Rss32{4-0};
3237  bits <5> Rt32;
3238  let Inst{12-8} = Rt32{4-0};
3239  bits <5> Rxx32;
3240  let Inst{4-0} = Rxx32{4-0};
3241}
3242class Enc_134437 : OpcodeHexagon {
3243  bits <2> Qs4;
3244  let Inst{9-8} = Qs4{1-0};
3245  bits <2> Qt4;
3246  let Inst{23-22} = Qt4{1-0};
3247  bits <2> Qd4;
3248  let Inst{1-0} = Qd4{1-0};
3249}
3250class Enc_f3f408 : OpcodeHexagon {
3251  bits <4> Ii;
3252  let Inst{13-13} = Ii{3-3};
3253  let Inst{10-8} = Ii{2-0};
3254  bits <5> Rt32;
3255  let Inst{20-16} = Rt32{4-0};
3256  bits <5> Vd32;
3257  let Inst{4-0} = Vd32{4-0};
3258}
3259class Enc_97d666 : OpcodeHexagon {
3260  bits <4> Rs16;
3261  let Inst{7-4} = Rs16{3-0};
3262  bits <4> Rd16;
3263  let Inst{3-0} = Rd16{3-0};
3264}
3265class Enc_f82eaf : OpcodeHexagon {
3266  bits <8> Ii;
3267  let Inst{10-5} = Ii{7-2};
3268  bits <2> Pt4;
3269  let Inst{12-11} = Pt4{1-0};
3270  bits <5> Rs32;
3271  let Inst{20-16} = Rs32{4-0};
3272  bits <5> Rd32;
3273  let Inst{4-0} = Rd32{4-0};
3274}
3275class Enc_69d63b : OpcodeHexagon {
3276  bits <11> Ii;
3277  let Inst{21-20} = Ii{10-9};
3278  let Inst{7-1} = Ii{8-2};
3279  bits <3> Ns8;
3280  let Inst{18-16} = Ns8{2-0};
3281}
3282class Enc_f79415 : OpcodeHexagon {
3283  bits <2> Ii;
3284  let Inst{13-13} = Ii{1-1};
3285  let Inst{6-6} = Ii{0-0};
3286  bits <6> II;
3287  let Inst{5-0} = II{5-0};
3288  bits <5> Ru32;
3289  let Inst{20-16} = Ru32{4-0};
3290  bits <5> Rtt32;
3291  let Inst{12-8} = Rtt32{4-0};
3292}
3293class Enc_ce6828 : OpcodeHexagon {
3294  bits <14> Ii;
3295  let Inst{26-25} = Ii{13-12};
3296  let Inst{13-13} = Ii{11-11};
3297  let Inst{7-0} = Ii{10-3};
3298  bits <5> Rs32;
3299  let Inst{20-16} = Rs32{4-0};
3300  bits <5> Rtt32;
3301  let Inst{12-8} = Rtt32{4-0};
3302}
3303class Enc_800e04 : OpcodeHexagon {
3304  bits <11> Ii;
3305  let Inst{21-20} = Ii{10-9};
3306  let Inst{7-1} = Ii{8-2};
3307  bits <4> Rs16;
3308  let Inst{19-16} = Rs16{3-0};
3309  bits <6> n1;
3310  let Inst{28-28} = n1{5-5};
3311  let Inst{25-22} = n1{4-1};
3312  let Inst{13-13} = n1{0-0};
3313}
3314class Enc_ad1831 : OpcodeHexagon {
3315  bits <16> Ii;
3316  let Inst{26-25} = Ii{15-14};
3317  let Inst{20-16} = Ii{13-9};
3318  let Inst{13-13} = Ii{8-8};
3319  let Inst{7-0} = Ii{7-0};
3320  bits <3> Nt8;
3321  let Inst{10-8} = Nt8{2-0};
3322}
3323class Enc_0fa531 : OpcodeHexagon {
3324  bits <15> Ii;
3325  let Inst{21-21} = Ii{14-14};
3326  let Inst{13-13} = Ii{13-13};
3327  let Inst{11-1} = Ii{12-2};
3328  bits <5> Rs32;
3329  let Inst{20-16} = Rs32{4-0};
3330}
3331class Enc_7eaeb6 : OpcodeHexagon {
3332  bits <6> Ii;
3333  let Inst{6-3} = Ii{5-2};
3334  bits <2> Pv4;
3335  let Inst{1-0} = Pv4{1-0};
3336  bits <5> Rt32;
3337  let Inst{12-8} = Rt32{4-0};
3338  bits <5> Rx32;
3339  let Inst{20-16} = Rx32{4-0};
3340}
3341class Enc_f55a0c : OpcodeHexagon {
3342  bits <6> Ii;
3343  let Inst{11-8} = Ii{5-2};
3344  bits <4> Rs16;
3345  let Inst{7-4} = Rs16{3-0};
3346  bits <4> Rt16;
3347  let Inst{3-0} = Rt16{3-0};
3348}
3349class Enc_f20719 : OpcodeHexagon {
3350  bits <7> Ii;
3351  let Inst{12-7} = Ii{6-1};
3352  bits <6> II;
3353  let Inst{13-13} = II{5-5};
3354  let Inst{4-0} = II{4-0};
3355  bits <2> Pv4;
3356  let Inst{6-5} = Pv4{1-0};
3357  bits <5> Rs32;
3358  let Inst{20-16} = Rs32{4-0};
3359}
3360class Enc_eafd18 : OpcodeHexagon {
3361  bits <5> II;
3362  let Inst{12-8} = II{4-0};
3363  bits <11> Ii;
3364  let Inst{21-20} = Ii{10-9};
3365  let Inst{7-1} = Ii{8-2};
3366  bits <3> Ns8;
3367  let Inst{18-16} = Ns8{2-0};
3368}
3369class Enc_7b523d : OpcodeHexagon {
3370  bits <5> Vu32;
3371  let Inst{12-8} = Vu32{4-0};
3372  bits <5> Vv32;
3373  let Inst{23-19} = Vv32{4-0};
3374  bits <3> Rt8;
3375  let Inst{18-16} = Rt8{2-0};
3376  bits <5> Vxx32;
3377  let Inst{4-0} = Vxx32{4-0};
3378}
3379class Enc_47ef61 : OpcodeHexagon {
3380  bits <3> Ii;
3381  let Inst{7-5} = Ii{2-0};
3382  bits <5> Rt32;
3383  let Inst{12-8} = Rt32{4-0};
3384  bits <5> Rs32;
3385  let Inst{20-16} = Rs32{4-0};
3386  bits <5> Rd32;
3387  let Inst{4-0} = Rd32{4-0};
3388}
3389class Enc_cc857d : OpcodeHexagon {
3390  bits <5> Vuu32;
3391  let Inst{12-8} = Vuu32{4-0};
3392  bits <5> Rt32;
3393  let Inst{20-16} = Rt32{4-0};
3394  bits <5> Vx32;
3395  let Inst{4-0} = Vx32{4-0};
3396}
3397class Enc_7fa7f6 : OpcodeHexagon {
3398  bits <6> II;
3399  let Inst{11-8} = II{5-2};
3400  let Inst{6-5} = II{1-0};
3401  bits <5> Rdd32;
3402  let Inst{4-0} = Rdd32{4-0};
3403  bits <5> Re32;
3404  let Inst{20-16} = Re32{4-0};
3405}
3406class Enc_0f8bab : OpcodeHexagon {
3407  bits <5> Vu32;
3408  let Inst{12-8} = Vu32{4-0};
3409  bits <5> Rt32;
3410  let Inst{20-16} = Rt32{4-0};
3411  bits <2> Qd4;
3412  let Inst{1-0} = Qd4{1-0};
3413}
3414class Enc_7eb485 : OpcodeHexagon {
3415  bits <2> Ii;
3416  let Inst{13-13} = Ii{1-1};
3417  let Inst{6-6} = Ii{0-0};
3418  bits <6> II;
3419  let Inst{5-0} = II{5-0};
3420  bits <5> Ru32;
3421  let Inst{20-16} = Ru32{4-0};
3422  bits <3> Nt8;
3423  let Inst{10-8} = Nt8{2-0};
3424}
3425class Enc_864a5a : OpcodeHexagon {
3426  bits <9> Ii;
3427  let Inst{12-8} = Ii{8-4};
3428  let Inst{4-3} = Ii{3-2};
3429  bits <5> Rs32;
3430  let Inst{20-16} = Rs32{4-0};
3431}
3432class Enc_c2b48e : OpcodeHexagon {
3433  bits <5> Rs32;
3434  let Inst{20-16} = Rs32{4-0};
3435  bits <5> Rt32;
3436  let Inst{12-8} = Rt32{4-0};
3437  bits <2> Pd4;
3438  let Inst{1-0} = Pd4{1-0};
3439}
3440class Enc_8c6530 : OpcodeHexagon {
3441  bits <5> Rtt32;
3442  let Inst{12-8} = Rtt32{4-0};
3443  bits <5> Rss32;
3444  let Inst{20-16} = Rss32{4-0};
3445  bits <2> Pu4;
3446  let Inst{6-5} = Pu4{1-0};
3447  bits <5> Rdd32;
3448  let Inst{4-0} = Rdd32{4-0};
3449}
3450class Enc_448f7f : OpcodeHexagon {
3451  bits <11> Ii;
3452  let Inst{26-25} = Ii{10-9};
3453  let Inst{13-13} = Ii{8-8};
3454  let Inst{7-0} = Ii{7-0};
3455  bits <5> Rs32;
3456  let Inst{20-16} = Rs32{4-0};
3457  bits <5> Rt32;
3458  let Inst{12-8} = Rt32{4-0};
3459}
3460class Enc_da8d43 : OpcodeHexagon {
3461  bits <6> Ii;
3462  let Inst{13-13} = Ii{5-5};
3463  let Inst{7-3} = Ii{4-0};
3464  bits <2> Pv4;
3465  let Inst{1-0} = Pv4{1-0};
3466  bits <5> Rs32;
3467  let Inst{20-16} = Rs32{4-0};
3468  bits <5> Rt32;
3469  let Inst{12-8} = Rt32{4-0};
3470}
3471class Enc_a6ce9c : OpcodeHexagon {
3472  bits <6> Ii;
3473  let Inst{3-0} = Ii{5-2};
3474  bits <4> Rs16;
3475  let Inst{7-4} = Rs16{3-0};
3476}
3477class Enc_3b7631 : OpcodeHexagon {
3478  bits <5> Vu32;
3479  let Inst{12-8} = Vu32{4-0};
3480  bits <5> Vdddd32;
3481  let Inst{4-0} = Vdddd32{4-0};
3482  bits <3> Rx8;
3483  let Inst{18-16} = Rx8{2-0};
3484}
3485class Enc_eca7c8 : OpcodeHexagon {
3486  bits <2> Ii;
3487  let Inst{13-13} = Ii{1-1};
3488  let Inst{7-7} = Ii{0-0};
3489  bits <5> Rs32;
3490  let Inst{20-16} = Rs32{4-0};
3491  bits <5> Ru32;
3492  let Inst{12-8} = Ru32{4-0};
3493  bits <5> Rt32;
3494  let Inst{4-0} = Rt32{4-0};
3495}
3496class Enc_4b39e4 : OpcodeHexagon {
3497  bits <3> Ii;
3498  let Inst{7-5} = Ii{2-0};
3499  bits <5> Vu32;
3500  let Inst{12-8} = Vu32{4-0};
3501  bits <5> Vv32;
3502  let Inst{20-16} = Vv32{4-0};
3503  bits <5> Vdd32;
3504  let Inst{4-0} = Vdd32{4-0};
3505}
3506