1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
16 #include "HexagonHazardRecognizer.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetOpcodes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/MC/MCInstrItineraries.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MachineValueType.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61
62 using namespace llvm;
63
64 #define DEBUG_TYPE "hexagon-instrinfo"
65
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
68 #include "HexagonDepTimingClasses.h"
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74 "packetization boundary."));
75
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
80 cl::Hidden, cl::ZeroOrMore, cl::init(false),
81 cl::desc("Disable schedule adjustment for new value stores."));
82
83 static cl::opt<bool> EnableTimingClassLatency(
84 "enable-timing-class-latency", cl::Hidden, cl::init(false),
85 cl::desc("Enable timing class latency"));
86
87 static cl::opt<bool> EnableALUForwarding(
88 "enable-alu-forwarding", cl::Hidden, cl::init(true),
89 cl::desc("Enable vec alu forwarding"));
90
91 static cl::opt<bool> EnableACCForwarding(
92 "enable-acc-forwarding", cl::Hidden, cl::init(true),
93 cl::desc("Enable vec acc forwarding"));
94
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
99 cl::init(true), cl::Hidden, cl::ZeroOrMore,
100 cl::desc("Use the DFA based hazard recognizer."));
101
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113
114 // Pin the vtable to this file.
anchor()115 void HexagonInstrInfo::anchor() {}
116
HexagonInstrInfo(HexagonSubtarget & ST)117 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119 Subtarget(ST) {}
120
isIntRegForSubInst(unsigned Reg)121 static bool isIntRegForSubInst(unsigned Reg) {
122 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
123 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
124 }
125
isDblRegForSubInst(unsigned Reg,const HexagonRegisterInfo & HRI)126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
127 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
129 }
130
131 /// Calculate number of instructions excluding the debug instructions.
nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,MachineBasicBlock::const_instr_iterator MIE)132 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
133 MachineBasicBlock::const_instr_iterator MIE) {
134 unsigned Count = 0;
135 for (; MIB != MIE; ++MIB) {
136 if (!MIB->isDebugInstr())
137 ++Count;
138 }
139 return Count;
140 }
141
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
findLoopInstr(MachineBasicBlock * BB,unsigned EndLoopOp,MachineBasicBlock * TargetBB,SmallPtrSet<MachineBasicBlock *,8> & Visited) const146 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
147 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
148 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
149 unsigned LOOPi;
150 unsigned LOOPr;
151 if (EndLoopOp == Hexagon::ENDLOOP0) {
152 LOOPi = Hexagon::J2_loop0i;
153 LOOPr = Hexagon::J2_loop0r;
154 } else { // EndLoopOp == Hexagon::EndLOOP1
155 LOOPi = Hexagon::J2_loop1i;
156 LOOPr = Hexagon::J2_loop1r;
157 }
158
159 // The loop set-up instruction will be in a predecessor block
160 for (MachineBasicBlock *PB : BB->predecessors()) {
161 // If this has been visited, already skip it.
162 if (!Visited.insert(PB).second)
163 continue;
164 if (PB == BB)
165 continue;
166 for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
167 unsigned Opc = I->getOpcode();
168 if (Opc == LOOPi || Opc == LOOPr)
169 return &*I;
170 // We've reached a different loop, which means the loop01 has been
171 // removed.
172 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
173 return nullptr;
174 }
175 // Check the predecessors for the LOOP instruction.
176 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
177 return Loop;
178 }
179 return nullptr;
180 }
181
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
parseOperands(const MachineInstr & MI,SmallVector<unsigned,4> & Defs,SmallVector<unsigned,8> & Uses)185 static inline void parseOperands(const MachineInstr &MI,
186 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
187 Defs.clear();
188 Uses.clear();
189
190 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
191 const MachineOperand &MO = MI.getOperand(i);
192
193 if (!MO.isReg())
194 continue;
195
196 Register Reg = MO.getReg();
197 if (!Reg)
198 continue;
199
200 if (MO.isUse())
201 Uses.push_back(MO.getReg());
202
203 if (MO.isDef())
204 Defs.push_back(MO.getReg());
205 }
206 }
207
208 // Position dependent, so check twice for swap.
isDuplexPairMatch(unsigned Ga,unsigned Gb)209 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
210 switch (Ga) {
211 case HexagonII::HSIG_None:
212 default:
213 return false;
214 case HexagonII::HSIG_L1:
215 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
216 case HexagonII::HSIG_L2:
217 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218 Gb == HexagonII::HSIG_A);
219 case HexagonII::HSIG_S1:
220 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
222 case HexagonII::HSIG_S2:
223 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
225 Gb == HexagonII::HSIG_A);
226 case HexagonII::HSIG_A:
227 return (Gb == HexagonII::HSIG_A);
228 case HexagonII::HSIG_Compound:
229 return (Gb == HexagonII::HSIG_Compound);
230 }
231 return false;
232 }
233
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const239 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
240 int &FrameIndex) const {
241 switch (MI.getOpcode()) {
242 default:
243 break;
244 case Hexagon::L2_loadri_io:
245 case Hexagon::L2_loadrd_io:
246 case Hexagon::V6_vL32b_ai:
247 case Hexagon::V6_vL32b_nt_ai:
248 case Hexagon::V6_vL32Ub_ai:
249 case Hexagon::LDriw_pred:
250 case Hexagon::LDriw_ctr:
251 case Hexagon::PS_vloadrq_ai:
252 case Hexagon::PS_vloadrw_ai:
253 case Hexagon::PS_vloadrw_nt_ai: {
254 const MachineOperand OpFI = MI.getOperand(1);
255 if (!OpFI.isFI())
256 return 0;
257 const MachineOperand OpOff = MI.getOperand(2);
258 if (!OpOff.isImm() || OpOff.getImm() != 0)
259 return 0;
260 FrameIndex = OpFI.getIndex();
261 return MI.getOperand(0).getReg();
262 }
263
264 case Hexagon::L2_ploadrit_io:
265 case Hexagon::L2_ploadrif_io:
266 case Hexagon::L2_ploadrdt_io:
267 case Hexagon::L2_ploadrdf_io: {
268 const MachineOperand OpFI = MI.getOperand(2);
269 if (!OpFI.isFI())
270 return 0;
271 const MachineOperand OpOff = MI.getOperand(3);
272 if (!OpOff.isImm() || OpOff.getImm() != 0)
273 return 0;
274 FrameIndex = OpFI.getIndex();
275 return MI.getOperand(0).getReg();
276 }
277 }
278
279 return 0;
280 }
281
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const287 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
288 int &FrameIndex) const {
289 switch (MI.getOpcode()) {
290 default:
291 break;
292 case Hexagon::S2_storerb_io:
293 case Hexagon::S2_storerh_io:
294 case Hexagon::S2_storeri_io:
295 case Hexagon::S2_storerd_io:
296 case Hexagon::V6_vS32b_ai:
297 case Hexagon::V6_vS32Ub_ai:
298 case Hexagon::STriw_pred:
299 case Hexagon::STriw_ctr:
300 case Hexagon::PS_vstorerq_ai:
301 case Hexagon::PS_vstorerw_ai: {
302 const MachineOperand &OpFI = MI.getOperand(0);
303 if (!OpFI.isFI())
304 return 0;
305 const MachineOperand &OpOff = MI.getOperand(1);
306 if (!OpOff.isImm() || OpOff.getImm() != 0)
307 return 0;
308 FrameIndex = OpFI.getIndex();
309 return MI.getOperand(2).getReg();
310 }
311
312 case Hexagon::S2_pstorerbt_io:
313 case Hexagon::S2_pstorerbf_io:
314 case Hexagon::S2_pstorerht_io:
315 case Hexagon::S2_pstorerhf_io:
316 case Hexagon::S2_pstorerit_io:
317 case Hexagon::S2_pstorerif_io:
318 case Hexagon::S2_pstorerdt_io:
319 case Hexagon::S2_pstorerdf_io: {
320 const MachineOperand &OpFI = MI.getOperand(1);
321 if (!OpFI.isFI())
322 return 0;
323 const MachineOperand &OpOff = MI.getOperand(2);
324 if (!OpOff.isImm() || OpOff.getImm() != 0)
325 return 0;
326 FrameIndex = OpFI.getIndex();
327 return MI.getOperand(3).getReg();
328 }
329 }
330
331 return 0;
332 }
333
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
hasLoadFromStackSlot(const MachineInstr & MI,SmallVectorImpl<const MachineMemOperand * > & Accesses) const337 bool HexagonInstrInfo::hasLoadFromStackSlot(
338 const MachineInstr &MI,
339 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
340 if (MI.isBundle()) {
341 const MachineBasicBlock *MBB = MI.getParent();
342 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
343 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
344 if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
345 return true;
346 return false;
347 }
348
349 return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
350 }
351
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
hasStoreToStackSlot(const MachineInstr & MI,SmallVectorImpl<const MachineMemOperand * > & Accesses) const355 bool HexagonInstrInfo::hasStoreToStackSlot(
356 const MachineInstr &MI,
357 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
358 if (MI.isBundle()) {
359 const MachineBasicBlock *MBB = MI.getParent();
360 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
361 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
362 if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
363 return true;
364 return false;
365 }
366
367 return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
368 }
369
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
376 /// Cond[0] = Jump_c
377 /// Cond[1] = p
378 /// HW-loop ENDLOOP:
379 /// Cond[0] = ENDLOOP
380 /// Cond[1] = MBB
381 /// New value jump:
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
383 /// Cond[1] = R
384 /// Cond[2] = Imm
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const385 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
386 MachineBasicBlock *&TBB,
387 MachineBasicBlock *&FBB,
388 SmallVectorImpl<MachineOperand> &Cond,
389 bool AllowModify) const {
390 TBB = nullptr;
391 FBB = nullptr;
392 Cond.clear();
393
394 // If the block has no terminators, it just falls into the block after it.
395 MachineBasicBlock::instr_iterator I = MBB.instr_end();
396 if (I == MBB.instr_begin())
397 return false;
398
399 // A basic block may looks like this:
400 //
401 // [ insn
402 // EH_LABEL
403 // insn
404 // insn
405 // insn
406 // EH_LABEL
407 // insn ]
408 //
409 // It has two succs but does not have a terminator
410 // Don't know how to handle it.
411 do {
412 --I;
413 if (I->isEHLabel())
414 // Don't analyze EH branches.
415 return true;
416 } while (I != MBB.instr_begin());
417
418 I = MBB.instr_end();
419 --I;
420
421 while (I->isDebugInstr()) {
422 if (I == MBB.instr_begin())
423 return false;
424 --I;
425 }
426
427 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
428 I->getOperand(0).isMBB();
429 // Delete the J2_jump if it's equivalent to a fall-through.
430 if (AllowModify && JumpToBlock &&
431 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
432 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433 I->eraseFromParent();
434 I = MBB.instr_end();
435 if (I == MBB.instr_begin())
436 return false;
437 --I;
438 }
439 if (!isUnpredicatedTerminator(*I))
440 return false;
441
442 // Get the last instruction in the block.
443 MachineInstr *LastInst = &*I;
444 MachineInstr *SecondLastInst = nullptr;
445 // Find one more terminator if present.
446 while (true) {
447 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
448 if (!SecondLastInst)
449 SecondLastInst = &*I;
450 else
451 // This is a third branch.
452 return true;
453 }
454 if (I == MBB.instr_begin())
455 break;
456 --I;
457 }
458
459 int LastOpcode = LastInst->getOpcode();
460 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
461 // If the branch target is not a basic block, it could be a tail call.
462 // (It is, if the target is a function.)
463 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
464 return true;
465 if (SecLastOpcode == Hexagon::J2_jump &&
466 !SecondLastInst->getOperand(0).isMBB())
467 return true;
468
469 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
470 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
471
472 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
473 return true;
474
475 // If there is only one terminator instruction, process it.
476 if (LastInst && !SecondLastInst) {
477 if (LastOpcode == Hexagon::J2_jump) {
478 TBB = LastInst->getOperand(0).getMBB();
479 return false;
480 }
481 if (isEndLoopN(LastOpcode)) {
482 TBB = LastInst->getOperand(0).getMBB();
483 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
484 Cond.push_back(LastInst->getOperand(0));
485 return false;
486 }
487 if (LastOpcodeHasJMP_c) {
488 TBB = LastInst->getOperand(1).getMBB();
489 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490 Cond.push_back(LastInst->getOperand(0));
491 return false;
492 }
493 // Only supporting rr/ri versions of new-value jumps.
494 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
495 TBB = LastInst->getOperand(2).getMBB();
496 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
497 Cond.push_back(LastInst->getOperand(0));
498 Cond.push_back(LastInst->getOperand(1));
499 return false;
500 }
501 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
502 << " with one jump\n";);
503 // Otherwise, don't know what this is.
504 return true;
505 }
506
507 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
508 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
509 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
510 if (!SecondLastInst->getOperand(1).isMBB())
511 return true;
512 TBB = SecondLastInst->getOperand(1).getMBB();
513 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
514 Cond.push_back(SecondLastInst->getOperand(0));
515 FBB = LastInst->getOperand(0).getMBB();
516 return false;
517 }
518
519 // Only supporting rr/ri versions of new-value jumps.
520 if (SecLastOpcodeHasNVJump &&
521 (SecondLastInst->getNumExplicitOperands() == 3) &&
522 (LastOpcode == Hexagon::J2_jump)) {
523 TBB = SecondLastInst->getOperand(2).getMBB();
524 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525 Cond.push_back(SecondLastInst->getOperand(0));
526 Cond.push_back(SecondLastInst->getOperand(1));
527 FBB = LastInst->getOperand(0).getMBB();
528 return false;
529 }
530
531 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532 // executed, so remove it.
533 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
534 TBB = SecondLastInst->getOperand(0).getMBB();
535 I = LastInst->getIterator();
536 if (AllowModify)
537 I->eraseFromParent();
538 return false;
539 }
540
541 // If the block ends with an ENDLOOP, and J2_jump, handle it.
542 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
543 TBB = SecondLastInst->getOperand(0).getMBB();
544 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
545 Cond.push_back(SecondLastInst->getOperand(0));
546 FBB = LastInst->getOperand(0).getMBB();
547 return false;
548 }
549 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550 << " with two jumps";);
551 // Otherwise, can't handle this.
552 return true;
553 }
554
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const555 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
556 int *BytesRemoved) const {
557 assert(!BytesRemoved && "code size not handled");
558
559 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
560 MachineBasicBlock::iterator I = MBB.end();
561 unsigned Count = 0;
562 while (I != MBB.begin()) {
563 --I;
564 if (I->isDebugInstr())
565 continue;
566 // Only removing branches from end of MBB.
567 if (!I->isBranch())
568 return Count;
569 if (Count && (I->getOpcode() == Hexagon::J2_jump))
570 llvm_unreachable("Malformed basic block: unconditional branch not last");
571 MBB.erase(&MBB.back());
572 I = MBB.end();
573 ++Count;
574 }
575 return Count;
576 }
577
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const578 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
579 MachineBasicBlock *TBB,
580 MachineBasicBlock *FBB,
581 ArrayRef<MachineOperand> Cond,
582 const DebugLoc &DL,
583 int *BytesAdded) const {
584 unsigned BOpc = Hexagon::J2_jump;
585 unsigned BccOpc = Hexagon::J2_jumpt;
586 assert(validateBranchCond(Cond) && "Invalid branching condition");
587 assert(TBB && "insertBranch must not be told to insert a fallthrough");
588 assert(!BytesAdded && "code size not handled");
589
590 // Check if reverseBranchCondition has asked to reverse this branch
591 // If we want to reverse the branch an odd number of times, we want
592 // J2_jumpf.
593 if (!Cond.empty() && Cond[0].isImm())
594 BccOpc = Cond[0].getImm();
595
596 if (!FBB) {
597 if (Cond.empty()) {
598 // Due to a bug in TailMerging/CFG Optimization, we need to add a
599 // special case handling of a predicated jump followed by an
600 // unconditional jump. If not, Tail Merging and CFG Optimization go
601 // into an infinite loop.
602 MachineBasicBlock *NewTBB, *NewFBB;
603 SmallVector<MachineOperand, 4> Cond;
604 auto Term = MBB.getFirstTerminator();
605 if (Term != MBB.end() && isPredicated(*Term) &&
606 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
607 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
608 reverseBranchCondition(Cond);
609 removeBranch(MBB);
610 return insertBranch(MBB, TBB, nullptr, Cond, DL);
611 }
612 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
613 } else if (isEndLoopN(Cond[0].getImm())) {
614 int EndLoopOp = Cond[0].getImm();
615 assert(Cond[1].isMBB());
616 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617 // Check for it, and change the BB target if needed.
618 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
619 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
620 VisitedBBs);
621 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
622 Loop->getOperand(0).setMBB(TBB);
623 // Add the ENDLOOP after the finding the LOOP0.
624 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
625 } else if (isNewValueJump(Cond[0].getImm())) {
626 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
627 // New value jump
628 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
631 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632 << printMBBReference(MBB););
633 if (Cond[2].isReg()) {
634 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637 } else if(Cond[2].isImm()) {
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639 addImm(Cond[2].getImm()).addMBB(TBB);
640 } else
641 llvm_unreachable("Invalid condition for branching");
642 } else {
643 assert((Cond.size() == 2) && "Malformed cond vector");
644 const MachineOperand &RO = Cond[1];
645 unsigned Flags = getUndefRegState(RO.isUndef());
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647 }
648 return 1;
649 }
650 assert((!Cond.empty()) &&
651 "Cond. cannot be empty when multiple branchings are required");
652 assert((!isNewValueJump(Cond[0].getImm())) &&
653 "NV-jump cannot be inserted with another branch");
654 // Special case for hardware loops. The condition is a basic block.
655 if (isEndLoopN(Cond[0].getImm())) {
656 int EndLoopOp = Cond[0].getImm();
657 assert(Cond[1].isMBB());
658 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659 // Check for it, and change the BB target if needed.
660 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
661 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662 VisitedBBs);
663 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664 Loop->getOperand(0).setMBB(TBB);
665 // Add the ENDLOOP after the finding the LOOP0.
666 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667 } else {
668 const MachineOperand &RO = Cond[1];
669 unsigned Flags = getUndefRegState(RO.isUndef());
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671 }
672 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673
674 return 2;
675 }
676
677 namespace {
678 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
679 MachineInstr *Loop, *EndLoop;
680 MachineFunction *MF;
681 const HexagonInstrInfo *TII;
682 int64_t TripCount;
683 Register LoopCount;
684 DebugLoc DL;
685
686 public:
HexagonPipelinerLoopInfo(MachineInstr * Loop,MachineInstr * EndLoop)687 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
688 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
689 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
690 DL(Loop->getDebugLoc()) {
691 // Inspect the Loop instruction up-front, as it may be deleted when we call
692 // createTripCountGreaterCondition.
693 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
694 ? -1
695 : Loop->getOperand(1).getImm();
696 if (TripCount == -1)
697 LoopCount = Loop->getOperand(1).getReg();
698 }
699
shouldIgnoreForPipelining(const MachineInstr * MI) const700 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
701 // Only ignore the terminator.
702 return MI == EndLoop;
703 }
704
705 Optional<bool>
createTripCountGreaterCondition(int TC,MachineBasicBlock & MBB,SmallVectorImpl<MachineOperand> & Cond)706 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
707 SmallVectorImpl<MachineOperand> &Cond) override {
708 if (TripCount == -1) {
709 // Check if we're done with the loop.
710 unsigned Done = TII->createVR(MF, MVT::i1);
711 MachineInstr *NewCmp = BuildMI(&MBB, DL,
712 TII->get(Hexagon::C2_cmpgtui), Done)
713 .addReg(LoopCount)
714 .addImm(TC);
715 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
716 Cond.push_back(NewCmp->getOperand(0));
717 return {};
718 }
719
720 return TripCount > TC;
721 }
722
setPreheader(MachineBasicBlock * NewPreheader)723 void setPreheader(MachineBasicBlock *NewPreheader) override {
724 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
725 Loop);
726 }
727
adjustTripCount(int TripCountAdjust)728 void adjustTripCount(int TripCountAdjust) override {
729 // If the loop trip count is a compile-time value, then just change the
730 // value.
731 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
732 Loop->getOpcode() == Hexagon::J2_loop1i) {
733 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
734 assert(TripCount > 0 && "Can't create an empty or negative loop!");
735 Loop->getOperand(1).setImm(TripCount);
736 return;
737 }
738
739 // The loop trip count is a run-time value. We generate code to subtract
740 // one from the trip count, and update the loop instruction.
741 Register LoopCount = Loop->getOperand(1).getReg();
742 Register NewLoopCount = TII->createVR(MF, MVT::i32);
743 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
744 TII->get(Hexagon::A2_addi), NewLoopCount)
745 .addReg(LoopCount)
746 .addImm(TripCountAdjust);
747 Loop->getOperand(1).setReg(NewLoopCount);
748 }
749
disposed()750 void disposed() override { Loop->eraseFromParent(); }
751 };
752 } // namespace
753
754 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
analyzeLoopForPipelining(MachineBasicBlock * LoopBB) const755 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
756 // We really "analyze" only hardware loops right now.
757 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
758
759 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
760 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
761 MachineInstr *LoopInst = findLoopInstr(
762 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
763 if (LoopInst)
764 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
765 }
766 return nullptr;
767 }
768
isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability) const769 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
770 unsigned NumCycles, unsigned ExtraPredCycles,
771 BranchProbability Probability) const {
772 return nonDbgBBSize(&MBB) <= 3;
773 }
774
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumTCycles,unsigned ExtraTCycles,MachineBasicBlock & FMBB,unsigned NumFCycles,unsigned ExtraFCycles,BranchProbability Probability) const775 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
776 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
777 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
778 const {
779 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
780 }
781
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumInstrs,BranchProbability Probability) const782 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
783 unsigned NumInstrs, BranchProbability Probability) const {
784 return NumInstrs <= 4;
785 }
786
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const787 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
788 MachineBasicBlock::iterator I,
789 const DebugLoc &DL, MCRegister DestReg,
790 MCRegister SrcReg, bool KillSrc) const {
791 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
792 unsigned KillFlag = getKillRegState(KillSrc);
793
794 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
795 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
796 .addReg(SrcReg, KillFlag);
797 return;
798 }
799 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
800 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
801 .addReg(SrcReg, KillFlag);
802 return;
803 }
804 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
805 // Map Pd = Ps to Pd = or(Ps, Ps).
806 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
807 .addReg(SrcReg).addReg(SrcReg, KillFlag);
808 return;
809 }
810 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
811 Hexagon::IntRegsRegClass.contains(SrcReg)) {
812 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
813 .addReg(SrcReg, KillFlag);
814 return;
815 }
816 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
817 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
818 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
819 .addReg(SrcReg, KillFlag);
820 return;
821 }
822 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
823 Hexagon::IntRegsRegClass.contains(SrcReg)) {
824 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
825 .addReg(SrcReg, KillFlag);
826 return;
827 }
828 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
829 Hexagon::IntRegsRegClass.contains(DestReg)) {
830 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
831 .addReg(SrcReg, KillFlag);
832 return;
833 }
834 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
835 Hexagon::PredRegsRegClass.contains(DestReg)) {
836 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
837 .addReg(SrcReg, KillFlag);
838 return;
839 }
840 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
841 Hexagon::IntRegsRegClass.contains(DestReg)) {
842 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
843 .addReg(SrcReg, KillFlag);
844 return;
845 }
846 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
847 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
848 addReg(SrcReg, KillFlag);
849 return;
850 }
851 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
852 Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
853 Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
854 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
855 .addReg(HiSrc, KillFlag)
856 .addReg(LoSrc, KillFlag);
857 return;
858 }
859 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
860 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
861 .addReg(SrcReg)
862 .addReg(SrcReg, KillFlag);
863 return;
864 }
865 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
866 Hexagon::HvxVRRegClass.contains(DestReg)) {
867 llvm_unreachable("Unimplemented pred to vec");
868 return;
869 }
870 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
871 Hexagon::HvxVRRegClass.contains(SrcReg)) {
872 llvm_unreachable("Unimplemented vec to pred");
873 return;
874 }
875
876 #ifndef NDEBUG
877 // Show the invalid registers to ease debugging.
878 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
879 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
880 #endif
881 llvm_unreachable("Unimplemented");
882 }
883
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const884 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
885 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
886 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
887 DebugLoc DL = MBB.findDebugLoc(I);
888 MachineFunction &MF = *MBB.getParent();
889 MachineFrameInfo &MFI = MF.getFrameInfo();
890 unsigned SlotAlign = MFI.getObjectAlignment(FI);
891 unsigned KillFlag = getKillRegState(isKill);
892
893 MachineMemOperand *MMO = MF.getMachineMemOperand(
894 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
895 MFI.getObjectSize(FI), SlotAlign);
896
897 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
898 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
899 .addFrameIndex(FI).addImm(0)
900 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
901 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
902 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
903 .addFrameIndex(FI).addImm(0)
904 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
905 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
906 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
907 .addFrameIndex(FI).addImm(0)
908 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
909 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
910 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
911 .addFrameIndex(FI).addImm(0)
912 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
913 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
914 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
915 .addFrameIndex(FI).addImm(0)
916 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
917 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
918 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
919 .addFrameIndex(FI).addImm(0)
920 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
921 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
922 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
923 .addFrameIndex(FI).addImm(0)
924 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
925 } else {
926 llvm_unreachable("Unimplemented");
927 }
928 }
929
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const930 void HexagonInstrInfo::loadRegFromStackSlot(
931 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
932 int FI, const TargetRegisterClass *RC,
933 const TargetRegisterInfo *TRI) const {
934 DebugLoc DL = MBB.findDebugLoc(I);
935 MachineFunction &MF = *MBB.getParent();
936 MachineFrameInfo &MFI = MF.getFrameInfo();
937 unsigned SlotAlign = MFI.getObjectAlignment(FI);
938
939 MachineMemOperand *MMO = MF.getMachineMemOperand(
940 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
941 MFI.getObjectSize(FI), SlotAlign);
942
943 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
944 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
945 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
946 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
947 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
948 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
949 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
950 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
951 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
952 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
953 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
954 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
955 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
956 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
957 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
959 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
960 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
962 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
963 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964 } else {
965 llvm_unreachable("Can't store this register to stack slot");
966 }
967 }
968
getLiveRegsAt(LivePhysRegs & Regs,const MachineInstr & MI)969 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
970 const MachineBasicBlock &B = *MI.getParent();
971 Regs.addLiveOuts(B);
972 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
973 for (auto I = B.rbegin(); I != E; ++I)
974 Regs.stepBackward(*I);
975 }
976
977 /// expandPostRAPseudo - This function is called for all pseudo instructions
978 /// that remain after register allocation. Many pseudo instructions are
979 /// created to help register allocation. This is the place to convert them
980 /// into real instructions. The target can edit MI in place, or it can insert
981 /// new instructions and erase MI. The function should return true if
982 /// anything was changed.
expandPostRAPseudo(MachineInstr & MI) const983 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
984 MachineBasicBlock &MBB = *MI.getParent();
985 MachineFunction &MF = *MBB.getParent();
986 MachineRegisterInfo &MRI = MF.getRegInfo();
987 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
988 DebugLoc DL = MI.getDebugLoc();
989 unsigned Opc = MI.getOpcode();
990
991 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
992 Register Mx = MI.getOperand(MxOp).getReg();
993 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
994 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
995 .add(MI.getOperand((HasImm ? 5 : 4)));
996 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
997 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
998 if (HasImm)
999 MIB.add(MI.getOperand(4));
1000 MIB.addReg(CSx, RegState::Implicit);
1001 MBB.erase(MI);
1002 return true;
1003 };
1004
1005 auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) {
1006 if (MI.memoperands().empty())
1007 return false;
1008 return all_of(MI.memoperands(),
1009 [NeedAlign] (const MachineMemOperand *MMO) {
1010 return NeedAlign <= MMO->getAlignment();
1011 });
1012 };
1013
1014 switch (Opc) {
1015 case TargetOpcode::COPY: {
1016 MachineOperand &MD = MI.getOperand(0);
1017 MachineOperand &MS = MI.getOperand(1);
1018 MachineBasicBlock::iterator MBBI = MI.getIterator();
1019 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1020 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1021 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1022 }
1023 MBB.erase(MBBI);
1024 return true;
1025 }
1026 case Hexagon::PS_aligna:
1027 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1028 .addReg(HRI.getFrameRegister())
1029 .addImm(-MI.getOperand(1).getImm());
1030 MBB.erase(MI);
1031 return true;
1032 case Hexagon::V6_vassignp: {
1033 Register SrcReg = MI.getOperand(1).getReg();
1034 Register DstReg = MI.getOperand(0).getReg();
1035 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1036 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1037 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1038 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1039 MBB.erase(MI);
1040 return true;
1041 }
1042 case Hexagon::V6_lo: {
1043 Register SrcReg = MI.getOperand(1).getReg();
1044 Register DstReg = MI.getOperand(0).getReg();
1045 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1046 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1047 MBB.erase(MI);
1048 MRI.clearKillFlags(SrcSubLo);
1049 return true;
1050 }
1051 case Hexagon::V6_hi: {
1052 Register SrcReg = MI.getOperand(1).getReg();
1053 Register DstReg = MI.getOperand(0).getReg();
1054 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1055 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1056 MBB.erase(MI);
1057 MRI.clearKillFlags(SrcSubHi);
1058 return true;
1059 }
1060 case Hexagon::PS_vloadrv_ai: {
1061 Register DstReg = MI.getOperand(0).getReg();
1062 const MachineOperand &BaseOp = MI.getOperand(1);
1063 assert(BaseOp.getSubReg() == 0);
1064 int Offset = MI.getOperand(2).getImm();
1065 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1066 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1067 : Hexagon::V6_vL32Ub_ai;
1068 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1069 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1070 .addImm(Offset)
1071 .cloneMemRefs(MI);
1072 MBB.erase(MI);
1073 return true;
1074 }
1075 case Hexagon::PS_vloadrw_ai: {
1076 Register DstReg = MI.getOperand(0).getReg();
1077 const MachineOperand &BaseOp = MI.getOperand(1);
1078 assert(BaseOp.getSubReg() == 0);
1079 int Offset = MI.getOperand(2).getImm();
1080 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1081 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1082 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1083 : Hexagon::V6_vL32Ub_ai;
1084 BuildMI(MBB, MI, DL, get(NewOpc),
1085 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1086 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1087 .addImm(Offset)
1088 .cloneMemRefs(MI);
1089 BuildMI(MBB, MI, DL, get(NewOpc),
1090 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1091 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1092 .addImm(Offset + VecOffset)
1093 .cloneMemRefs(MI);
1094 MBB.erase(MI);
1095 return true;
1096 }
1097 case Hexagon::PS_vstorerv_ai: {
1098 const MachineOperand &SrcOp = MI.getOperand(2);
1099 assert(SrcOp.getSubReg() == 0);
1100 const MachineOperand &BaseOp = MI.getOperand(0);
1101 assert(BaseOp.getSubReg() == 0);
1102 int Offset = MI.getOperand(1).getImm();
1103 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1104 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1105 : Hexagon::V6_vS32Ub_ai;
1106 BuildMI(MBB, MI, DL, get(NewOpc))
1107 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1108 .addImm(Offset)
1109 .addReg(SrcOp.getReg(), getRegState(SrcOp))
1110 .cloneMemRefs(MI);
1111 MBB.erase(MI);
1112 return true;
1113 }
1114 case Hexagon::PS_vstorerw_ai: {
1115 Register SrcReg = MI.getOperand(2).getReg();
1116 const MachineOperand &BaseOp = MI.getOperand(0);
1117 assert(BaseOp.getSubReg() == 0);
1118 int Offset = MI.getOperand(1).getImm();
1119 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1120 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1121 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1122 : Hexagon::V6_vS32Ub_ai;
1123 BuildMI(MBB, MI, DL, get(NewOpc))
1124 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1125 .addImm(Offset)
1126 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1127 .cloneMemRefs(MI);
1128 BuildMI(MBB, MI, DL, get(NewOpc))
1129 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1130 .addImm(Offset + VecOffset)
1131 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1132 .cloneMemRefs(MI);
1133 MBB.erase(MI);
1134 return true;
1135 }
1136 case Hexagon::PS_true: {
1137 Register Reg = MI.getOperand(0).getReg();
1138 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1139 .addReg(Reg, RegState::Undef)
1140 .addReg(Reg, RegState::Undef);
1141 MBB.erase(MI);
1142 return true;
1143 }
1144 case Hexagon::PS_false: {
1145 Register Reg = MI.getOperand(0).getReg();
1146 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1147 .addReg(Reg, RegState::Undef)
1148 .addReg(Reg, RegState::Undef);
1149 MBB.erase(MI);
1150 return true;
1151 }
1152 case Hexagon::PS_qtrue: {
1153 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1154 .addReg(Hexagon::V0, RegState::Undef)
1155 .addReg(Hexagon::V0, RegState::Undef);
1156 MBB.erase(MI);
1157 return true;
1158 }
1159 case Hexagon::PS_qfalse: {
1160 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1161 .addReg(Hexagon::V0, RegState::Undef)
1162 .addReg(Hexagon::V0, RegState::Undef);
1163 MBB.erase(MI);
1164 return true;
1165 }
1166 case Hexagon::PS_vdd0: {
1167 Register Vd = MI.getOperand(0).getReg();
1168 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1169 .addReg(Vd, RegState::Undef)
1170 .addReg(Vd, RegState::Undef);
1171 MBB.erase(MI);
1172 return true;
1173 }
1174 case Hexagon::PS_vmulw: {
1175 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1176 Register DstReg = MI.getOperand(0).getReg();
1177 Register Src1Reg = MI.getOperand(1).getReg();
1178 Register Src2Reg = MI.getOperand(2).getReg();
1179 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1180 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1181 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1182 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1183 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1184 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1185 .addReg(Src1SubHi)
1186 .addReg(Src2SubHi);
1187 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1188 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1189 .addReg(Src1SubLo)
1190 .addReg(Src2SubLo);
1191 MBB.erase(MI);
1192 MRI.clearKillFlags(Src1SubHi);
1193 MRI.clearKillFlags(Src1SubLo);
1194 MRI.clearKillFlags(Src2SubHi);
1195 MRI.clearKillFlags(Src2SubLo);
1196 return true;
1197 }
1198 case Hexagon::PS_vmulw_acc: {
1199 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1200 Register DstReg = MI.getOperand(0).getReg();
1201 Register Src1Reg = MI.getOperand(1).getReg();
1202 Register Src2Reg = MI.getOperand(2).getReg();
1203 Register Src3Reg = MI.getOperand(3).getReg();
1204 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1205 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1206 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1207 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1208 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1209 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1210 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1211 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1212 .addReg(Src1SubHi)
1213 .addReg(Src2SubHi)
1214 .addReg(Src3SubHi);
1215 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1216 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1217 .addReg(Src1SubLo)
1218 .addReg(Src2SubLo)
1219 .addReg(Src3SubLo);
1220 MBB.erase(MI);
1221 MRI.clearKillFlags(Src1SubHi);
1222 MRI.clearKillFlags(Src1SubLo);
1223 MRI.clearKillFlags(Src2SubHi);
1224 MRI.clearKillFlags(Src2SubLo);
1225 MRI.clearKillFlags(Src3SubHi);
1226 MRI.clearKillFlags(Src3SubLo);
1227 return true;
1228 }
1229 case Hexagon::PS_pselect: {
1230 const MachineOperand &Op0 = MI.getOperand(0);
1231 const MachineOperand &Op1 = MI.getOperand(1);
1232 const MachineOperand &Op2 = MI.getOperand(2);
1233 const MachineOperand &Op3 = MI.getOperand(3);
1234 Register Rd = Op0.getReg();
1235 Register Pu = Op1.getReg();
1236 Register Rs = Op2.getReg();
1237 Register Rt = Op3.getReg();
1238 DebugLoc DL = MI.getDebugLoc();
1239 unsigned K1 = getKillRegState(Op1.isKill());
1240 unsigned K2 = getKillRegState(Op2.isKill());
1241 unsigned K3 = getKillRegState(Op3.isKill());
1242 if (Rd != Rs)
1243 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1244 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1245 .addReg(Rs, K2);
1246 if (Rd != Rt)
1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1248 .addReg(Pu, K1)
1249 .addReg(Rt, K3);
1250 MBB.erase(MI);
1251 return true;
1252 }
1253 case Hexagon::PS_vselect: {
1254 const MachineOperand &Op0 = MI.getOperand(0);
1255 const MachineOperand &Op1 = MI.getOperand(1);
1256 const MachineOperand &Op2 = MI.getOperand(2);
1257 const MachineOperand &Op3 = MI.getOperand(3);
1258 LivePhysRegs LiveAtMI(HRI);
1259 getLiveRegsAt(LiveAtMI, MI);
1260 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1261 Register PReg = Op1.getReg();
1262 assert(Op1.getSubReg() == 0);
1263 unsigned PState = getRegState(Op1);
1264
1265 if (Op0.getReg() != Op2.getReg()) {
1266 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1267 : PState;
1268 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1269 .add(Op0)
1270 .addReg(PReg, S)
1271 .add(Op2);
1272 if (IsDestLive)
1273 T.addReg(Op0.getReg(), RegState::Implicit);
1274 IsDestLive = true;
1275 }
1276 if (Op0.getReg() != Op3.getReg()) {
1277 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1278 .add(Op0)
1279 .addReg(PReg, PState)
1280 .add(Op3);
1281 if (IsDestLive)
1282 T.addReg(Op0.getReg(), RegState::Implicit);
1283 }
1284 MBB.erase(MI);
1285 return true;
1286 }
1287 case Hexagon::PS_wselect: {
1288 MachineOperand &Op0 = MI.getOperand(0);
1289 MachineOperand &Op1 = MI.getOperand(1);
1290 MachineOperand &Op2 = MI.getOperand(2);
1291 MachineOperand &Op3 = MI.getOperand(3);
1292 LivePhysRegs LiveAtMI(HRI);
1293 getLiveRegsAt(LiveAtMI, MI);
1294 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1295 Register PReg = Op1.getReg();
1296 assert(Op1.getSubReg() == 0);
1297 unsigned PState = getRegState(Op1);
1298
1299 if (Op0.getReg() != Op2.getReg()) {
1300 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1301 : PState;
1302 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1303 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1304 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1305 .add(Op0)
1306 .addReg(PReg, S)
1307 .addReg(SrcHi)
1308 .addReg(SrcLo);
1309 if (IsDestLive)
1310 T.addReg(Op0.getReg(), RegState::Implicit);
1311 IsDestLive = true;
1312 }
1313 if (Op0.getReg() != Op3.getReg()) {
1314 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1315 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1316 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1317 .add(Op0)
1318 .addReg(PReg, PState)
1319 .addReg(SrcHi)
1320 .addReg(SrcLo);
1321 if (IsDestLive)
1322 T.addReg(Op0.getReg(), RegState::Implicit);
1323 }
1324 MBB.erase(MI);
1325 return true;
1326 }
1327
1328 case Hexagon::PS_crash: {
1329 // Generate a misaligned load that is guaranteed to cause a crash.
1330 class CrashPseudoSourceValue : public PseudoSourceValue {
1331 public:
1332 CrashPseudoSourceValue(const TargetInstrInfo &TII)
1333 : PseudoSourceValue(TargetCustom, TII) {}
1334
1335 bool isConstant(const MachineFrameInfo *) const override {
1336 return false;
1337 }
1338 bool isAliased(const MachineFrameInfo *) const override {
1339 return false;
1340 }
1341 bool mayAlias(const MachineFrameInfo *) const override {
1342 return false;
1343 }
1344 void printCustom(raw_ostream &OS) const override {
1345 OS << "MisalignedCrash";
1346 }
1347 };
1348
1349 static const CrashPseudoSourceValue CrashPSV(*this);
1350 MachineMemOperand *MMO = MF.getMachineMemOperand(
1351 MachinePointerInfo(&CrashPSV),
1352 MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1);
1353 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1354 .addImm(0xBADC0FEE) // Misaligned load.
1355 .addMemOperand(MMO);
1356 MBB.erase(MI);
1357 return true;
1358 }
1359
1360 case Hexagon::PS_tailcall_i:
1361 MI.setDesc(get(Hexagon::J2_jump));
1362 return true;
1363 case Hexagon::PS_tailcall_r:
1364 case Hexagon::PS_jmpret:
1365 MI.setDesc(get(Hexagon::J2_jumpr));
1366 return true;
1367 case Hexagon::PS_jmprett:
1368 MI.setDesc(get(Hexagon::J2_jumprt));
1369 return true;
1370 case Hexagon::PS_jmpretf:
1371 MI.setDesc(get(Hexagon::J2_jumprf));
1372 return true;
1373 case Hexagon::PS_jmprettnewpt:
1374 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1375 return true;
1376 case Hexagon::PS_jmpretfnewpt:
1377 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1378 return true;
1379 case Hexagon::PS_jmprettnew:
1380 MI.setDesc(get(Hexagon::J2_jumprtnew));
1381 return true;
1382 case Hexagon::PS_jmpretfnew:
1383 MI.setDesc(get(Hexagon::J2_jumprfnew));
1384 return true;
1385
1386 case Hexagon::PS_loadrub_pci:
1387 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1388 case Hexagon::PS_loadrb_pci:
1389 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1390 case Hexagon::PS_loadruh_pci:
1391 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1392 case Hexagon::PS_loadrh_pci:
1393 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1394 case Hexagon::PS_loadri_pci:
1395 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1396 case Hexagon::PS_loadrd_pci:
1397 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1398 case Hexagon::PS_loadrub_pcr:
1399 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1400 case Hexagon::PS_loadrb_pcr:
1401 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1402 case Hexagon::PS_loadruh_pcr:
1403 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1404 case Hexagon::PS_loadrh_pcr:
1405 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1406 case Hexagon::PS_loadri_pcr:
1407 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1408 case Hexagon::PS_loadrd_pcr:
1409 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1410 case Hexagon::PS_storerb_pci:
1411 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1412 case Hexagon::PS_storerh_pci:
1413 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1414 case Hexagon::PS_storerf_pci:
1415 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1416 case Hexagon::PS_storeri_pci:
1417 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1418 case Hexagon::PS_storerd_pci:
1419 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1420 case Hexagon::PS_storerb_pcr:
1421 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1422 case Hexagon::PS_storerh_pcr:
1423 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1424 case Hexagon::PS_storerf_pcr:
1425 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1426 case Hexagon::PS_storeri_pcr:
1427 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1428 case Hexagon::PS_storerd_pcr:
1429 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1430 }
1431
1432 return false;
1433 }
1434
1435 MachineBasicBlock::instr_iterator
expandVGatherPseudo(MachineInstr & MI) const1436 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1437 MachineBasicBlock &MBB = *MI.getParent();
1438 const DebugLoc &DL = MI.getDebugLoc();
1439 unsigned Opc = MI.getOpcode();
1440 MachineBasicBlock::iterator First;
1441
1442 switch (Opc) {
1443 case Hexagon::V6_vgathermh_pseudo:
1444 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1445 .add(MI.getOperand(1))
1446 .add(MI.getOperand(2))
1447 .add(MI.getOperand(3));
1448 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1449 .add(MI.getOperand(0))
1450 .addImm(0)
1451 .addReg(Hexagon::VTMP);
1452 MBB.erase(MI);
1453 return First.getInstrIterator();
1454
1455 case Hexagon::V6_vgathermw_pseudo:
1456 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1457 .add(MI.getOperand(1))
1458 .add(MI.getOperand(2))
1459 .add(MI.getOperand(3));
1460 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1461 .add(MI.getOperand(0))
1462 .addImm(0)
1463 .addReg(Hexagon::VTMP);
1464 MBB.erase(MI);
1465 return First.getInstrIterator();
1466
1467 case Hexagon::V6_vgathermhw_pseudo:
1468 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1469 .add(MI.getOperand(1))
1470 .add(MI.getOperand(2))
1471 .add(MI.getOperand(3));
1472 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1473 .add(MI.getOperand(0))
1474 .addImm(0)
1475 .addReg(Hexagon::VTMP);
1476 MBB.erase(MI);
1477 return First.getInstrIterator();
1478
1479 case Hexagon::V6_vgathermhq_pseudo:
1480 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1481 .add(MI.getOperand(1))
1482 .add(MI.getOperand(2))
1483 .add(MI.getOperand(3))
1484 .add(MI.getOperand(4));
1485 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1486 .add(MI.getOperand(0))
1487 .addImm(0)
1488 .addReg(Hexagon::VTMP);
1489 MBB.erase(MI);
1490 return First.getInstrIterator();
1491
1492 case Hexagon::V6_vgathermwq_pseudo:
1493 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1494 .add(MI.getOperand(1))
1495 .add(MI.getOperand(2))
1496 .add(MI.getOperand(3))
1497 .add(MI.getOperand(4));
1498 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1499 .add(MI.getOperand(0))
1500 .addImm(0)
1501 .addReg(Hexagon::VTMP);
1502 MBB.erase(MI);
1503 return First.getInstrIterator();
1504
1505 case Hexagon::V6_vgathermhwq_pseudo:
1506 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1507 .add(MI.getOperand(1))
1508 .add(MI.getOperand(2))
1509 .add(MI.getOperand(3))
1510 .add(MI.getOperand(4));
1511 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1512 .add(MI.getOperand(0))
1513 .addImm(0)
1514 .addReg(Hexagon::VTMP);
1515 MBB.erase(MI);
1516 return First.getInstrIterator();
1517 }
1518
1519 return MI.getIterator();
1520 }
1521
1522 // We indicate that we want to reverse the branch by
1523 // inserting the reversed branching opcode.
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const1524 bool HexagonInstrInfo::reverseBranchCondition(
1525 SmallVectorImpl<MachineOperand> &Cond) const {
1526 if (Cond.empty())
1527 return true;
1528 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1529 unsigned opcode = Cond[0].getImm();
1530 //unsigned temp;
1531 assert(get(opcode).isBranch() && "Should be a branching condition.");
1532 if (isEndLoopN(opcode))
1533 return true;
1534 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1535 Cond[0].setImm(NewOpcode);
1536 return false;
1537 }
1538
insertNoop(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const1539 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1540 MachineBasicBlock::iterator MI) const {
1541 DebugLoc DL;
1542 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1543 }
1544
isPostIncrement(const MachineInstr & MI) const1545 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1546 return getAddrMode(MI) == HexagonII::PostInc;
1547 }
1548
1549 // Returns true if an instruction is predicated irrespective of the predicate
1550 // sense. For example, all of the following will return true.
1551 // if (p0) R1 = add(R2, R3)
1552 // if (!p0) R1 = add(R2, R3)
1553 // if (p0.new) R1 = add(R2, R3)
1554 // if (!p0.new) R1 = add(R2, R3)
1555 // Note: New-value stores are not included here as in the current
1556 // implementation, we don't need to check their predicate sense.
isPredicated(const MachineInstr & MI) const1557 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1558 const uint64_t F = MI.getDesc().TSFlags;
1559 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1560 }
1561
PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Cond) const1562 bool HexagonInstrInfo::PredicateInstruction(
1563 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1564 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1565 isEndLoopN(Cond[0].getImm())) {
1566 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1567 return false;
1568 }
1569 int Opc = MI.getOpcode();
1570 assert (isPredicable(MI) && "Expected predicable instruction");
1571 bool invertJump = predOpcodeHasNot(Cond);
1572
1573 // We have to predicate MI "in place", i.e. after this function returns,
1574 // MI will need to be transformed into a predicated form. To avoid com-
1575 // plicated manipulations with the operands (handling tied operands,
1576 // etc.), build a new temporary instruction, then overwrite MI with it.
1577
1578 MachineBasicBlock &B = *MI.getParent();
1579 DebugLoc DL = MI.getDebugLoc();
1580 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1581 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1582 unsigned NOp = 0, NumOps = MI.getNumOperands();
1583 while (NOp < NumOps) {
1584 MachineOperand &Op = MI.getOperand(NOp);
1585 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1586 break;
1587 T.add(Op);
1588 NOp++;
1589 }
1590
1591 unsigned PredReg, PredRegPos, PredRegFlags;
1592 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1593 (void)GotPredReg;
1594 assert(GotPredReg);
1595 T.addReg(PredReg, PredRegFlags);
1596 while (NOp < NumOps)
1597 T.add(MI.getOperand(NOp++));
1598
1599 MI.setDesc(get(PredOpc));
1600 while (unsigned n = MI.getNumOperands())
1601 MI.RemoveOperand(n-1);
1602 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1603 MI.addOperand(T->getOperand(i));
1604
1605 MachineBasicBlock::instr_iterator TI = T->getIterator();
1606 B.erase(TI);
1607
1608 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1609 MRI.clearKillFlags(PredReg);
1610 return true;
1611 }
1612
SubsumesPredicate(ArrayRef<MachineOperand> Pred1,ArrayRef<MachineOperand> Pred2) const1613 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1614 ArrayRef<MachineOperand> Pred2) const {
1615 // TODO: Fix this
1616 return false;
1617 }
1618
DefinesPredicate(MachineInstr & MI,std::vector<MachineOperand> & Pred) const1619 bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI,
1620 std::vector<MachineOperand> &Pred) const {
1621 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1622
1623 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1624 MachineOperand MO = MI.getOperand(oper);
1625 if (MO.isReg()) {
1626 if (!MO.isDef())
1627 continue;
1628 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1629 if (RC == &Hexagon::PredRegsRegClass) {
1630 Pred.push_back(MO);
1631 return true;
1632 }
1633 continue;
1634 } else if (MO.isRegMask()) {
1635 for (unsigned PR : Hexagon::PredRegsRegClass) {
1636 if (!MI.modifiesRegister(PR, &HRI))
1637 continue;
1638 Pred.push_back(MO);
1639 return true;
1640 }
1641 }
1642 }
1643 return false;
1644 }
1645
isPredicable(const MachineInstr & MI) const1646 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1647 if (!MI.getDesc().isPredicable())
1648 return false;
1649
1650 if (MI.isCall() || isTailCall(MI)) {
1651 if (!Subtarget.usePredicatedCalls())
1652 return false;
1653 }
1654
1655 // HVX loads are not predicable on v60, but are on v62.
1656 if (!Subtarget.hasV62Ops()) {
1657 switch (MI.getOpcode()) {
1658 case Hexagon::V6_vL32b_ai:
1659 case Hexagon::V6_vL32b_pi:
1660 case Hexagon::V6_vL32b_ppu:
1661 case Hexagon::V6_vL32b_cur_ai:
1662 case Hexagon::V6_vL32b_cur_pi:
1663 case Hexagon::V6_vL32b_cur_ppu:
1664 case Hexagon::V6_vL32b_nt_ai:
1665 case Hexagon::V6_vL32b_nt_pi:
1666 case Hexagon::V6_vL32b_nt_ppu:
1667 case Hexagon::V6_vL32b_tmp_ai:
1668 case Hexagon::V6_vL32b_tmp_pi:
1669 case Hexagon::V6_vL32b_tmp_ppu:
1670 case Hexagon::V6_vL32b_nt_cur_ai:
1671 case Hexagon::V6_vL32b_nt_cur_pi:
1672 case Hexagon::V6_vL32b_nt_cur_ppu:
1673 case Hexagon::V6_vL32b_nt_tmp_ai:
1674 case Hexagon::V6_vL32b_nt_tmp_pi:
1675 case Hexagon::V6_vL32b_nt_tmp_ppu:
1676 return false;
1677 }
1678 }
1679 return true;
1680 }
1681
isSchedulingBoundary(const MachineInstr & MI,const MachineBasicBlock * MBB,const MachineFunction & MF) const1682 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1683 const MachineBasicBlock *MBB,
1684 const MachineFunction &MF) const {
1685 // Debug info is never a scheduling boundary. It's necessary to be explicit
1686 // due to the special treatment of IT instructions below, otherwise a
1687 // dbg_value followed by an IT will result in the IT instruction being
1688 // considered a scheduling hazard, which is wrong. It should be the actual
1689 // instruction preceding the dbg_value instruction(s), just like it is
1690 // when debug info is not present.
1691 if (MI.isDebugInstr())
1692 return false;
1693
1694 // Throwing call is a boundary.
1695 if (MI.isCall()) {
1696 // Don't mess around with no return calls.
1697 if (doesNotReturn(MI))
1698 return true;
1699 // If any of the block's successors is a landing pad, this could be a
1700 // throwing call.
1701 for (auto I : MBB->successors())
1702 if (I->isEHPad())
1703 return true;
1704 }
1705
1706 // Terminators and labels can't be scheduled around.
1707 if (MI.getDesc().isTerminator() || MI.isPosition())
1708 return true;
1709
1710 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1711 return true;
1712
1713 return false;
1714 }
1715
1716 /// Measure the specified inline asm to determine an approximation of its
1717 /// length.
1718 /// Comments (which run till the next SeparatorString or newline) do not
1719 /// count as an instruction.
1720 /// Any other non-whitespace text is considered an instruction, with
1721 /// multiple instructions separated by SeparatorString or newlines.
1722 /// Variable-length instructions are not handled here; this function
1723 /// may be overloaded in the target code to do that.
1724 /// Hexagon counts the number of ##'s and adjust for that many
1725 /// constant exenders.
getInlineAsmLength(const char * Str,const MCAsmInfo & MAI,const TargetSubtargetInfo * STI) const1726 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1727 const MCAsmInfo &MAI,
1728 const TargetSubtargetInfo *STI) const {
1729 StringRef AStr(Str);
1730 // Count the number of instructions in the asm.
1731 bool atInsnStart = true;
1732 unsigned Length = 0;
1733 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1734 for (; *Str; ++Str) {
1735 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1736 strlen(MAI.getSeparatorString())) == 0)
1737 atInsnStart = true;
1738 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1739 Length += MaxInstLength;
1740 atInsnStart = false;
1741 }
1742 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1743 MAI.getCommentString().size()) == 0)
1744 atInsnStart = false;
1745 }
1746
1747 // Add to size number of constant extenders seen * 4.
1748 StringRef Occ("##");
1749 Length += AStr.count(Occ)*4;
1750 return Length;
1751 }
1752
1753 ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const1754 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1755 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1756 if (UseDFAHazardRec)
1757 return new HexagonHazardRecognizer(II, this, Subtarget);
1758 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1759 }
1760
1761 /// For a comparison instruction, return the source registers in
1762 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1763 /// compares against in CmpValue. Return true if the comparison instruction
1764 /// can be analyzed.
analyzeCompare(const MachineInstr & MI,unsigned & SrcReg,unsigned & SrcReg2,int & Mask,int & Value) const1765 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1766 unsigned &SrcReg2, int &Mask,
1767 int &Value) const {
1768 unsigned Opc = MI.getOpcode();
1769
1770 // Set mask and the first source register.
1771 switch (Opc) {
1772 case Hexagon::C2_cmpeq:
1773 case Hexagon::C2_cmpeqp:
1774 case Hexagon::C2_cmpgt:
1775 case Hexagon::C2_cmpgtp:
1776 case Hexagon::C2_cmpgtu:
1777 case Hexagon::C2_cmpgtup:
1778 case Hexagon::C4_cmpneq:
1779 case Hexagon::C4_cmplte:
1780 case Hexagon::C4_cmplteu:
1781 case Hexagon::C2_cmpeqi:
1782 case Hexagon::C2_cmpgti:
1783 case Hexagon::C2_cmpgtui:
1784 case Hexagon::C4_cmpneqi:
1785 case Hexagon::C4_cmplteui:
1786 case Hexagon::C4_cmpltei:
1787 SrcReg = MI.getOperand(1).getReg();
1788 Mask = ~0;
1789 break;
1790 case Hexagon::A4_cmpbeq:
1791 case Hexagon::A4_cmpbgt:
1792 case Hexagon::A4_cmpbgtu:
1793 case Hexagon::A4_cmpbeqi:
1794 case Hexagon::A4_cmpbgti:
1795 case Hexagon::A4_cmpbgtui:
1796 SrcReg = MI.getOperand(1).getReg();
1797 Mask = 0xFF;
1798 break;
1799 case Hexagon::A4_cmpheq:
1800 case Hexagon::A4_cmphgt:
1801 case Hexagon::A4_cmphgtu:
1802 case Hexagon::A4_cmpheqi:
1803 case Hexagon::A4_cmphgti:
1804 case Hexagon::A4_cmphgtui:
1805 SrcReg = MI.getOperand(1).getReg();
1806 Mask = 0xFFFF;
1807 break;
1808 }
1809
1810 // Set the value/second source register.
1811 switch (Opc) {
1812 case Hexagon::C2_cmpeq:
1813 case Hexagon::C2_cmpeqp:
1814 case Hexagon::C2_cmpgt:
1815 case Hexagon::C2_cmpgtp:
1816 case Hexagon::C2_cmpgtu:
1817 case Hexagon::C2_cmpgtup:
1818 case Hexagon::A4_cmpbeq:
1819 case Hexagon::A4_cmpbgt:
1820 case Hexagon::A4_cmpbgtu:
1821 case Hexagon::A4_cmpheq:
1822 case Hexagon::A4_cmphgt:
1823 case Hexagon::A4_cmphgtu:
1824 case Hexagon::C4_cmpneq:
1825 case Hexagon::C4_cmplte:
1826 case Hexagon::C4_cmplteu:
1827 SrcReg2 = MI.getOperand(2).getReg();
1828 return true;
1829
1830 case Hexagon::C2_cmpeqi:
1831 case Hexagon::C2_cmpgtui:
1832 case Hexagon::C2_cmpgti:
1833 case Hexagon::C4_cmpneqi:
1834 case Hexagon::C4_cmplteui:
1835 case Hexagon::C4_cmpltei:
1836 case Hexagon::A4_cmpbeqi:
1837 case Hexagon::A4_cmpbgti:
1838 case Hexagon::A4_cmpbgtui:
1839 case Hexagon::A4_cmpheqi:
1840 case Hexagon::A4_cmphgti:
1841 case Hexagon::A4_cmphgtui: {
1842 SrcReg2 = 0;
1843 const MachineOperand &Op2 = MI.getOperand(2);
1844 if (!Op2.isImm())
1845 return false;
1846 Value = MI.getOperand(2).getImm();
1847 return true;
1848 }
1849 }
1850
1851 return false;
1852 }
1853
getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const1854 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1855 const MachineInstr &MI,
1856 unsigned *PredCost) const {
1857 return getInstrTimingClassLatency(ItinData, MI);
1858 }
1859
CreateTargetScheduleState(const TargetSubtargetInfo & STI) const1860 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1861 const TargetSubtargetInfo &STI) const {
1862 const InstrItineraryData *II = STI.getInstrItineraryData();
1863 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1864 }
1865
1866 // Inspired by this pair:
1867 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1868 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1869 // Currently AA considers the addresses in these instructions to be aliasing.
areMemAccessesTriviallyDisjoint(const MachineInstr & MIa,const MachineInstr & MIb) const1870 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1871 const MachineInstr &MIa, const MachineInstr &MIb) const {
1872 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1873 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1874 return false;
1875
1876 // Instructions that are pure loads, not loads and stores like memops are not
1877 // dependent.
1878 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1879 return true;
1880
1881 // Get the base register in MIa.
1882 unsigned BasePosA, OffsetPosA;
1883 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1884 return false;
1885 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1886 Register BaseRegA = BaseA.getReg();
1887 unsigned BaseSubA = BaseA.getSubReg();
1888
1889 // Get the base register in MIb.
1890 unsigned BasePosB, OffsetPosB;
1891 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1892 return false;
1893 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1894 Register BaseRegB = BaseB.getReg();
1895 unsigned BaseSubB = BaseB.getSubReg();
1896
1897 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1898 return false;
1899
1900 // Get the access sizes.
1901 unsigned SizeA = getMemAccessSize(MIa);
1902 unsigned SizeB = getMemAccessSize(MIb);
1903
1904 // Get the offsets. Handle immediates only for now.
1905 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1906 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1907 if (!MIa.getOperand(OffsetPosA).isImm() ||
1908 !MIb.getOperand(OffsetPosB).isImm())
1909 return false;
1910 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1911 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1912
1913 // This is a mem access with the same base register and known offsets from it.
1914 // Reason about it.
1915 if (OffsetA > OffsetB) {
1916 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1917 return SizeB <= OffDiff;
1918 }
1919 if (OffsetA < OffsetB) {
1920 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1921 return SizeA <= OffDiff;
1922 }
1923
1924 return false;
1925 }
1926
1927 /// If the instruction is an increment of a constant value, return the amount.
getIncrementValue(const MachineInstr & MI,int & Value) const1928 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
1929 int &Value) const {
1930 if (isPostIncrement(MI)) {
1931 unsigned BasePos = 0, OffsetPos = 0;
1932 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1933 return false;
1934 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1935 if (OffsetOp.isImm()) {
1936 Value = OffsetOp.getImm();
1937 return true;
1938 }
1939 } else if (MI.getOpcode() == Hexagon::A2_addi) {
1940 const MachineOperand &AddOp = MI.getOperand(2);
1941 if (AddOp.isImm()) {
1942 Value = AddOp.getImm();
1943 return true;
1944 }
1945 }
1946
1947 return false;
1948 }
1949
1950 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const1951 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1952 return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1953 TF & HexagonII::MO_Bitmasks);
1954 }
1955
1956 ArrayRef<std::pair<unsigned, const char*>>
getSerializableDirectMachineOperandTargetFlags() const1957 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1958 using namespace HexagonII;
1959
1960 static const std::pair<unsigned, const char*> Flags[] = {
1961 {MO_PCREL, "hexagon-pcrel"},
1962 {MO_GOT, "hexagon-got"},
1963 {MO_LO16, "hexagon-lo16"},
1964 {MO_HI16, "hexagon-hi16"},
1965 {MO_GPREL, "hexagon-gprel"},
1966 {MO_GDGOT, "hexagon-gdgot"},
1967 {MO_GDPLT, "hexagon-gdplt"},
1968 {MO_IE, "hexagon-ie"},
1969 {MO_IEGOT, "hexagon-iegot"},
1970 {MO_TPREL, "hexagon-tprel"}
1971 };
1972 return makeArrayRef(Flags);
1973 }
1974
1975 ArrayRef<std::pair<unsigned, const char*>>
getSerializableBitmaskMachineOperandTargetFlags() const1976 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1977 using namespace HexagonII;
1978
1979 static const std::pair<unsigned, const char*> Flags[] = {
1980 {HMOTF_ConstExtended, "hexagon-ext"}
1981 };
1982 return makeArrayRef(Flags);
1983 }
1984
createVR(MachineFunction * MF,MVT VT) const1985 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
1986 MachineRegisterInfo &MRI = MF->getRegInfo();
1987 const TargetRegisterClass *TRC;
1988 if (VT == MVT::i1) {
1989 TRC = &Hexagon::PredRegsRegClass;
1990 } else if (VT == MVT::i32 || VT == MVT::f32) {
1991 TRC = &Hexagon::IntRegsRegClass;
1992 } else if (VT == MVT::i64 || VT == MVT::f64) {
1993 TRC = &Hexagon::DoubleRegsRegClass;
1994 } else {
1995 llvm_unreachable("Cannot handle this register class");
1996 }
1997
1998 Register NewReg = MRI.createVirtualRegister(TRC);
1999 return NewReg;
2000 }
2001
isAbsoluteSet(const MachineInstr & MI) const2002 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2003 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2004 }
2005
isAccumulator(const MachineInstr & MI) const2006 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2007 const uint64_t F = MI.getDesc().TSFlags;
2008 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
2009 }
2010
isBaseImmOffset(const MachineInstr & MI) const2011 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2012 return getAddrMode(MI) == HexagonII::BaseImmOffset;
2013 }
2014
isComplex(const MachineInstr & MI) const2015 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2016 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2017 !MI.getDesc().mayStore() &&
2018 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2019 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2020 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2021 }
2022
2023 // Return true if the instruction is a compund branch instruction.
isCompoundBranchInstr(const MachineInstr & MI) const2024 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2025 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2026 }
2027
2028 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2029 // isFPImm and later getFPImm as well.
isConstExtended(const MachineInstr & MI) const2030 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2031 const uint64_t F = MI.getDesc().TSFlags;
2032 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2033 if (isExtended) // Instruction must be extended.
2034 return true;
2035
2036 unsigned isExtendable =
2037 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
2038 if (!isExtendable)
2039 return false;
2040
2041 if (MI.isCall())
2042 return false;
2043
2044 short ExtOpNum = getCExtOpNum(MI);
2045 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2046 // Use MO operand flags to determine if MO
2047 // has the HMOTF_ConstExtended flag set.
2048 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2049 return true;
2050 // If this is a Machine BB address we are talking about, and it is
2051 // not marked as extended, say so.
2052 if (MO.isMBB())
2053 return false;
2054
2055 // We could be using an instruction with an extendable immediate and shoehorn
2056 // a global address into it. If it is a global address it will be constant
2057 // extended. We do this for COMBINE.
2058 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2059 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2060 return true;
2061
2062 // If the extendable operand is not 'Immediate' type, the instruction should
2063 // have 'isExtended' flag set.
2064 assert(MO.isImm() && "Extendable operand must be Immediate type");
2065
2066 int MinValue = getMinValue(MI);
2067 int MaxValue = getMaxValue(MI);
2068 int ImmValue = MO.getImm();
2069
2070 return (ImmValue < MinValue || ImmValue > MaxValue);
2071 }
2072
isDeallocRet(const MachineInstr & MI) const2073 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2074 switch (MI.getOpcode()) {
2075 case Hexagon::L4_return:
2076 case Hexagon::L4_return_t:
2077 case Hexagon::L4_return_f:
2078 case Hexagon::L4_return_tnew_pnt:
2079 case Hexagon::L4_return_fnew_pnt:
2080 case Hexagon::L4_return_tnew_pt:
2081 case Hexagon::L4_return_fnew_pt:
2082 return true;
2083 }
2084 return false;
2085 }
2086
2087 // Return true when ConsMI uses a register defined by ProdMI.
isDependent(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const2088 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2089 const MachineInstr &ConsMI) const {
2090 if (!ProdMI.getDesc().getNumDefs())
2091 return false;
2092 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2093
2094 SmallVector<unsigned, 4> DefsA;
2095 SmallVector<unsigned, 4> DefsB;
2096 SmallVector<unsigned, 8> UsesA;
2097 SmallVector<unsigned, 8> UsesB;
2098
2099 parseOperands(ProdMI, DefsA, UsesA);
2100 parseOperands(ConsMI, DefsB, UsesB);
2101
2102 for (auto &RegA : DefsA)
2103 for (auto &RegB : UsesB) {
2104 // True data dependency.
2105 if (RegA == RegB)
2106 return true;
2107
2108 if (Register::isPhysicalRegister(RegA))
2109 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2110 if (RegB == *SubRegs)
2111 return true;
2112
2113 if (Register::isPhysicalRegister(RegB))
2114 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2115 if (RegA == *SubRegs)
2116 return true;
2117 }
2118
2119 return false;
2120 }
2121
2122 // Returns true if the instruction is alread a .cur.
isDotCurInst(const MachineInstr & MI) const2123 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2124 switch (MI.getOpcode()) {
2125 case Hexagon::V6_vL32b_cur_pi:
2126 case Hexagon::V6_vL32b_cur_ai:
2127 return true;
2128 }
2129 return false;
2130 }
2131
2132 // Returns true, if any one of the operands is a dot new
2133 // insn, whether it is predicated dot new or register dot new.
isDotNewInst(const MachineInstr & MI) const2134 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2135 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2136 return true;
2137
2138 return false;
2139 }
2140
2141 /// Symmetrical. See if these two instructions are fit for duplex pair.
isDuplexPair(const MachineInstr & MIa,const MachineInstr & MIb) const2142 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2143 const MachineInstr &MIb) const {
2144 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
2145 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
2146 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2147 }
2148
isEarlySourceInstr(const MachineInstr & MI) const2149 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
2150 if (MI.mayLoadOrStore() || MI.isCompare())
2151 return true;
2152
2153 // Multiply
2154 unsigned SchedClass = MI.getDesc().getSchedClass();
2155 return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2156 }
2157
isEndLoopN(unsigned Opcode) const2158 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2159 return (Opcode == Hexagon::ENDLOOP0 ||
2160 Opcode == Hexagon::ENDLOOP1);
2161 }
2162
isExpr(unsigned OpType) const2163 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2164 switch(OpType) {
2165 case MachineOperand::MO_MachineBasicBlock:
2166 case MachineOperand::MO_GlobalAddress:
2167 case MachineOperand::MO_ExternalSymbol:
2168 case MachineOperand::MO_JumpTableIndex:
2169 case MachineOperand::MO_ConstantPoolIndex:
2170 case MachineOperand::MO_BlockAddress:
2171 return true;
2172 default:
2173 return false;
2174 }
2175 }
2176
isExtendable(const MachineInstr & MI) const2177 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2178 const MCInstrDesc &MID = MI.getDesc();
2179 const uint64_t F = MID.TSFlags;
2180 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2181 return true;
2182
2183 // TODO: This is largely obsolete now. Will need to be removed
2184 // in consecutive patches.
2185 switch (MI.getOpcode()) {
2186 // PS_fi and PS_fia remain special cases.
2187 case Hexagon::PS_fi:
2188 case Hexagon::PS_fia:
2189 return true;
2190 default:
2191 return false;
2192 }
2193 return false;
2194 }
2195
2196 // This returns true in two cases:
2197 // - The OP code itself indicates that this is an extended instruction.
2198 // - One of MOs has been marked with HMOTF_ConstExtended flag.
isExtended(const MachineInstr & MI) const2199 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2200 // First check if this is permanently extended op code.
2201 const uint64_t F = MI.getDesc().TSFlags;
2202 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2203 return true;
2204 // Use MO operand flags to determine if one of MI's operands
2205 // has HMOTF_ConstExtended flag set.
2206 for (const MachineOperand &MO : MI.operands())
2207 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2208 return true;
2209 return false;
2210 }
2211
isFloat(const MachineInstr & MI) const2212 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2213 unsigned Opcode = MI.getOpcode();
2214 const uint64_t F = get(Opcode).TSFlags;
2215 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2216 }
2217
2218 // No V60 HVX VMEM with A_INDIRECT.
isHVXMemWithAIndirect(const MachineInstr & I,const MachineInstr & J) const2219 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2220 const MachineInstr &J) const {
2221 if (!isHVXVec(I))
2222 return false;
2223 if (!I.mayLoad() && !I.mayStore())
2224 return false;
2225 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2226 }
2227
isIndirectCall(const MachineInstr & MI) const2228 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2229 switch (MI.getOpcode()) {
2230 case Hexagon::J2_callr:
2231 case Hexagon::J2_callrf:
2232 case Hexagon::J2_callrt:
2233 case Hexagon::PS_call_nr:
2234 return true;
2235 }
2236 return false;
2237 }
2238
isIndirectL4Return(const MachineInstr & MI) const2239 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2240 switch (MI.getOpcode()) {
2241 case Hexagon::L4_return:
2242 case Hexagon::L4_return_t:
2243 case Hexagon::L4_return_f:
2244 case Hexagon::L4_return_fnew_pnt:
2245 case Hexagon::L4_return_fnew_pt:
2246 case Hexagon::L4_return_tnew_pnt:
2247 case Hexagon::L4_return_tnew_pt:
2248 return true;
2249 }
2250 return false;
2251 }
2252
isJumpR(const MachineInstr & MI) const2253 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2254 switch (MI.getOpcode()) {
2255 case Hexagon::J2_jumpr:
2256 case Hexagon::J2_jumprt:
2257 case Hexagon::J2_jumprf:
2258 case Hexagon::J2_jumprtnewpt:
2259 case Hexagon::J2_jumprfnewpt:
2260 case Hexagon::J2_jumprtnew:
2261 case Hexagon::J2_jumprfnew:
2262 return true;
2263 }
2264 return false;
2265 }
2266
2267 // Return true if a given MI can accommodate given offset.
2268 // Use abs estimate as oppose to the exact number.
2269 // TODO: This will need to be changed to use MC level
2270 // definition of instruction extendable field size.
isJumpWithinBranchRange(const MachineInstr & MI,unsigned offset) const2271 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2272 unsigned offset) const {
2273 // This selection of jump instructions matches to that what
2274 // analyzeBranch can parse, plus NVJ.
2275 if (isNewValueJump(MI)) // r9:2
2276 return isInt<11>(offset);
2277
2278 switch (MI.getOpcode()) {
2279 // Still missing Jump to address condition on register value.
2280 default:
2281 return false;
2282 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2283 case Hexagon::J2_call:
2284 case Hexagon::PS_call_nr:
2285 return isInt<24>(offset);
2286 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2287 case Hexagon::J2_jumpf:
2288 case Hexagon::J2_jumptnew:
2289 case Hexagon::J2_jumptnewpt:
2290 case Hexagon::J2_jumpfnew:
2291 case Hexagon::J2_jumpfnewpt:
2292 case Hexagon::J2_callt:
2293 case Hexagon::J2_callf:
2294 return isInt<17>(offset);
2295 case Hexagon::J2_loop0i:
2296 case Hexagon::J2_loop0iext:
2297 case Hexagon::J2_loop0r:
2298 case Hexagon::J2_loop0rext:
2299 case Hexagon::J2_loop1i:
2300 case Hexagon::J2_loop1iext:
2301 case Hexagon::J2_loop1r:
2302 case Hexagon::J2_loop1rext:
2303 return isInt<9>(offset);
2304 // TODO: Add all the compound branches here. Can we do this in Relation model?
2305 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2306 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2307 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2308 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2309 return isInt<11>(offset);
2310 }
2311 }
2312
isLateInstrFeedsEarlyInstr(const MachineInstr & LRMI,const MachineInstr & ESMI) const2313 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
2314 const MachineInstr &ESMI) const {
2315 bool isLate = isLateResultInstr(LRMI);
2316 bool isEarly = isEarlySourceInstr(ESMI);
2317
2318 LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2319 LLVM_DEBUG(LRMI.dump());
2320 LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2321 LLVM_DEBUG(ESMI.dump());
2322
2323 if (isLate && isEarly) {
2324 LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2325 return true;
2326 }
2327
2328 return false;
2329 }
2330
isLateResultInstr(const MachineInstr & MI) const2331 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
2332 switch (MI.getOpcode()) {
2333 case TargetOpcode::EXTRACT_SUBREG:
2334 case TargetOpcode::INSERT_SUBREG:
2335 case TargetOpcode::SUBREG_TO_REG:
2336 case TargetOpcode::REG_SEQUENCE:
2337 case TargetOpcode::IMPLICIT_DEF:
2338 case TargetOpcode::COPY:
2339 case TargetOpcode::INLINEASM:
2340 case TargetOpcode::PHI:
2341 return false;
2342 default:
2343 break;
2344 }
2345
2346 unsigned SchedClass = MI.getDesc().getSchedClass();
2347 return !is_TC1(SchedClass);
2348 }
2349
isLateSourceInstr(const MachineInstr & MI) const2350 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2351 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2352 // resource, but all operands can be received late like an ALU instruction.
2353 return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2354 }
2355
isLoopN(const MachineInstr & MI) const2356 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2357 unsigned Opcode = MI.getOpcode();
2358 return Opcode == Hexagon::J2_loop0i ||
2359 Opcode == Hexagon::J2_loop0r ||
2360 Opcode == Hexagon::J2_loop0iext ||
2361 Opcode == Hexagon::J2_loop0rext ||
2362 Opcode == Hexagon::J2_loop1i ||
2363 Opcode == Hexagon::J2_loop1r ||
2364 Opcode == Hexagon::J2_loop1iext ||
2365 Opcode == Hexagon::J2_loop1rext;
2366 }
2367
isMemOp(const MachineInstr & MI) const2368 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2369 switch (MI.getOpcode()) {
2370 default: return false;
2371 case Hexagon::L4_iadd_memopw_io:
2372 case Hexagon::L4_isub_memopw_io:
2373 case Hexagon::L4_add_memopw_io:
2374 case Hexagon::L4_sub_memopw_io:
2375 case Hexagon::L4_and_memopw_io:
2376 case Hexagon::L4_or_memopw_io:
2377 case Hexagon::L4_iadd_memoph_io:
2378 case Hexagon::L4_isub_memoph_io:
2379 case Hexagon::L4_add_memoph_io:
2380 case Hexagon::L4_sub_memoph_io:
2381 case Hexagon::L4_and_memoph_io:
2382 case Hexagon::L4_or_memoph_io:
2383 case Hexagon::L4_iadd_memopb_io:
2384 case Hexagon::L4_isub_memopb_io:
2385 case Hexagon::L4_add_memopb_io:
2386 case Hexagon::L4_sub_memopb_io:
2387 case Hexagon::L4_and_memopb_io:
2388 case Hexagon::L4_or_memopb_io:
2389 case Hexagon::L4_ior_memopb_io:
2390 case Hexagon::L4_ior_memoph_io:
2391 case Hexagon::L4_ior_memopw_io:
2392 case Hexagon::L4_iand_memopb_io:
2393 case Hexagon::L4_iand_memoph_io:
2394 case Hexagon::L4_iand_memopw_io:
2395 return true;
2396 }
2397 return false;
2398 }
2399
isNewValue(const MachineInstr & MI) const2400 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2401 const uint64_t F = MI.getDesc().TSFlags;
2402 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2403 }
2404
isNewValue(unsigned Opcode) const2405 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2406 const uint64_t F = get(Opcode).TSFlags;
2407 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2408 }
2409
isNewValueInst(const MachineInstr & MI) const2410 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2411 return isNewValueJump(MI) || isNewValueStore(MI);
2412 }
2413
isNewValueJump(const MachineInstr & MI) const2414 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2415 return isNewValue(MI) && MI.isBranch();
2416 }
2417
isNewValueJump(unsigned Opcode) const2418 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2419 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2420 }
2421
isNewValueStore(const MachineInstr & MI) const2422 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2423 const uint64_t F = MI.getDesc().TSFlags;
2424 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2425 }
2426
isNewValueStore(unsigned Opcode) const2427 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2428 const uint64_t F = get(Opcode).TSFlags;
2429 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2430 }
2431
2432 // Returns true if a particular operand is extendable for an instruction.
isOperandExtended(const MachineInstr & MI,unsigned OperandNum) const2433 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2434 unsigned OperandNum) const {
2435 const uint64_t F = MI.getDesc().TSFlags;
2436 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2437 == OperandNum;
2438 }
2439
isPredicatedNew(const MachineInstr & MI) const2440 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2441 const uint64_t F = MI.getDesc().TSFlags;
2442 assert(isPredicated(MI));
2443 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2444 }
2445
isPredicatedNew(unsigned Opcode) const2446 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2447 const uint64_t F = get(Opcode).TSFlags;
2448 assert(isPredicated(Opcode));
2449 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2450 }
2451
isPredicatedTrue(const MachineInstr & MI) const2452 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2453 const uint64_t F = MI.getDesc().TSFlags;
2454 return !((F >> HexagonII::PredicatedFalsePos) &
2455 HexagonII::PredicatedFalseMask);
2456 }
2457
isPredicatedTrue(unsigned Opcode) const2458 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2459 const uint64_t F = get(Opcode).TSFlags;
2460 // Make sure that the instruction is predicated.
2461 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2462 return !((F >> HexagonII::PredicatedFalsePos) &
2463 HexagonII::PredicatedFalseMask);
2464 }
2465
isPredicated(unsigned Opcode) const2466 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2467 const uint64_t F = get(Opcode).TSFlags;
2468 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2469 }
2470
isPredicateLate(unsigned Opcode) const2471 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2472 const uint64_t F = get(Opcode).TSFlags;
2473 return (F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2474 }
2475
isPredictedTaken(unsigned Opcode) const2476 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2477 const uint64_t F = get(Opcode).TSFlags;
2478 assert(get(Opcode).isBranch() &&
2479 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2480 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2481 }
2482
isSaveCalleeSavedRegsCall(const MachineInstr & MI) const2483 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2484 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2485 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2486 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2487 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2488 }
2489
isSignExtendingLoad(const MachineInstr & MI) const2490 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2491 switch (MI.getOpcode()) {
2492 // Byte
2493 case Hexagon::L2_loadrb_io:
2494 case Hexagon::L4_loadrb_ur:
2495 case Hexagon::L4_loadrb_ap:
2496 case Hexagon::L2_loadrb_pr:
2497 case Hexagon::L2_loadrb_pbr:
2498 case Hexagon::L2_loadrb_pi:
2499 case Hexagon::L2_loadrb_pci:
2500 case Hexagon::L2_loadrb_pcr:
2501 case Hexagon::L2_loadbsw2_io:
2502 case Hexagon::L4_loadbsw2_ur:
2503 case Hexagon::L4_loadbsw2_ap:
2504 case Hexagon::L2_loadbsw2_pr:
2505 case Hexagon::L2_loadbsw2_pbr:
2506 case Hexagon::L2_loadbsw2_pi:
2507 case Hexagon::L2_loadbsw2_pci:
2508 case Hexagon::L2_loadbsw2_pcr:
2509 case Hexagon::L2_loadbsw4_io:
2510 case Hexagon::L4_loadbsw4_ur:
2511 case Hexagon::L4_loadbsw4_ap:
2512 case Hexagon::L2_loadbsw4_pr:
2513 case Hexagon::L2_loadbsw4_pbr:
2514 case Hexagon::L2_loadbsw4_pi:
2515 case Hexagon::L2_loadbsw4_pci:
2516 case Hexagon::L2_loadbsw4_pcr:
2517 case Hexagon::L4_loadrb_rr:
2518 case Hexagon::L2_ploadrbt_io:
2519 case Hexagon::L2_ploadrbt_pi:
2520 case Hexagon::L2_ploadrbf_io:
2521 case Hexagon::L2_ploadrbf_pi:
2522 case Hexagon::L2_ploadrbtnew_io:
2523 case Hexagon::L2_ploadrbfnew_io:
2524 case Hexagon::L4_ploadrbt_rr:
2525 case Hexagon::L4_ploadrbf_rr:
2526 case Hexagon::L4_ploadrbtnew_rr:
2527 case Hexagon::L4_ploadrbfnew_rr:
2528 case Hexagon::L2_ploadrbtnew_pi:
2529 case Hexagon::L2_ploadrbfnew_pi:
2530 case Hexagon::L4_ploadrbt_abs:
2531 case Hexagon::L4_ploadrbf_abs:
2532 case Hexagon::L4_ploadrbtnew_abs:
2533 case Hexagon::L4_ploadrbfnew_abs:
2534 case Hexagon::L2_loadrbgp:
2535 // Half
2536 case Hexagon::L2_loadrh_io:
2537 case Hexagon::L4_loadrh_ur:
2538 case Hexagon::L4_loadrh_ap:
2539 case Hexagon::L2_loadrh_pr:
2540 case Hexagon::L2_loadrh_pbr:
2541 case Hexagon::L2_loadrh_pi:
2542 case Hexagon::L2_loadrh_pci:
2543 case Hexagon::L2_loadrh_pcr:
2544 case Hexagon::L4_loadrh_rr:
2545 case Hexagon::L2_ploadrht_io:
2546 case Hexagon::L2_ploadrht_pi:
2547 case Hexagon::L2_ploadrhf_io:
2548 case Hexagon::L2_ploadrhf_pi:
2549 case Hexagon::L2_ploadrhtnew_io:
2550 case Hexagon::L2_ploadrhfnew_io:
2551 case Hexagon::L4_ploadrht_rr:
2552 case Hexagon::L4_ploadrhf_rr:
2553 case Hexagon::L4_ploadrhtnew_rr:
2554 case Hexagon::L4_ploadrhfnew_rr:
2555 case Hexagon::L2_ploadrhtnew_pi:
2556 case Hexagon::L2_ploadrhfnew_pi:
2557 case Hexagon::L4_ploadrht_abs:
2558 case Hexagon::L4_ploadrhf_abs:
2559 case Hexagon::L4_ploadrhtnew_abs:
2560 case Hexagon::L4_ploadrhfnew_abs:
2561 case Hexagon::L2_loadrhgp:
2562 return true;
2563 default:
2564 return false;
2565 }
2566 }
2567
isSolo(const MachineInstr & MI) const2568 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2569 const uint64_t F = MI.getDesc().TSFlags;
2570 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2571 }
2572
isSpillPredRegOp(const MachineInstr & MI) const2573 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2574 switch (MI.getOpcode()) {
2575 case Hexagon::STriw_pred:
2576 case Hexagon::LDriw_pred:
2577 return true;
2578 default:
2579 return false;
2580 }
2581 }
2582
isTailCall(const MachineInstr & MI) const2583 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2584 if (!MI.isBranch())
2585 return false;
2586
2587 for (auto &Op : MI.operands())
2588 if (Op.isGlobal() || Op.isSymbol())
2589 return true;
2590 return false;
2591 }
2592
2593 // Returns true when SU has a timing class TC1.
isTC1(const MachineInstr & MI) const2594 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2595 unsigned SchedClass = MI.getDesc().getSchedClass();
2596 return is_TC1(SchedClass);
2597 }
2598
isTC2(const MachineInstr & MI) const2599 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2600 unsigned SchedClass = MI.getDesc().getSchedClass();
2601 return is_TC2(SchedClass);
2602 }
2603
isTC2Early(const MachineInstr & MI) const2604 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2605 unsigned SchedClass = MI.getDesc().getSchedClass();
2606 return is_TC2early(SchedClass);
2607 }
2608
isTC4x(const MachineInstr & MI) const2609 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2610 unsigned SchedClass = MI.getDesc().getSchedClass();
2611 return is_TC4x(SchedClass);
2612 }
2613
2614 // Schedule this ASAP.
isToBeScheduledASAP(const MachineInstr & MI1,const MachineInstr & MI2) const2615 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2616 const MachineInstr &MI2) const {
2617 if (mayBeCurLoad(MI1)) {
2618 // if (result of SU is used in Next) return true;
2619 Register DstReg = MI1.getOperand(0).getReg();
2620 int N = MI2.getNumOperands();
2621 for (int I = 0; I < N; I++)
2622 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2623 return true;
2624 }
2625 if (mayBeNewStore(MI2))
2626 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2627 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2628 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2629 return true;
2630 return false;
2631 }
2632
isHVXVec(const MachineInstr & MI) const2633 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2634 const uint64_t V = getType(MI);
2635 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2636 }
2637
2638 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
isValidAutoIncImm(const EVT VT,int Offset) const2639 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2640 int Size = VT.getSizeInBits() / 8;
2641 if (Offset % Size != 0)
2642 return false;
2643 int Count = Offset / Size;
2644
2645 switch (VT.getSimpleVT().SimpleTy) {
2646 // For scalars the auto-inc is s4
2647 case MVT::i8:
2648 case MVT::i16:
2649 case MVT::i32:
2650 case MVT::i64:
2651 case MVT::f32:
2652 case MVT::f64:
2653 case MVT::v2i16:
2654 case MVT::v2i32:
2655 case MVT::v4i8:
2656 case MVT::v4i16:
2657 case MVT::v8i8:
2658 return isInt<4>(Count);
2659 // For HVX vectors the auto-inc is s3
2660 case MVT::v64i8:
2661 case MVT::v32i16:
2662 case MVT::v16i32:
2663 case MVT::v8i64:
2664 case MVT::v128i8:
2665 case MVT::v64i16:
2666 case MVT::v32i32:
2667 case MVT::v16i64:
2668 return isInt<3>(Count);
2669 default:
2670 break;
2671 }
2672
2673 llvm_unreachable("Not an valid type!");
2674 }
2675
isValidOffset(unsigned Opcode,int Offset,const TargetRegisterInfo * TRI,bool Extend) const2676 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2677 const TargetRegisterInfo *TRI, bool Extend) const {
2678 // This function is to check whether the "Offset" is in the correct range of
2679 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2680 // inserted to calculate the final address. Due to this reason, the function
2681 // assumes that the "Offset" has correct alignment.
2682 // We used to assert if the offset was not properly aligned, however,
2683 // there are cases where a misaligned pointer recast can cause this
2684 // problem, and we need to allow for it. The front end warns of such
2685 // misaligns with respect to load size.
2686 switch (Opcode) {
2687 case Hexagon::PS_vstorerq_ai:
2688 case Hexagon::PS_vstorerv_ai:
2689 case Hexagon::PS_vstorerw_ai:
2690 case Hexagon::PS_vstorerw_nt_ai:
2691 case Hexagon::PS_vloadrq_ai:
2692 case Hexagon::PS_vloadrv_ai:
2693 case Hexagon::PS_vloadrw_ai:
2694 case Hexagon::PS_vloadrw_nt_ai:
2695 case Hexagon::V6_vL32b_ai:
2696 case Hexagon::V6_vS32b_ai:
2697 case Hexagon::V6_vL32b_nt_ai:
2698 case Hexagon::V6_vS32b_nt_ai:
2699 case Hexagon::V6_vL32Ub_ai:
2700 case Hexagon::V6_vS32Ub_ai: {
2701 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2702 assert(isPowerOf2_32(VectorSize));
2703 if (Offset & (VectorSize-1))
2704 return false;
2705 return isInt<4>(Offset >> Log2_32(VectorSize));
2706 }
2707
2708 case Hexagon::J2_loop0i:
2709 case Hexagon::J2_loop1i:
2710 return isUInt<10>(Offset);
2711
2712 case Hexagon::S4_storeirb_io:
2713 case Hexagon::S4_storeirbt_io:
2714 case Hexagon::S4_storeirbf_io:
2715 return isUInt<6>(Offset);
2716
2717 case Hexagon::S4_storeirh_io:
2718 case Hexagon::S4_storeirht_io:
2719 case Hexagon::S4_storeirhf_io:
2720 return isShiftedUInt<6,1>(Offset);
2721
2722 case Hexagon::S4_storeiri_io:
2723 case Hexagon::S4_storeirit_io:
2724 case Hexagon::S4_storeirif_io:
2725 return isShiftedUInt<6,2>(Offset);
2726 }
2727
2728 if (Extend)
2729 return true;
2730
2731 switch (Opcode) {
2732 case Hexagon::L2_loadri_io:
2733 case Hexagon::S2_storeri_io:
2734 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2735 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2736
2737 case Hexagon::L2_loadrd_io:
2738 case Hexagon::S2_storerd_io:
2739 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2740 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2741
2742 case Hexagon::L2_loadrh_io:
2743 case Hexagon::L2_loadruh_io:
2744 case Hexagon::S2_storerh_io:
2745 case Hexagon::S2_storerf_io:
2746 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2747 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2748
2749 case Hexagon::L2_loadrb_io:
2750 case Hexagon::L2_loadrub_io:
2751 case Hexagon::S2_storerb_io:
2752 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2753 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2754
2755 case Hexagon::A2_addi:
2756 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2757 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2758
2759 case Hexagon::L4_iadd_memopw_io:
2760 case Hexagon::L4_isub_memopw_io:
2761 case Hexagon::L4_add_memopw_io:
2762 case Hexagon::L4_sub_memopw_io:
2763 case Hexagon::L4_and_memopw_io:
2764 case Hexagon::L4_or_memopw_io:
2765 return (0 <= Offset && Offset <= 255);
2766
2767 case Hexagon::L4_iadd_memoph_io:
2768 case Hexagon::L4_isub_memoph_io:
2769 case Hexagon::L4_add_memoph_io:
2770 case Hexagon::L4_sub_memoph_io:
2771 case Hexagon::L4_and_memoph_io:
2772 case Hexagon::L4_or_memoph_io:
2773 return (0 <= Offset && Offset <= 127);
2774
2775 case Hexagon::L4_iadd_memopb_io:
2776 case Hexagon::L4_isub_memopb_io:
2777 case Hexagon::L4_add_memopb_io:
2778 case Hexagon::L4_sub_memopb_io:
2779 case Hexagon::L4_and_memopb_io:
2780 case Hexagon::L4_or_memopb_io:
2781 return (0 <= Offset && Offset <= 63);
2782
2783 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2784 // any size. Later pass knows how to handle it.
2785 case Hexagon::STriw_pred:
2786 case Hexagon::LDriw_pred:
2787 case Hexagon::STriw_ctr:
2788 case Hexagon::LDriw_ctr:
2789 return true;
2790
2791 case Hexagon::PS_fi:
2792 case Hexagon::PS_fia:
2793 case Hexagon::INLINEASM:
2794 return true;
2795
2796 case Hexagon::L2_ploadrbt_io:
2797 case Hexagon::L2_ploadrbf_io:
2798 case Hexagon::L2_ploadrubt_io:
2799 case Hexagon::L2_ploadrubf_io:
2800 case Hexagon::S2_pstorerbt_io:
2801 case Hexagon::S2_pstorerbf_io:
2802 return isUInt<6>(Offset);
2803
2804 case Hexagon::L2_ploadrht_io:
2805 case Hexagon::L2_ploadrhf_io:
2806 case Hexagon::L2_ploadruht_io:
2807 case Hexagon::L2_ploadruhf_io:
2808 case Hexagon::S2_pstorerht_io:
2809 case Hexagon::S2_pstorerhf_io:
2810 return isShiftedUInt<6,1>(Offset);
2811
2812 case Hexagon::L2_ploadrit_io:
2813 case Hexagon::L2_ploadrif_io:
2814 case Hexagon::S2_pstorerit_io:
2815 case Hexagon::S2_pstorerif_io:
2816 return isShiftedUInt<6,2>(Offset);
2817
2818 case Hexagon::L2_ploadrdt_io:
2819 case Hexagon::L2_ploadrdf_io:
2820 case Hexagon::S2_pstorerdt_io:
2821 case Hexagon::S2_pstorerdf_io:
2822 return isShiftedUInt<6,3>(Offset);
2823 } // switch
2824
2825 llvm_unreachable("No offset range is defined for this opcode. "
2826 "Please define it in the above switch statement!");
2827 }
2828
isVecAcc(const MachineInstr & MI) const2829 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2830 return isHVXVec(MI) && isAccumulator(MI);
2831 }
2832
isVecALU(const MachineInstr & MI) const2833 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2834 const uint64_t F = get(MI.getOpcode()).TSFlags;
2835 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2836 return
2837 V == HexagonII::TypeCVI_VA ||
2838 V == HexagonII::TypeCVI_VA_DV;
2839 }
2840
isVecUsableNextPacket(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const2841 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2842 const MachineInstr &ConsMI) const {
2843 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2844 return true;
2845
2846 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2847 return true;
2848
2849 if (mayBeNewStore(ConsMI))
2850 return true;
2851
2852 return false;
2853 }
2854
isZeroExtendingLoad(const MachineInstr & MI) const2855 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2856 switch (MI.getOpcode()) {
2857 // Byte
2858 case Hexagon::L2_loadrub_io:
2859 case Hexagon::L4_loadrub_ur:
2860 case Hexagon::L4_loadrub_ap:
2861 case Hexagon::L2_loadrub_pr:
2862 case Hexagon::L2_loadrub_pbr:
2863 case Hexagon::L2_loadrub_pi:
2864 case Hexagon::L2_loadrub_pci:
2865 case Hexagon::L2_loadrub_pcr:
2866 case Hexagon::L2_loadbzw2_io:
2867 case Hexagon::L4_loadbzw2_ur:
2868 case Hexagon::L4_loadbzw2_ap:
2869 case Hexagon::L2_loadbzw2_pr:
2870 case Hexagon::L2_loadbzw2_pbr:
2871 case Hexagon::L2_loadbzw2_pi:
2872 case Hexagon::L2_loadbzw2_pci:
2873 case Hexagon::L2_loadbzw2_pcr:
2874 case Hexagon::L2_loadbzw4_io:
2875 case Hexagon::L4_loadbzw4_ur:
2876 case Hexagon::L4_loadbzw4_ap:
2877 case Hexagon::L2_loadbzw4_pr:
2878 case Hexagon::L2_loadbzw4_pbr:
2879 case Hexagon::L2_loadbzw4_pi:
2880 case Hexagon::L2_loadbzw4_pci:
2881 case Hexagon::L2_loadbzw4_pcr:
2882 case Hexagon::L4_loadrub_rr:
2883 case Hexagon::L2_ploadrubt_io:
2884 case Hexagon::L2_ploadrubt_pi:
2885 case Hexagon::L2_ploadrubf_io:
2886 case Hexagon::L2_ploadrubf_pi:
2887 case Hexagon::L2_ploadrubtnew_io:
2888 case Hexagon::L2_ploadrubfnew_io:
2889 case Hexagon::L4_ploadrubt_rr:
2890 case Hexagon::L4_ploadrubf_rr:
2891 case Hexagon::L4_ploadrubtnew_rr:
2892 case Hexagon::L4_ploadrubfnew_rr:
2893 case Hexagon::L2_ploadrubtnew_pi:
2894 case Hexagon::L2_ploadrubfnew_pi:
2895 case Hexagon::L4_ploadrubt_abs:
2896 case Hexagon::L4_ploadrubf_abs:
2897 case Hexagon::L4_ploadrubtnew_abs:
2898 case Hexagon::L4_ploadrubfnew_abs:
2899 case Hexagon::L2_loadrubgp:
2900 // Half
2901 case Hexagon::L2_loadruh_io:
2902 case Hexagon::L4_loadruh_ur:
2903 case Hexagon::L4_loadruh_ap:
2904 case Hexagon::L2_loadruh_pr:
2905 case Hexagon::L2_loadruh_pbr:
2906 case Hexagon::L2_loadruh_pi:
2907 case Hexagon::L2_loadruh_pci:
2908 case Hexagon::L2_loadruh_pcr:
2909 case Hexagon::L4_loadruh_rr:
2910 case Hexagon::L2_ploadruht_io:
2911 case Hexagon::L2_ploadruht_pi:
2912 case Hexagon::L2_ploadruhf_io:
2913 case Hexagon::L2_ploadruhf_pi:
2914 case Hexagon::L2_ploadruhtnew_io:
2915 case Hexagon::L2_ploadruhfnew_io:
2916 case Hexagon::L4_ploadruht_rr:
2917 case Hexagon::L4_ploadruhf_rr:
2918 case Hexagon::L4_ploadruhtnew_rr:
2919 case Hexagon::L4_ploadruhfnew_rr:
2920 case Hexagon::L2_ploadruhtnew_pi:
2921 case Hexagon::L2_ploadruhfnew_pi:
2922 case Hexagon::L4_ploadruht_abs:
2923 case Hexagon::L4_ploadruhf_abs:
2924 case Hexagon::L4_ploadruhtnew_abs:
2925 case Hexagon::L4_ploadruhfnew_abs:
2926 case Hexagon::L2_loadruhgp:
2927 return true;
2928 default:
2929 return false;
2930 }
2931 }
2932
2933 // Add latency to instruction.
addLatencyToSchedule(const MachineInstr & MI1,const MachineInstr & MI2) const2934 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
2935 const MachineInstr &MI2) const {
2936 if (isHVXVec(MI1) && isHVXVec(MI2))
2937 if (!isVecUsableNextPacket(MI1, MI2))
2938 return true;
2939 return false;
2940 }
2941
2942 /// Get the base register and byte offset of a load/store instr.
getMemOperandWithOffset(const MachineInstr & LdSt,const MachineOperand * & BaseOp,int64_t & Offset,const TargetRegisterInfo * TRI) const2943 bool HexagonInstrInfo::getMemOperandWithOffset(
2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2945 const TargetRegisterInfo *TRI) const {
2946 unsigned AccessSize = 0;
2947 BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2948 return BaseOp != nullptr && BaseOp->isReg();
2949 }
2950
2951 /// Can these instructions execute at the same time in a bundle.
canExecuteInBundle(const MachineInstr & First,const MachineInstr & Second) const2952 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
2953 const MachineInstr &Second) const {
2954 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2955 const MachineOperand &Op = Second.getOperand(0);
2956 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2957 return true;
2958 }
2959 if (DisableNVSchedule)
2960 return false;
2961 if (mayBeNewStore(Second)) {
2962 // Make sure the definition of the first instruction is the value being
2963 // stored.
2964 const MachineOperand &Stored =
2965 Second.getOperand(Second.getNumOperands() - 1);
2966 if (!Stored.isReg())
2967 return false;
2968 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2969 const MachineOperand &Op = First.getOperand(i);
2970 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2971 return true;
2972 }
2973 }
2974 return false;
2975 }
2976
doesNotReturn(const MachineInstr & CallMI) const2977 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
2978 unsigned Opc = CallMI.getOpcode();
2979 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2980 }
2981
hasEHLabel(const MachineBasicBlock * B) const2982 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2983 for (auto &I : *B)
2984 if (I.isEHLabel())
2985 return true;
2986 return false;
2987 }
2988
2989 // Returns true if an instruction can be converted into a non-extended
2990 // equivalent instruction.
hasNonExtEquivalent(const MachineInstr & MI) const2991 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
2992 short NonExtOpcode;
2993 // Check if the instruction has a register form that uses register in place
2994 // of the extended operand, if so return that as the non-extended form.
2995 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2996 return true;
2997
2998 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2999 // Check addressing mode and retrieve non-ext equivalent instruction.
3000
3001 switch (getAddrMode(MI)) {
3002 case HexagonII::Absolute:
3003 // Load/store with absolute addressing mode can be converted into
3004 // base+offset mode.
3005 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3006 break;
3007 case HexagonII::BaseImmOffset:
3008 // Load/store with base+offset addressing mode can be converted into
3009 // base+register offset addressing mode. However left shift operand should
3010 // be set to 0.
3011 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3012 break;
3013 case HexagonII::BaseLongOffset:
3014 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3015 break;
3016 default:
3017 return false;
3018 }
3019 if (NonExtOpcode < 0)
3020 return false;
3021 return true;
3022 }
3023 return false;
3024 }
3025
hasPseudoInstrPair(const MachineInstr & MI) const3026 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3027 return Hexagon::getRealHWInstr(MI.getOpcode(),
3028 Hexagon::InstrType_Pseudo) >= 0;
3029 }
3030
hasUncondBranch(const MachineBasicBlock * B) const3031 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3032 const {
3033 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3034 while (I != E) {
3035 if (I->isBarrier())
3036 return true;
3037 ++I;
3038 }
3039 return false;
3040 }
3041
3042 // Returns true, if a LD insn can be promoted to a cur load.
mayBeCurLoad(const MachineInstr & MI) const3043 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3044 const uint64_t F = MI.getDesc().TSFlags;
3045 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
3046 Subtarget.hasV60Ops();
3047 }
3048
3049 // Returns true, if a ST insn can be promoted to a new-value store.
mayBeNewStore(const MachineInstr & MI) const3050 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3051 if (MI.mayStore() && !Subtarget.useNewValueStores())
3052 return false;
3053
3054 const uint64_t F = MI.getDesc().TSFlags;
3055 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
3056 }
3057
producesStall(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const3058 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3059 const MachineInstr &ConsMI) const {
3060 // There is no stall when ProdMI is not a V60 vector.
3061 if (!isHVXVec(ProdMI))
3062 return false;
3063
3064 // There is no stall when ProdMI and ConsMI are not dependent.
3065 if (!isDependent(ProdMI, ConsMI))
3066 return false;
3067
3068 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3069 // are scheduled in consecutive packets.
3070 if (isVecUsableNextPacket(ProdMI, ConsMI))
3071 return false;
3072
3073 return true;
3074 }
3075
producesStall(const MachineInstr & MI,MachineBasicBlock::const_instr_iterator BII) const3076 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3077 MachineBasicBlock::const_instr_iterator BII) const {
3078 // There is no stall when I is not a V60 vector.
3079 if (!isHVXVec(MI))
3080 return false;
3081
3082 MachineBasicBlock::const_instr_iterator MII = BII;
3083 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3084
3085 if (!MII->isBundle())
3086 return producesStall(*MII, MI);
3087
3088 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3089 const MachineInstr &J = *MII;
3090 if (producesStall(J, MI))
3091 return true;
3092 }
3093 return false;
3094 }
3095
predCanBeUsedAsDotNew(const MachineInstr & MI,unsigned PredReg) const3096 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3097 unsigned PredReg) const {
3098 for (const MachineOperand &MO : MI.operands()) {
3099 // Predicate register must be explicitly defined.
3100 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3101 return false;
3102 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3103 return false;
3104 }
3105
3106 // Instruction that produce late predicate cannot be used as sources of
3107 // dot-new.
3108 switch (MI.getOpcode()) {
3109 case Hexagon::A4_addp_c:
3110 case Hexagon::A4_subp_c:
3111 case Hexagon::A4_tlbmatch:
3112 case Hexagon::A5_ACS:
3113 case Hexagon::F2_sfinvsqrta:
3114 case Hexagon::F2_sfrecipa:
3115 case Hexagon::J2_endloop0:
3116 case Hexagon::J2_endloop01:
3117 case Hexagon::J2_ploop1si:
3118 case Hexagon::J2_ploop1sr:
3119 case Hexagon::J2_ploop2si:
3120 case Hexagon::J2_ploop2sr:
3121 case Hexagon::J2_ploop3si:
3122 case Hexagon::J2_ploop3sr:
3123 case Hexagon::S2_cabacdecbin:
3124 case Hexagon::S2_storew_locked:
3125 case Hexagon::S4_stored_locked:
3126 return false;
3127 }
3128 return true;
3129 }
3130
PredOpcodeHasJMP_c(unsigned Opcode) const3131 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3132 return Opcode == Hexagon::J2_jumpt ||
3133 Opcode == Hexagon::J2_jumptpt ||
3134 Opcode == Hexagon::J2_jumpf ||
3135 Opcode == Hexagon::J2_jumpfpt ||
3136 Opcode == Hexagon::J2_jumptnew ||
3137 Opcode == Hexagon::J2_jumpfnew ||
3138 Opcode == Hexagon::J2_jumptnewpt ||
3139 Opcode == Hexagon::J2_jumpfnewpt;
3140 }
3141
predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const3142 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3143 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3144 return false;
3145 return !isPredicatedTrue(Cond[0].getImm());
3146 }
3147
getAddrMode(const MachineInstr & MI) const3148 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3149 const uint64_t F = MI.getDesc().TSFlags;
3150 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3151 }
3152
3153 // Returns the base register in a memory access (load/store). The offset is
3154 // returned in Offset and the access size is returned in AccessSize.
3155 // If the base operand has a subregister or the offset field does not contain
3156 // an immediate value, return nullptr.
getBaseAndOffset(const MachineInstr & MI,int64_t & Offset,unsigned & AccessSize) const3157 MachineOperand *HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3158 int64_t &Offset,
3159 unsigned &AccessSize) const {
3160 // Return if it is not a base+offset type instruction or a MemOp.
3161 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3162 getAddrMode(MI) != HexagonII::BaseLongOffset &&
3163 !isMemOp(MI) && !isPostIncrement(MI))
3164 return nullptr;
3165
3166 AccessSize = getMemAccessSize(MI);
3167
3168 unsigned BasePos = 0, OffsetPos = 0;
3169 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3170 return nullptr;
3171
3172 // Post increment updates its EA after the mem access,
3173 // so we need to treat its offset as zero.
3174 if (isPostIncrement(MI)) {
3175 Offset = 0;
3176 } else {
3177 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3178 if (!OffsetOp.isImm())
3179 return nullptr;
3180 Offset = OffsetOp.getImm();
3181 }
3182
3183 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3184 if (BaseOp.getSubReg() != 0)
3185 return nullptr;
3186 return &const_cast<MachineOperand&>(BaseOp);
3187 }
3188
3189 /// Return the position of the base and offset operands for this instruction.
getBaseAndOffsetPosition(const MachineInstr & MI,unsigned & BasePos,unsigned & OffsetPos) const3190 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3191 unsigned &BasePos, unsigned &OffsetPos) const {
3192 if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3193 return false;
3194
3195 // Deal with memops first.
3196 if (isMemOp(MI)) {
3197 BasePos = 0;
3198 OffsetPos = 1;
3199 } else if (MI.mayStore()) {
3200 BasePos = 0;
3201 OffsetPos = 1;
3202 } else if (MI.mayLoad()) {
3203 BasePos = 1;
3204 OffsetPos = 2;
3205 } else
3206 return false;
3207
3208 if (isPredicated(MI)) {
3209 BasePos++;
3210 OffsetPos++;
3211 }
3212 if (isPostIncrement(MI)) {
3213 BasePos++;
3214 OffsetPos++;
3215 }
3216
3217 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3218 return false;
3219
3220 return true;
3221 }
3222
3223 // Inserts branching instructions in reverse order of their occurrence.
3224 // e.g. jump_t t1 (i1)
3225 // jump t2 (i2)
3226 // Jumpers = {i2, i1}
getBranchingInstrs(MachineBasicBlock & MBB) const3227 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3228 MachineBasicBlock& MBB) const {
3229 SmallVector<MachineInstr*, 2> Jumpers;
3230 // If the block has no terminators, it just falls into the block after it.
3231 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3232 if (I == MBB.instr_begin())
3233 return Jumpers;
3234
3235 // A basic block may looks like this:
3236 //
3237 // [ insn
3238 // EH_LABEL
3239 // insn
3240 // insn
3241 // insn
3242 // EH_LABEL
3243 // insn ]
3244 //
3245 // It has two succs but does not have a terminator
3246 // Don't know how to handle it.
3247 do {
3248 --I;
3249 if (I->isEHLabel())
3250 return Jumpers;
3251 } while (I != MBB.instr_begin());
3252
3253 I = MBB.instr_end();
3254 --I;
3255
3256 while (I->isDebugInstr()) {
3257 if (I == MBB.instr_begin())
3258 return Jumpers;
3259 --I;
3260 }
3261 if (!isUnpredicatedTerminator(*I))
3262 return Jumpers;
3263
3264 // Get the last instruction in the block.
3265 MachineInstr *LastInst = &*I;
3266 Jumpers.push_back(LastInst);
3267 MachineInstr *SecondLastInst = nullptr;
3268 // Find one more terminator if present.
3269 do {
3270 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3271 if (!SecondLastInst) {
3272 SecondLastInst = &*I;
3273 Jumpers.push_back(SecondLastInst);
3274 } else // This is a third branch.
3275 return Jumpers;
3276 }
3277 if (I == MBB.instr_begin())
3278 break;
3279 --I;
3280 } while (true);
3281 return Jumpers;
3282 }
3283
3284 // Returns Operand Index for the constant extended instruction.
getCExtOpNum(const MachineInstr & MI) const3285 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3286 const uint64_t F = MI.getDesc().TSFlags;
3287 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3288 }
3289
3290 // See if instruction could potentially be a duplex candidate.
3291 // If so, return its group. Zero otherwise.
getCompoundCandidateGroup(const MachineInstr & MI) const3292 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3293 const MachineInstr &MI) const {
3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3295
3296 switch (MI.getOpcode()) {
3297 default:
3298 return HexagonII::HCG_None;
3299 //
3300 // Compound pairs.
3301 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3302 // "Rd16=#U6 ; jump #r9:2"
3303 // "Rd16=Rs16 ; jump #r9:2"
3304 //
3305 case Hexagon::C2_cmpeq:
3306 case Hexagon::C2_cmpgt:
3307 case Hexagon::C2_cmpgtu:
3308 DstReg = MI.getOperand(0).getReg();
3309 Src1Reg = MI.getOperand(1).getReg();
3310 Src2Reg = MI.getOperand(2).getReg();
3311 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3312 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3313 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3314 return HexagonII::HCG_A;
3315 break;
3316 case Hexagon::C2_cmpeqi:
3317 case Hexagon::C2_cmpgti:
3318 case Hexagon::C2_cmpgtui:
3319 // P0 = cmp.eq(Rs,#u2)
3320 DstReg = MI.getOperand(0).getReg();
3321 SrcReg = MI.getOperand(1).getReg();
3322 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3323 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3324 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3325 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3326 (MI.getOperand(2).getImm() == -1)))
3327 return HexagonII::HCG_A;
3328 break;
3329 case Hexagon::A2_tfr:
3330 // Rd = Rs
3331 DstReg = MI.getOperand(0).getReg();
3332 SrcReg = MI.getOperand(1).getReg();
3333 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3334 return HexagonII::HCG_A;
3335 break;
3336 case Hexagon::A2_tfrsi:
3337 // Rd = #u6
3338 // Do not test for #u6 size since the const is getting extended
3339 // regardless and compound could be formed.
3340 DstReg = MI.getOperand(0).getReg();
3341 if (isIntRegForSubInst(DstReg))
3342 return HexagonII::HCG_A;
3343 break;
3344 case Hexagon::S2_tstbit_i:
3345 DstReg = MI.getOperand(0).getReg();
3346 Src1Reg = MI.getOperand(1).getReg();
3347 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3348 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3349 MI.getOperand(2).isImm() &&
3350 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3351 return HexagonII::HCG_A;
3352 break;
3353 // The fact that .new form is used pretty much guarantees
3354 // that predicate register will match. Nevertheless,
3355 // there could be some false positives without additional
3356 // checking.
3357 case Hexagon::J2_jumptnew:
3358 case Hexagon::J2_jumpfnew:
3359 case Hexagon::J2_jumptnewpt:
3360 case Hexagon::J2_jumpfnewpt:
3361 Src1Reg = MI.getOperand(0).getReg();
3362 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3363 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3364 return HexagonII::HCG_B;
3365 break;
3366 // Transfer and jump:
3367 // Rd=#U6 ; jump #r9:2
3368 // Rd=Rs ; jump #r9:2
3369 // Do not test for jump range here.
3370 case Hexagon::J2_jump:
3371 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3372 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3373 return HexagonII::HCG_C;
3374 }
3375
3376 return HexagonII::HCG_None;
3377 }
3378
3379 // Returns -1 when there is no opcode found.
getCompoundOpcode(const MachineInstr & GA,const MachineInstr & GB) const3380 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3381 const MachineInstr &GB) const {
3382 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3383 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3384 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3385 (GB.getOpcode() != Hexagon::J2_jumptnew))
3386 return -1u;
3387 Register DestReg = GA.getOperand(0).getReg();
3388 if (!GB.readsRegister(DestReg))
3389 return -1u;
3390 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3391 return -1u;
3392 // The value compared against must be either u5 or -1.
3393 const MachineOperand &CmpOp = GA.getOperand(2);
3394 if (!CmpOp.isImm())
3395 return -1u;
3396 int V = CmpOp.getImm();
3397 if (V == -1)
3398 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3399 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3400 if (!isUInt<5>(V))
3401 return -1u;
3402 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3403 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3404 }
3405
getCondOpcode(int Opc,bool invertPredicate) const3406 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3407 enum Hexagon::PredSense inPredSense;
3408 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3409 Hexagon::PredSense_true;
3410 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3411 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3412 return CondOpcode;
3413
3414 llvm_unreachable("Unexpected predicable instruction");
3415 }
3416
3417 // Return the cur value instruction for a given store.
getDotCurOp(const MachineInstr & MI) const3418 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3419 switch (MI.getOpcode()) {
3420 default: llvm_unreachable("Unknown .cur type");
3421 case Hexagon::V6_vL32b_pi:
3422 return Hexagon::V6_vL32b_cur_pi;
3423 case Hexagon::V6_vL32b_ai:
3424 return Hexagon::V6_vL32b_cur_ai;
3425 case Hexagon::V6_vL32b_nt_pi:
3426 return Hexagon::V6_vL32b_nt_cur_pi;
3427 case Hexagon::V6_vL32b_nt_ai:
3428 return Hexagon::V6_vL32b_nt_cur_ai;
3429 }
3430 return 0;
3431 }
3432
3433 // Return the regular version of the .cur instruction.
getNonDotCurOp(const MachineInstr & MI) const3434 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3435 switch (MI.getOpcode()) {
3436 default: llvm_unreachable("Unknown .cur type");
3437 case Hexagon::V6_vL32b_cur_pi:
3438 return Hexagon::V6_vL32b_pi;
3439 case Hexagon::V6_vL32b_cur_ai:
3440 return Hexagon::V6_vL32b_ai;
3441 case Hexagon::V6_vL32b_nt_cur_pi:
3442 return Hexagon::V6_vL32b_nt_pi;
3443 case Hexagon::V6_vL32b_nt_cur_ai:
3444 return Hexagon::V6_vL32b_nt_ai;
3445 }
3446 return 0;
3447 }
3448
3449 // The diagram below shows the steps involved in the conversion of a predicated
3450 // store instruction to its .new predicated new-value form.
3451 //
3452 // Note: It doesn't include conditional new-value stores as they can't be
3453 // converted to .new predicate.
3454 //
3455 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3456 // ^ ^
3457 // / \ (not OK. it will cause new-value store to be
3458 // / X conditional on p0.new while R2 producer is
3459 // / \ on p0)
3460 // / \.
3461 // p.new store p.old NV store
3462 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3463 // ^ ^
3464 // \ /
3465 // \ /
3466 // \ /
3467 // p.old store
3468 // [if (p0)memw(R0+#0)=R2]
3469 //
3470 // The following set of instructions further explains the scenario where
3471 // conditional new-value store becomes invalid when promoted to .new predicate
3472 // form.
3473 //
3474 // { 1) if (p0) r0 = add(r1, r2)
3475 // 2) p0 = cmp.eq(r3, #0) }
3476 //
3477 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3478 // the first two instructions because in instr 1, r0 is conditional on old value
3479 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3480 // is not valid for new-value stores.
3481 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3482 // from the "Conditional Store" list. Because a predicated new value store
3483 // would NOT be promoted to a double dot new store. See diagram below:
3484 // This function returns yes for those stores that are predicated but not
3485 // yet promoted to predicate dot new instructions.
3486 //
3487 // +---------------------+
3488 // /-----| if (p0) memw(..)=r0 |---------\~
3489 // || +---------------------+ ||
3490 // promote || /\ /\ || promote
3491 // || /||\ /||\ ||
3492 // \||/ demote || \||/
3493 // \/ || || \/
3494 // +-------------------------+ || +-------------------------+
3495 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3496 // +-------------------------+ || +-------------------------+
3497 // || || ||
3498 // || demote \||/
3499 // promote || \/ NOT possible
3500 // || || /\~
3501 // \||/ || /||\~
3502 // \/ || ||
3503 // +-----------------------------+
3504 // | if (p0.new) memw(..)=r0.new |
3505 // +-----------------------------+
3506 // Double Dot New Store
3507 //
3508 // Returns the most basic instruction for the .new predicated instructions and
3509 // new-value stores.
3510 // For example, all of the following instructions will be converted back to the
3511 // same instruction:
3512 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3513 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3514 // 3) if (p0.new) memw(R0+#0) = R1 --->
3515 //
3516 // To understand the translation of instruction 1 to its original form, consider
3517 // a packet with 3 instructions.
3518 // { p0 = cmp.eq(R0,R1)
3519 // if (p0.new) R2 = add(R3, R4)
3520 // R5 = add (R3, R1)
3521 // }
3522 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3523 //
3524 // This instruction can be part of the previous packet only if both p0 and R2
3525 // are promoted to .new values. This promotion happens in steps, first
3526 // predicate register is promoted to .new and in the next iteration R2 is
3527 // promoted. Therefore, in case of dependence check failure (due to R5) during
3528 // next iteration, it should be converted back to its most basic form.
3529
3530 // Return the new value instruction for a given store.
getDotNewOp(const MachineInstr & MI) const3531 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3532 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3533 if (NVOpcode >= 0) // Valid new-value store instruction.
3534 return NVOpcode;
3535
3536 switch (MI.getOpcode()) {
3537 default:
3538 report_fatal_error(std::string("Unknown .new type: ") +
3539 std::to_string(MI.getOpcode()));
3540 case Hexagon::S4_storerb_ur:
3541 return Hexagon::S4_storerbnew_ur;
3542
3543 case Hexagon::S2_storerb_pci:
3544 return Hexagon::S2_storerb_pci;
3545
3546 case Hexagon::S2_storeri_pci:
3547 return Hexagon::S2_storeri_pci;
3548
3549 case Hexagon::S2_storerh_pci:
3550 return Hexagon::S2_storerh_pci;
3551
3552 case Hexagon::S2_storerd_pci:
3553 return Hexagon::S2_storerd_pci;
3554
3555 case Hexagon::S2_storerf_pci:
3556 return Hexagon::S2_storerf_pci;
3557
3558 case Hexagon::V6_vS32b_ai:
3559 return Hexagon::V6_vS32b_new_ai;
3560
3561 case Hexagon::V6_vS32b_pi:
3562 return Hexagon::V6_vS32b_new_pi;
3563 }
3564 return 0;
3565 }
3566
3567 // Returns the opcode to use when converting MI, which is a conditional jump,
3568 // into a conditional instruction which uses the .new value of the predicate.
3569 // We also use branch probabilities to add a hint to the jump.
3570 // If MBPI is null, all edges will be treated as equally likely for the
3571 // purposes of establishing a predication hint.
getDotNewPredJumpOp(const MachineInstr & MI,const MachineBranchProbabilityInfo * MBPI) const3572 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3573 const MachineBranchProbabilityInfo *MBPI) const {
3574 // We assume that block can have at most two successors.
3575 const MachineBasicBlock *Src = MI.getParent();
3576 const MachineOperand &BrTarget = MI.getOperand(1);
3577 bool Taken = false;
3578 const BranchProbability OneHalf(1, 2);
3579
3580 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3581 const MachineBasicBlock *Dst) {
3582 if (MBPI)
3583 return MBPI->getEdgeProbability(Src, Dst);
3584 return BranchProbability(1, Src->succ_size());
3585 };
3586
3587 if (BrTarget.isMBB()) {
3588 const MachineBasicBlock *Dst = BrTarget.getMBB();
3589 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3590 } else {
3591 // The branch target is not a basic block (most likely a function).
3592 // Since BPI only gives probabilities for targets that are basic blocks,
3593 // try to identify another target of this branch (potentially a fall-
3594 // -through) and check the probability of that target.
3595 //
3596 // The only handled branch combinations are:
3597 // - one conditional branch,
3598 // - one conditional branch followed by one unconditional branch.
3599 // Otherwise, assume not-taken.
3600 assert(MI.isConditionalBranch());
3601 const MachineBasicBlock &B = *MI.getParent();
3602 bool SawCond = false, Bad = false;
3603 for (const MachineInstr &I : B) {
3604 if (!I.isBranch())
3605 continue;
3606 if (I.isConditionalBranch()) {
3607 SawCond = true;
3608 if (&I != &MI) {
3609 Bad = true;
3610 break;
3611 }
3612 }
3613 if (I.isUnconditionalBranch() && !SawCond) {
3614 Bad = true;
3615 break;
3616 }
3617 }
3618 if (!Bad) {
3619 MachineBasicBlock::const_instr_iterator It(MI);
3620 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3621 if (NextIt == B.instr_end()) {
3622 // If this branch is the last, look for the fall-through block.
3623 for (const MachineBasicBlock *SB : B.successors()) {
3624 if (!B.isLayoutSuccessor(SB))
3625 continue;
3626 Taken = getEdgeProbability(Src, SB) < OneHalf;
3627 break;
3628 }
3629 } else {
3630 assert(NextIt->isUnconditionalBranch());
3631 // Find the first MBB operand and assume it's the target.
3632 const MachineBasicBlock *BT = nullptr;
3633 for (const MachineOperand &Op : NextIt->operands()) {
3634 if (!Op.isMBB())
3635 continue;
3636 BT = Op.getMBB();
3637 break;
3638 }
3639 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3640 }
3641 } // if (!Bad)
3642 }
3643
3644 // The Taken flag should be set to something reasonable by this point.
3645
3646 switch (MI.getOpcode()) {
3647 case Hexagon::J2_jumpt:
3648 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3649 case Hexagon::J2_jumpf:
3650 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3651
3652 default:
3653 llvm_unreachable("Unexpected jump instruction.");
3654 }
3655 }
3656
3657 // Return .new predicate version for an instruction.
getDotNewPredOp(const MachineInstr & MI,const MachineBranchProbabilityInfo * MBPI) const3658 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3659 const MachineBranchProbabilityInfo *MBPI) const {
3660 switch (MI.getOpcode()) {
3661 // Condtional Jumps
3662 case Hexagon::J2_jumpt:
3663 case Hexagon::J2_jumpf:
3664 return getDotNewPredJumpOp(MI, MBPI);
3665 }
3666
3667 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3668 if (NewOpcode >= 0)
3669 return NewOpcode;
3670 return 0;
3671 }
3672
getDotOldOp(const MachineInstr & MI) const3673 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3674 int NewOp = MI.getOpcode();
3675 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3676 NewOp = Hexagon::getPredOldOpcode(NewOp);
3677 // All Hexagon architectures have prediction bits on dot-new branches,
3678 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3679 // to pick the right opcode when converting back to dot-old.
3680 if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3681 switch (NewOp) {
3682 case Hexagon::J2_jumptpt:
3683 NewOp = Hexagon::J2_jumpt;
3684 break;
3685 case Hexagon::J2_jumpfpt:
3686 NewOp = Hexagon::J2_jumpf;
3687 break;
3688 case Hexagon::J2_jumprtpt:
3689 NewOp = Hexagon::J2_jumprt;
3690 break;
3691 case Hexagon::J2_jumprfpt:
3692 NewOp = Hexagon::J2_jumprf;
3693 break;
3694 }
3695 }
3696 assert(NewOp >= 0 &&
3697 "Couldn't change predicate new instruction to its old form.");
3698 }
3699
3700 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3701 NewOp = Hexagon::getNonNVStore(NewOp);
3702 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3703 }
3704
3705 if (Subtarget.hasV60Ops())
3706 return NewOp;
3707
3708 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3709 switch (NewOp) {
3710 case Hexagon::J2_jumpfpt:
3711 return Hexagon::J2_jumpf;
3712 case Hexagon::J2_jumptpt:
3713 return Hexagon::J2_jumpt;
3714 case Hexagon::J2_jumprfpt:
3715 return Hexagon::J2_jumprf;
3716 case Hexagon::J2_jumprtpt:
3717 return Hexagon::J2_jumprt;
3718 }
3719 return NewOp;
3720 }
3721
3722 // See if instruction could potentially be a duplex candidate.
3723 // If so, return its group. Zero otherwise.
getDuplexCandidateGroup(const MachineInstr & MI) const3724 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3725 const MachineInstr &MI) const {
3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3727 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3728
3729 switch (MI.getOpcode()) {
3730 default:
3731 return HexagonII::HSIG_None;
3732 //
3733 // Group L1:
3734 //
3735 // Rd = memw(Rs+#u4:2)
3736 // Rd = memub(Rs+#u4:0)
3737 case Hexagon::L2_loadri_io:
3738 DstReg = MI.getOperand(0).getReg();
3739 SrcReg = MI.getOperand(1).getReg();
3740 // Special case this one from Group L2.
3741 // Rd = memw(r29+#u5:2)
3742 if (isIntRegForSubInst(DstReg)) {
3743 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3744 HRI.getStackRegister() == SrcReg &&
3745 MI.getOperand(2).isImm() &&
3746 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3747 return HexagonII::HSIG_L2;
3748 // Rd = memw(Rs+#u4:2)
3749 if (isIntRegForSubInst(SrcReg) &&
3750 (MI.getOperand(2).isImm() &&
3751 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3752 return HexagonII::HSIG_L1;
3753 }
3754 break;
3755 case Hexagon::L2_loadrub_io:
3756 // Rd = memub(Rs+#u4:0)
3757 DstReg = MI.getOperand(0).getReg();
3758 SrcReg = MI.getOperand(1).getReg();
3759 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3760 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3761 return HexagonII::HSIG_L1;
3762 break;
3763 //
3764 // Group L2:
3765 //
3766 // Rd = memh/memuh(Rs+#u3:1)
3767 // Rd = memb(Rs+#u3:0)
3768 // Rd = memw(r29+#u5:2) - Handled above.
3769 // Rdd = memd(r29+#u5:3)
3770 // deallocframe
3771 // [if ([!]p0[.new])] dealloc_return
3772 // [if ([!]p0[.new])] jumpr r31
3773 case Hexagon::L2_loadrh_io:
3774 case Hexagon::L2_loadruh_io:
3775 // Rd = memh/memuh(Rs+#u3:1)
3776 DstReg = MI.getOperand(0).getReg();
3777 SrcReg = MI.getOperand(1).getReg();
3778 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3779 MI.getOperand(2).isImm() &&
3780 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3781 return HexagonII::HSIG_L2;
3782 break;
3783 case Hexagon::L2_loadrb_io:
3784 // Rd = memb(Rs+#u3:0)
3785 DstReg = MI.getOperand(0).getReg();
3786 SrcReg = MI.getOperand(1).getReg();
3787 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3788 MI.getOperand(2).isImm() &&
3789 isUInt<3>(MI.getOperand(2).getImm()))
3790 return HexagonII::HSIG_L2;
3791 break;
3792 case Hexagon::L2_loadrd_io:
3793 // Rdd = memd(r29+#u5:3)
3794 DstReg = MI.getOperand(0).getReg();
3795 SrcReg = MI.getOperand(1).getReg();
3796 if (isDblRegForSubInst(DstReg, HRI) &&
3797 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3798 HRI.getStackRegister() == SrcReg &&
3799 MI.getOperand(2).isImm() &&
3800 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3801 return HexagonII::HSIG_L2;
3802 break;
3803 // dealloc_return is not documented in Hexagon Manual, but marked
3804 // with A_SUBINSN attribute in iset_v4classic.py.
3805 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3806 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3807 case Hexagon::L4_return:
3808 case Hexagon::L2_deallocframe:
3809 return HexagonII::HSIG_L2;
3810 case Hexagon::EH_RETURN_JMPR:
3811 case Hexagon::PS_jmpret:
3812 case Hexagon::SL2_jumpr31:
3813 // jumpr r31
3814 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3815 DstReg = MI.getOperand(0).getReg();
3816 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3817 return HexagonII::HSIG_L2;
3818 break;
3819 case Hexagon::PS_jmprett:
3820 case Hexagon::PS_jmpretf:
3821 case Hexagon::PS_jmprettnewpt:
3822 case Hexagon::PS_jmpretfnewpt:
3823 case Hexagon::PS_jmprettnew:
3824 case Hexagon::PS_jmpretfnew:
3825 case Hexagon::SL2_jumpr31_t:
3826 case Hexagon::SL2_jumpr31_f:
3827 case Hexagon::SL2_jumpr31_tnew:
3828 DstReg = MI.getOperand(1).getReg();
3829 SrcReg = MI.getOperand(0).getReg();
3830 // [if ([!]p0[.new])] jumpr r31
3831 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3832 (Hexagon::P0 == SrcReg)) &&
3833 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3834 return HexagonII::HSIG_L2;
3835 break;
3836 case Hexagon::L4_return_t:
3837 case Hexagon::L4_return_f:
3838 case Hexagon::L4_return_tnew_pnt:
3839 case Hexagon::L4_return_fnew_pnt:
3840 case Hexagon::L4_return_tnew_pt:
3841 case Hexagon::L4_return_fnew_pt:
3842 // [if ([!]p0[.new])] dealloc_return
3843 SrcReg = MI.getOperand(0).getReg();
3844 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3845 return HexagonII::HSIG_L2;
3846 break;
3847 //
3848 // Group S1:
3849 //
3850 // memw(Rs+#u4:2) = Rt
3851 // memb(Rs+#u4:0) = Rt
3852 case Hexagon::S2_storeri_io:
3853 // Special case this one from Group S2.
3854 // memw(r29+#u5:2) = Rt
3855 Src1Reg = MI.getOperand(0).getReg();
3856 Src2Reg = MI.getOperand(2).getReg();
3857 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3858 isIntRegForSubInst(Src2Reg) &&
3859 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3860 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3861 return HexagonII::HSIG_S2;
3862 // memw(Rs+#u4:2) = Rt
3863 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3864 MI.getOperand(1).isImm() &&
3865 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3866 return HexagonII::HSIG_S1;
3867 break;
3868 case Hexagon::S2_storerb_io:
3869 // memb(Rs+#u4:0) = Rt
3870 Src1Reg = MI.getOperand(0).getReg();
3871 Src2Reg = MI.getOperand(2).getReg();
3872 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3873 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3874 return HexagonII::HSIG_S1;
3875 break;
3876 //
3877 // Group S2:
3878 //
3879 // memh(Rs+#u3:1) = Rt
3880 // memw(r29+#u5:2) = Rt
3881 // memd(r29+#s6:3) = Rtt
3882 // memw(Rs+#u4:2) = #U1
3883 // memb(Rs+#u4) = #U1
3884 // allocframe(#u5:3)
3885 case Hexagon::S2_storerh_io:
3886 // memh(Rs+#u3:1) = Rt
3887 Src1Reg = MI.getOperand(0).getReg();
3888 Src2Reg = MI.getOperand(2).getReg();
3889 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3890 MI.getOperand(1).isImm() &&
3891 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3892 return HexagonII::HSIG_S1;
3893 break;
3894 case Hexagon::S2_storerd_io:
3895 // memd(r29+#s6:3) = Rtt
3896 Src1Reg = MI.getOperand(0).getReg();
3897 Src2Reg = MI.getOperand(2).getReg();
3898 if (isDblRegForSubInst(Src2Reg, HRI) &&
3899 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3900 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3901 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3902 return HexagonII::HSIG_S2;
3903 break;
3904 case Hexagon::S4_storeiri_io:
3905 // memw(Rs+#u4:2) = #U1
3906 Src1Reg = MI.getOperand(0).getReg();
3907 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3908 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3909 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3910 return HexagonII::HSIG_S2;
3911 break;
3912 case Hexagon::S4_storeirb_io:
3913 // memb(Rs+#u4) = #U1
3914 Src1Reg = MI.getOperand(0).getReg();
3915 if (isIntRegForSubInst(Src1Reg) &&
3916 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3917 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3918 return HexagonII::HSIG_S2;
3919 break;
3920 case Hexagon::S2_allocframe:
3921 if (MI.getOperand(2).isImm() &&
3922 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3923 return HexagonII::HSIG_S1;
3924 break;
3925 //
3926 // Group A:
3927 //
3928 // Rx = add(Rx,#s7)
3929 // Rd = Rs
3930 // Rd = #u6
3931 // Rd = #-1
3932 // if ([!]P0[.new]) Rd = #0
3933 // Rd = add(r29,#u6:2)
3934 // Rx = add(Rx,Rs)
3935 // P0 = cmp.eq(Rs,#u2)
3936 // Rdd = combine(#0,Rs)
3937 // Rdd = combine(Rs,#0)
3938 // Rdd = combine(#u2,#U2)
3939 // Rd = add(Rs,#1)
3940 // Rd = add(Rs,#-1)
3941 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3942 // Rd = and(Rs,#1)
3943 case Hexagon::A2_addi:
3944 DstReg = MI.getOperand(0).getReg();
3945 SrcReg = MI.getOperand(1).getReg();
3946 if (isIntRegForSubInst(DstReg)) {
3947 // Rd = add(r29,#u6:2)
3948 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3949 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3950 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3951 return HexagonII::HSIG_A;
3952 // Rx = add(Rx,#s7)
3953 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3954 isInt<7>(MI.getOperand(2).getImm()))
3955 return HexagonII::HSIG_A;
3956 // Rd = add(Rs,#1)
3957 // Rd = add(Rs,#-1)
3958 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3959 ((MI.getOperand(2).getImm() == 1) ||
3960 (MI.getOperand(2).getImm() == -1)))
3961 return HexagonII::HSIG_A;
3962 }
3963 break;
3964 case Hexagon::A2_add:
3965 // Rx = add(Rx,Rs)
3966 DstReg = MI.getOperand(0).getReg();
3967 Src1Reg = MI.getOperand(1).getReg();
3968 Src2Reg = MI.getOperand(2).getReg();
3969 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3970 isIntRegForSubInst(Src2Reg))
3971 return HexagonII::HSIG_A;
3972 break;
3973 case Hexagon::A2_andir:
3974 // Same as zxtb.
3975 // Rd16=and(Rs16,#255)
3976 // Rd16=and(Rs16,#1)
3977 DstReg = MI.getOperand(0).getReg();
3978 SrcReg = MI.getOperand(1).getReg();
3979 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3980 MI.getOperand(2).isImm() &&
3981 ((MI.getOperand(2).getImm() == 1) ||
3982 (MI.getOperand(2).getImm() == 255)))
3983 return HexagonII::HSIG_A;
3984 break;
3985 case Hexagon::A2_tfr:
3986 // Rd = Rs
3987 DstReg = MI.getOperand(0).getReg();
3988 SrcReg = MI.getOperand(1).getReg();
3989 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3990 return HexagonII::HSIG_A;
3991 break;
3992 case Hexagon::A2_tfrsi:
3993 // Rd = #u6
3994 // Do not test for #u6 size since the const is getting extended
3995 // regardless and compound could be formed.
3996 // Rd = #-1
3997 DstReg = MI.getOperand(0).getReg();
3998 if (isIntRegForSubInst(DstReg))
3999 return HexagonII::HSIG_A;
4000 break;
4001 case Hexagon::C2_cmoveit:
4002 case Hexagon::C2_cmovenewit:
4003 case Hexagon::C2_cmoveif:
4004 case Hexagon::C2_cmovenewif:
4005 // if ([!]P0[.new]) Rd = #0
4006 // Actual form:
4007 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4008 DstReg = MI.getOperand(0).getReg();
4009 SrcReg = MI.getOperand(1).getReg();
4010 if (isIntRegForSubInst(DstReg) &&
4011 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4012 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4013 return HexagonII::HSIG_A;
4014 break;
4015 case Hexagon::C2_cmpeqi:
4016 // P0 = cmp.eq(Rs,#u2)
4017 DstReg = MI.getOperand(0).getReg();
4018 SrcReg = MI.getOperand(1).getReg();
4019 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4020 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4021 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4022 return HexagonII::HSIG_A;
4023 break;
4024 case Hexagon::A2_combineii:
4025 case Hexagon::A4_combineii:
4026 // Rdd = combine(#u2,#U2)
4027 DstReg = MI.getOperand(0).getReg();
4028 if (isDblRegForSubInst(DstReg, HRI) &&
4029 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4030 (MI.getOperand(1).isGlobal() &&
4031 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4032 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4033 (MI.getOperand(2).isGlobal() &&
4034 isUInt<2>(MI.getOperand(2).getOffset()))))
4035 return HexagonII::HSIG_A;
4036 break;
4037 case Hexagon::A4_combineri:
4038 // Rdd = combine(Rs,#0)
4039 DstReg = MI.getOperand(0).getReg();
4040 SrcReg = MI.getOperand(1).getReg();
4041 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4042 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4043 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4044 return HexagonII::HSIG_A;
4045 break;
4046 case Hexagon::A4_combineir:
4047 // Rdd = combine(#0,Rs)
4048 DstReg = MI.getOperand(0).getReg();
4049 SrcReg = MI.getOperand(2).getReg();
4050 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4051 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4052 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4053 return HexagonII::HSIG_A;
4054 break;
4055 case Hexagon::A2_sxtb:
4056 case Hexagon::A2_sxth:
4057 case Hexagon::A2_zxtb:
4058 case Hexagon::A2_zxth:
4059 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4060 DstReg = MI.getOperand(0).getReg();
4061 SrcReg = MI.getOperand(1).getReg();
4062 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4063 return HexagonII::HSIG_A;
4064 break;
4065 }
4066
4067 return HexagonII::HSIG_None;
4068 }
4069
getEquivalentHWInstr(const MachineInstr & MI) const4070 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4071 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4072 }
4073
getInstrTimingClassLatency(const InstrItineraryData * ItinData,const MachineInstr & MI) const4074 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4075 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4076 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4077 // still have a MinLatency property, which getStageLatency checks.
4078 if (!ItinData)
4079 return getInstrLatency(ItinData, MI);
4080
4081 if (MI.isTransient())
4082 return 0;
4083 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4084 }
4085
4086 /// getOperandLatency - Compute and return the use operand latency of a given
4087 /// pair of def and use.
4088 /// In most cases, the static scheduling itinerary was enough to determine the
4089 /// operand latency. But it may not be possible for instructions with variable
4090 /// number of defs / uses.
4091 ///
4092 /// This is a raw interface to the itinerary that may be directly overriden by
4093 /// a target. Use computeOperandLatency to get the best estimate of latency.
getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const4094 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4095 const MachineInstr &DefMI,
4096 unsigned DefIdx,
4097 const MachineInstr &UseMI,
4098 unsigned UseIdx) const {
4099 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4100
4101 // Get DefIdx and UseIdx for super registers.
4102 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4103
4104 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4105 if (DefMO.isImplicit()) {
4106 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4107 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4108 if (Idx != -1) {
4109 DefIdx = Idx;
4110 break;
4111 }
4112 }
4113 }
4114
4115 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4116 if (UseMO.isImplicit()) {
4117 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4118 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4119 if (Idx != -1) {
4120 UseIdx = Idx;
4121 break;
4122 }
4123 }
4124 }
4125 }
4126
4127 int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4128 UseMI, UseIdx);
4129 if (!Latency)
4130 // We should never have 0 cycle latency between two instructions unless
4131 // they can be packetized together. However, this decision can't be made
4132 // here.
4133 Latency = 1;
4134 return Latency;
4135 }
4136
4137 // inverts the predication logic.
4138 // p -> NotP
4139 // NotP -> P
getInvertedPredSense(SmallVectorImpl<MachineOperand> & Cond) const4140 bool HexagonInstrInfo::getInvertedPredSense(
4141 SmallVectorImpl<MachineOperand> &Cond) const {
4142 if (Cond.empty())
4143 return false;
4144 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4145 Cond[0].setImm(Opc);
4146 return true;
4147 }
4148
getInvertedPredicatedOpcode(const int Opc) const4149 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4150 int InvPredOpcode;
4151 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4152 : Hexagon::getTruePredOpcode(Opc);
4153 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4154 return InvPredOpcode;
4155
4156 llvm_unreachable("Unexpected predicated instruction");
4157 }
4158
4159 // Returns the max value that doesn't need to be extended.
getMaxValue(const MachineInstr & MI) const4160 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4161 const uint64_t F = MI.getDesc().TSFlags;
4162 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4163 & HexagonII::ExtentSignedMask;
4164 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4165 & HexagonII::ExtentBitsMask;
4166
4167 if (isSigned) // if value is signed
4168 return ~(-1U << (bits - 1));
4169 else
4170 return ~(-1U << bits);
4171 }
4172
4173
isAddrModeWithOffset(const MachineInstr & MI) const4174 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4175 switch (MI.getOpcode()) {
4176 case Hexagon::L2_loadrbgp:
4177 case Hexagon::L2_loadrdgp:
4178 case Hexagon::L2_loadrhgp:
4179 case Hexagon::L2_loadrigp:
4180 case Hexagon::L2_loadrubgp:
4181 case Hexagon::L2_loadruhgp:
4182 case Hexagon::S2_storerbgp:
4183 case Hexagon::S2_storerbnewgp:
4184 case Hexagon::S2_storerhgp:
4185 case Hexagon::S2_storerhnewgp:
4186 case Hexagon::S2_storerigp:
4187 case Hexagon::S2_storerinewgp:
4188 case Hexagon::S2_storerdgp:
4189 case Hexagon::S2_storerfgp:
4190 return true;
4191 }
4192 const uint64_t F = MI.getDesc().TSFlags;
4193 unsigned addrMode =
4194 ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
4195 // Disallow any base+offset instruction. The assembler does not yet reorder
4196 // based up any zero offset instruction.
4197 return (addrMode == HexagonII::BaseRegOffset ||
4198 addrMode == HexagonII::BaseImmOffset ||
4199 addrMode == HexagonII::BaseLongOffset);
4200 }
4201
getMemAccessSize(const MachineInstr & MI) const4202 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4203 using namespace HexagonII;
4204
4205 const uint64_t F = MI.getDesc().TSFlags;
4206 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4207 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4208 if (Size != 0)
4209 return Size;
4210
4211 // Handle vector access sizes.
4212 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4213 switch (S) {
4214 case HexagonII::HVXVectorAccess:
4215 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4216 default:
4217 llvm_unreachable("Unexpected instruction");
4218 }
4219 }
4220
4221 // Returns the min value that doesn't need to be extended.
getMinValue(const MachineInstr & MI) const4222 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4223 const uint64_t F = MI.getDesc().TSFlags;
4224 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4225 & HexagonII::ExtentSignedMask;
4226 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4227 & HexagonII::ExtentBitsMask;
4228
4229 if (isSigned) // if value is signed
4230 return -1U << (bits - 1);
4231 else
4232 return 0;
4233 }
4234
4235 // Returns opcode of the non-extended equivalent instruction.
getNonExtOpcode(const MachineInstr & MI) const4236 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4237 // Check if the instruction has a register form that uses register in place
4238 // of the extended operand, if so return that as the non-extended form.
4239 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4240 if (NonExtOpcode >= 0)
4241 return NonExtOpcode;
4242
4243 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4244 // Check addressing mode and retrieve non-ext equivalent instruction.
4245 switch (getAddrMode(MI)) {
4246 case HexagonII::Absolute:
4247 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4248 case HexagonII::BaseImmOffset:
4249 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4250 case HexagonII::BaseLongOffset:
4251 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4252
4253 default:
4254 return -1;
4255 }
4256 }
4257 return -1;
4258 }
4259
getPredReg(ArrayRef<MachineOperand> Cond,unsigned & PredReg,unsigned & PredRegPos,unsigned & PredRegFlags) const4260 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4261 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4262 if (Cond.empty())
4263 return false;
4264 assert(Cond.size() == 2);
4265 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4266 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4267 return false;
4268 }
4269 PredReg = Cond[1].getReg();
4270 PredRegPos = 1;
4271 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4272 PredRegFlags = 0;
4273 if (Cond[1].isImplicit())
4274 PredRegFlags = RegState::Implicit;
4275 if (Cond[1].isUndef())
4276 PredRegFlags |= RegState::Undef;
4277 return true;
4278 }
4279
getPseudoInstrPair(const MachineInstr & MI) const4280 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4281 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4282 }
4283
getRegForm(const MachineInstr & MI) const4284 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4285 return Hexagon::getRegForm(MI.getOpcode());
4286 }
4287
4288 // Return the number of bytes required to encode the instruction.
4289 // Hexagon instructions are fixed length, 4 bytes, unless they
4290 // use a constant extender, which requires another 4 bytes.
4291 // For debug instructions and prolog labels, return 0.
getSize(const MachineInstr & MI) const4292 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4293 if (MI.isDebugInstr() || MI.isPosition())
4294 return 0;
4295
4296 unsigned Size = MI.getDesc().getSize();
4297 if (!Size)
4298 // Assume the default insn size in case it cannot be determined
4299 // for whatever reason.
4300 Size = HEXAGON_INSTR_SIZE;
4301
4302 if (isConstExtended(MI) || isExtended(MI))
4303 Size += HEXAGON_INSTR_SIZE;
4304
4305 // Try and compute number of instructions in asm.
4306 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4307 const MachineBasicBlock &MBB = *MI.getParent();
4308 const MachineFunction *MF = MBB.getParent();
4309 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4310
4311 // Count the number of register definitions to find the asm string.
4312 unsigned NumDefs = 0;
4313 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4314 ++NumDefs)
4315 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4316
4317 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4318 // Disassemble the AsmStr and approximate number of instructions.
4319 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4320 Size = getInlineAsmLength(AsmStr, *MAI);
4321 }
4322
4323 return Size;
4324 }
4325
getType(const MachineInstr & MI) const4326 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4327 const uint64_t F = MI.getDesc().TSFlags;
4328 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4329 }
4330
getUnits(const MachineInstr & MI) const4331 unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4332 const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4333 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4334
4335 return IS.getUnits();
4336 }
4337
4338 // Calculate size of the basic block without debug instructions.
nonDbgBBSize(const MachineBasicBlock * BB) const4339 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4340 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4341 }
4342
nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const4343 unsigned HexagonInstrInfo::nonDbgBundleSize(
4344 MachineBasicBlock::const_iterator BundleHead) const {
4345 assert(BundleHead->isBundle() && "Not a bundle header");
4346 auto MII = BundleHead.getInstrIterator();
4347 // Skip the bundle header.
4348 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4349 }
4350
4351 /// immediateExtend - Changes the instruction in place to one using an immediate
4352 /// extender.
immediateExtend(MachineInstr & MI) const4353 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4354 assert((isExtendable(MI)||isConstExtended(MI)) &&
4355 "Instruction must be extendable");
4356 // Find which operand is extendable.
4357 short ExtOpNum = getCExtOpNum(MI);
4358 MachineOperand &MO = MI.getOperand(ExtOpNum);
4359 // This needs to be something we understand.
4360 assert((MO.isMBB() || MO.isImm()) &&
4361 "Branch with unknown extendable field type");
4362 // Mark given operand as extended.
4363 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4364 }
4365
invertAndChangeJumpTarget(MachineInstr & MI,MachineBasicBlock * NewTarget) const4366 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4367 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4368 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4369 << printMBBReference(*NewTarget);
4370 MI.dump(););
4371 assert(MI.isBranch());
4372 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4373 int TargetPos = MI.getNumOperands() - 1;
4374 // In general branch target is the last operand,
4375 // but some implicit defs added at the end might change it.
4376 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4377 --TargetPos;
4378 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4379 MI.getOperand(TargetPos).setMBB(NewTarget);
4380 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4381 NewOpcode = reversePrediction(NewOpcode);
4382 }
4383 MI.setDesc(get(NewOpcode));
4384 return true;
4385 }
4386
genAllInsnTimingClasses(MachineFunction & MF) const4387 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4388 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4389 MachineFunction::iterator A = MF.begin();
4390 MachineBasicBlock &B = *A;
4391 MachineBasicBlock::iterator I = B.begin();
4392 DebugLoc DL = I->getDebugLoc();
4393 MachineInstr *NewMI;
4394
4395 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4396 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4397 NewMI = BuildMI(B, I, DL, get(insn));
4398 LLVM_DEBUG(dbgs() << "\n"
4399 << getName(NewMI->getOpcode())
4400 << " Class: " << NewMI->getDesc().getSchedClass());
4401 NewMI->eraseFromParent();
4402 }
4403 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4404 }
4405
4406 // inverts the predication logic.
4407 // p -> NotP
4408 // NotP -> P
reversePredSense(MachineInstr & MI) const4409 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4410 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4411 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4412 return true;
4413 }
4414
4415 // Reverse the branch prediction.
reversePrediction(unsigned Opcode) const4416 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4417 int PredRevOpcode = -1;
4418 if (isPredictedTaken(Opcode))
4419 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4420 else
4421 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4422 assert(PredRevOpcode > 0);
4423 return PredRevOpcode;
4424 }
4425
4426 // TODO: Add more rigorous validation.
validateBranchCond(const ArrayRef<MachineOperand> & Cond) const4427 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4428 const {
4429 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4430 }
4431
4432 void HexagonInstrInfo::
setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const4433 setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
4434 assert(MIB->isBundle());
4435 MachineOperand &Operand = MIB->getOperand(0);
4436 if (Operand.isImm())
4437 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4438 else
4439 MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4440 }
4441
getBundleNoShuf(const MachineInstr & MIB) const4442 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4443 assert(MIB.isBundle());
4444 const MachineOperand &Operand = MIB.getOperand(0);
4445 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4446 }
4447
4448 // Addressing mode relations.
changeAddrMode_abs_io(short Opc) const4449 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4450 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4451 }
4452
changeAddrMode_io_abs(short Opc) const4453 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4454 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4455 }
4456
changeAddrMode_io_pi(short Opc) const4457 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4458 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4459 }
4460
changeAddrMode_io_rr(short Opc) const4461 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4462 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4463 }
4464
changeAddrMode_pi_io(short Opc) const4465 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4466 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4467 }
4468
changeAddrMode_rr_io(short Opc) const4469 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
4470 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4471 }
4472
changeAddrMode_rr_ur(short Opc) const4473 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
4474 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4475 }
4476
changeAddrMode_ur_rr(short Opc) const4477 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
4478 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4479 }
4480