1//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 MPX instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM. 16let SchedRW = [WriteSystem] in { 17 18multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> { 19 def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), 20 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>, 21 Requires<[Not64BitMode]>; 22 def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), 23 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>, 24 Requires<[In64BitMode]>; 25} 26 27defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; 28 29multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> { 30 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2), 31 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, 32 Requires<[Not64BitMode]>; 33 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2), 34 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, 35 Requires<[In64BitMode]>; 36 37 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2), 38 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, 39 Requires<[Not64BitMode]>; 40 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2), 41 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, 42 Requires<[In64BitMode]>; 43} 44defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; 45defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; 46defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; 47 48def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), 49 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 50 NotMemoryFoldable; 51let mayLoad = 1 in { 52def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), 53 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 54 Requires<[Not64BitMode]>, NotMemoryFoldable; 55def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), 56 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 57 Requires<[In64BitMode]>, NotMemoryFoldable; 58} 59let isCodeGenOnly = 1, ForceDisassemble = 1 in 60def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), 61 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 62 NotMemoryFoldable; 63let mayStore = 1 in { 64def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), 65 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 66 Requires<[Not64BitMode]>, NotMemoryFoldable; 67def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), 68 "bndmov\t{$src, $dst|$dst, $src}", []>, PD, 69 Requires<[In64BitMode]>, NotMemoryFoldable; 70 71def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), 72 "bndstx\t{$src, $dst|$dst, $src}", []>, PS; 73} 74let mayLoad = 1 in 75def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), 76 "bndldx\t{$src, $dst|$dst, $src}", []>, PS; 77} // SchedRW 78