1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "util/u_debug.h"
29 #include "pipe/p_shader_tokens.h"
30 #include "tgsi_parse.h"
31 #include "tgsi_util.h"
32
33 union pointer_hack
34 {
35 void *pointer;
36 uint64_t uint64;
37 };
38
39 void *
tgsi_align_128bit(void * unaligned)40 tgsi_align_128bit(
41 void *unaligned )
42 {
43 union pointer_hack ph;
44
45 ph.uint64 = 0;
46 ph.pointer = unaligned;
47 ph.uint64 = (ph.uint64 + 15) & ~15;
48 return ph.pointer;
49 }
50
51 unsigned
tgsi_util_get_src_register_swizzle(const struct tgsi_src_register * reg,unsigned component)52 tgsi_util_get_src_register_swizzle(
53 const struct tgsi_src_register *reg,
54 unsigned component )
55 {
56 switch( component ) {
57 case 0:
58 return reg->SwizzleX;
59 case 1:
60 return reg->SwizzleY;
61 case 2:
62 return reg->SwizzleZ;
63 case 3:
64 return reg->SwizzleW;
65 default:
66 assert( 0 );
67 }
68 return 0;
69 }
70
71
72 unsigned
tgsi_util_get_full_src_register_swizzle(const struct tgsi_full_src_register * reg,unsigned component)73 tgsi_util_get_full_src_register_swizzle(
74 const struct tgsi_full_src_register *reg,
75 unsigned component )
76 {
77 return tgsi_util_get_src_register_swizzle(
78 ®->Register,
79 component );
80 }
81
82 void
tgsi_util_set_src_register_swizzle(struct tgsi_src_register * reg,unsigned swizzle,unsigned component)83 tgsi_util_set_src_register_swizzle(
84 struct tgsi_src_register *reg,
85 unsigned swizzle,
86 unsigned component )
87 {
88 switch( component ) {
89 case 0:
90 reg->SwizzleX = swizzle;
91 break;
92 case 1:
93 reg->SwizzleY = swizzle;
94 break;
95 case 2:
96 reg->SwizzleZ = swizzle;
97 break;
98 case 3:
99 reg->SwizzleW = swizzle;
100 break;
101 default:
102 assert( 0 );
103 }
104 }
105
106 unsigned
tgsi_util_get_full_src_register_sign_mode(const struct tgsi_full_src_register * reg,UNUSED unsigned component)107 tgsi_util_get_full_src_register_sign_mode(
108 const struct tgsi_full_src_register *reg,
109 UNUSED unsigned component )
110 {
111 unsigned sign_mode;
112
113 if( reg->Register.Absolute ) {
114 /* Consider only the post-abs negation. */
115
116 if( reg->Register.Negate ) {
117 sign_mode = TGSI_UTIL_SIGN_SET;
118 }
119 else {
120 sign_mode = TGSI_UTIL_SIGN_CLEAR;
121 }
122 }
123 else {
124 if( reg->Register.Negate ) {
125 sign_mode = TGSI_UTIL_SIGN_TOGGLE;
126 }
127 else {
128 sign_mode = TGSI_UTIL_SIGN_KEEP;
129 }
130 }
131
132 return sign_mode;
133 }
134
135 void
tgsi_util_set_full_src_register_sign_mode(struct tgsi_full_src_register * reg,unsigned sign_mode)136 tgsi_util_set_full_src_register_sign_mode(
137 struct tgsi_full_src_register *reg,
138 unsigned sign_mode )
139 {
140 switch (sign_mode)
141 {
142 case TGSI_UTIL_SIGN_CLEAR:
143 reg->Register.Negate = 0;
144 reg->Register.Absolute = 1;
145 break;
146
147 case TGSI_UTIL_SIGN_SET:
148 reg->Register.Absolute = 1;
149 reg->Register.Negate = 1;
150 break;
151
152 case TGSI_UTIL_SIGN_TOGGLE:
153 reg->Register.Negate = 1;
154 reg->Register.Absolute = 0;
155 break;
156
157 case TGSI_UTIL_SIGN_KEEP:
158 reg->Register.Negate = 0;
159 reg->Register.Absolute = 0;
160 break;
161
162 default:
163 assert( 0 );
164 }
165 }
166
167 /**
168 * Determine which channels of the specificed src register are effectively
169 * used by this instruction.
170 */
171 unsigned
tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction * inst,unsigned src_idx)172 tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst,
173 unsigned src_idx)
174 {
175 const struct tgsi_full_src_register *src = &inst->Src[src_idx];
176 unsigned write_mask = inst->Dst[0].Register.WriteMask;
177 unsigned read_mask;
178 unsigned usage_mask;
179 unsigned chan;
180
181 switch (inst->Instruction.Opcode) {
182 case TGSI_OPCODE_MOV:
183 case TGSI_OPCODE_ARL:
184 case TGSI_OPCODE_ARR:
185 case TGSI_OPCODE_RCP:
186 case TGSI_OPCODE_MUL:
187 case TGSI_OPCODE_DIV:
188 case TGSI_OPCODE_ADD:
189 case TGSI_OPCODE_MIN:
190 case TGSI_OPCODE_MAX:
191 case TGSI_OPCODE_SLT:
192 case TGSI_OPCODE_SGE:
193 case TGSI_OPCODE_MAD:
194 case TGSI_OPCODE_SUB:
195 case TGSI_OPCODE_LRP:
196 case TGSI_OPCODE_FRC:
197 case TGSI_OPCODE_CEIL:
198 case TGSI_OPCODE_FLR:
199 case TGSI_OPCODE_ROUND:
200 case TGSI_OPCODE_POW:
201 case TGSI_OPCODE_ABS:
202 case TGSI_OPCODE_COS:
203 case TGSI_OPCODE_SIN:
204 case TGSI_OPCODE_DDX:
205 case TGSI_OPCODE_DDY:
206 case TGSI_OPCODE_SEQ:
207 case TGSI_OPCODE_SGT:
208 case TGSI_OPCODE_SLE:
209 case TGSI_OPCODE_SNE:
210 case TGSI_OPCODE_SSG:
211 case TGSI_OPCODE_CMP:
212 case TGSI_OPCODE_TRUNC:
213 case TGSI_OPCODE_NOT:
214 case TGSI_OPCODE_AND:
215 case TGSI_OPCODE_OR:
216 case TGSI_OPCODE_XOR:
217 case TGSI_OPCODE_FSEQ:
218 case TGSI_OPCODE_FSGE:
219 case TGSI_OPCODE_FSLT:
220 case TGSI_OPCODE_FSNE:
221 case TGSI_OPCODE_F2I:
222 case TGSI_OPCODE_IDIV:
223 case TGSI_OPCODE_IMAX:
224 case TGSI_OPCODE_IMIN:
225 case TGSI_OPCODE_INEG:
226 case TGSI_OPCODE_ISGE:
227 case TGSI_OPCODE_ISHR:
228 case TGSI_OPCODE_ISLT:
229 case TGSI_OPCODE_F2U:
230 case TGSI_OPCODE_U2F:
231 case TGSI_OPCODE_UADD:
232 case TGSI_OPCODE_UDIV:
233 case TGSI_OPCODE_UMAD:
234 case TGSI_OPCODE_UMAX:
235 case TGSI_OPCODE_UMIN:
236 case TGSI_OPCODE_UMOD:
237 case TGSI_OPCODE_UMUL:
238 case TGSI_OPCODE_USEQ:
239 case TGSI_OPCODE_USGE:
240 case TGSI_OPCODE_USHR:
241 case TGSI_OPCODE_USLT:
242 case TGSI_OPCODE_USNE:
243 case TGSI_OPCODE_IMUL_HI:
244 case TGSI_OPCODE_UMUL_HI:
245 case TGSI_OPCODE_DDX_FINE:
246 case TGSI_OPCODE_DDY_FINE:
247 /* Channel-wise operations */
248 read_mask = write_mask;
249 break;
250
251 case TGSI_OPCODE_EX2:
252 case TGSI_OPCODE_LG2:
253 read_mask = TGSI_WRITEMASK_X;
254 break;
255
256 case TGSI_OPCODE_SCS:
257 read_mask = write_mask & TGSI_WRITEMASK_XY ? TGSI_WRITEMASK_X : 0;
258 break;
259
260 case TGSI_OPCODE_EXP:
261 case TGSI_OPCODE_LOG:
262 read_mask = write_mask & TGSI_WRITEMASK_XYZ ? TGSI_WRITEMASK_X : 0;
263 break;
264
265 case TGSI_OPCODE_DP2:
266 read_mask = TGSI_WRITEMASK_XY;
267 break;
268
269 case TGSI_OPCODE_DP3:
270 read_mask = TGSI_WRITEMASK_XYZ;
271 break;
272
273 case TGSI_OPCODE_DP4:
274 read_mask = TGSI_WRITEMASK_XYZW;
275 break;
276
277 case TGSI_OPCODE_DPH:
278 read_mask = src_idx == 0 ? TGSI_WRITEMASK_XYZ : TGSI_WRITEMASK_XYZW;
279 break;
280
281 case TGSI_OPCODE_TEX:
282 case TGSI_OPCODE_TXD:
283 case TGSI_OPCODE_TXB:
284 case TGSI_OPCODE_TXL:
285 case TGSI_OPCODE_TXP:
286 if (src_idx == 0) {
287 /* Note that the SHADOW variants use the Z component too */
288 switch (inst->Texture.Texture) {
289 case TGSI_TEXTURE_1D:
290 read_mask = TGSI_WRITEMASK_X;
291 break;
292 case TGSI_TEXTURE_SHADOW1D:
293 read_mask = TGSI_WRITEMASK_XZ;
294 break;
295 case TGSI_TEXTURE_1D_ARRAY:
296 case TGSI_TEXTURE_2D:
297 case TGSI_TEXTURE_RECT:
298 read_mask = TGSI_WRITEMASK_XY;
299 break;
300 case TGSI_TEXTURE_SHADOW1D_ARRAY:
301 case TGSI_TEXTURE_SHADOW2D:
302 case TGSI_TEXTURE_SHADOWRECT:
303 case TGSI_TEXTURE_2D_ARRAY:
304 case TGSI_TEXTURE_3D:
305 case TGSI_TEXTURE_CUBE:
306 case TGSI_TEXTURE_2D_MSAA:
307 read_mask = TGSI_WRITEMASK_XYZ;
308 break;
309 case TGSI_TEXTURE_SHADOW2D_ARRAY:
310 case TGSI_TEXTURE_CUBE_ARRAY:
311 case TGSI_TEXTURE_SHADOWCUBE:
312 case TGSI_TEXTURE_2D_ARRAY_MSAA:
313 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
314 read_mask = TGSI_WRITEMASK_XYZW;
315 break;
316 default:
317 assert(0);
318 read_mask = 0;
319 }
320
321 if (inst->Instruction.Opcode != TGSI_OPCODE_TEX) {
322 read_mask |= TGSI_WRITEMASK_W;
323 }
324 } else {
325 /* A safe approximation */
326 read_mask = TGSI_WRITEMASK_XYZW;
327 }
328 break;
329
330 default:
331 /* Assume all channels are read */
332 read_mask = TGSI_WRITEMASK_XYZW;
333 break;
334 }
335
336 usage_mask = 0;
337 for (chan = 0; chan < 4; ++chan) {
338 if (read_mask & (1 << chan)) {
339 usage_mask |= 1 << tgsi_util_get_full_src_register_swizzle(src, chan);
340 }
341 }
342
343 return usage_mask;
344 }
345
346 /**
347 * Convert a tgsi_ind_register into a tgsi_src_register
348 */
349 struct tgsi_src_register
tgsi_util_get_src_from_ind(const struct tgsi_ind_register * reg)350 tgsi_util_get_src_from_ind(const struct tgsi_ind_register *reg)
351 {
352 struct tgsi_src_register src = { 0 };
353
354 src.File = reg->File;
355 src.Index = reg->Index;
356 src.SwizzleX = reg->Swizzle;
357 src.SwizzleY = reg->Swizzle;
358 src.SwizzleZ = reg->Swizzle;
359 src.SwizzleW = reg->Swizzle;
360
361 return src;
362 }
363
364 /**
365 * Return the dimension of the texture coordinates (layer included for array
366 * textures), as well as the location of the shadow reference value or the
367 * sample index.
368 */
369 int
tgsi_util_get_texture_coord_dim(int tgsi_tex,int * shadow_or_sample)370 tgsi_util_get_texture_coord_dim(int tgsi_tex, int *shadow_or_sample)
371 {
372 int dim;
373
374 /*
375 * Depending on the texture target, (src0.xyzw, src1.x) is interpreted
376 * differently:
377 *
378 * (s, X, X, X, X), for BUFFER
379 * (s, X, X, X, X), for 1D
380 * (s, t, X, X, X), for 2D, RECT
381 * (s, t, r, X, X), for 3D, CUBE
382 *
383 * (s, layer, X, X, X), for 1D_ARRAY
384 * (s, t, layer, X, X), for 2D_ARRAY
385 * (s, t, r, layer, X), for CUBE_ARRAY
386 *
387 * (s, X, shadow, X, X), for SHADOW1D
388 * (s, t, shadow, X, X), for SHADOW2D, SHADOWRECT
389 * (s, t, r, shadow, X), for SHADOWCUBE
390 *
391 * (s, layer, shadow, X, X), for SHADOW1D_ARRAY
392 * (s, t, layer, shadow, X), for SHADOW2D_ARRAY
393 * (s, t, r, layer, shadow), for SHADOWCUBE_ARRAY
394 *
395 * (s, t, sample, X, X), for 2D_MSAA
396 * (s, t, layer, sample, X), for 2D_ARRAY_MSAA
397 */
398 switch (tgsi_tex) {
399 case TGSI_TEXTURE_BUFFER:
400 case TGSI_TEXTURE_1D:
401 case TGSI_TEXTURE_SHADOW1D:
402 dim = 1;
403 break;
404 case TGSI_TEXTURE_2D:
405 case TGSI_TEXTURE_RECT:
406 case TGSI_TEXTURE_1D_ARRAY:
407 case TGSI_TEXTURE_SHADOW2D:
408 case TGSI_TEXTURE_SHADOWRECT:
409 case TGSI_TEXTURE_SHADOW1D_ARRAY:
410 case TGSI_TEXTURE_2D_MSAA:
411 dim = 2;
412 break;
413 case TGSI_TEXTURE_3D:
414 case TGSI_TEXTURE_CUBE:
415 case TGSI_TEXTURE_2D_ARRAY:
416 case TGSI_TEXTURE_SHADOWCUBE:
417 case TGSI_TEXTURE_SHADOW2D_ARRAY:
418 case TGSI_TEXTURE_2D_ARRAY_MSAA:
419 dim = 3;
420 break;
421 case TGSI_TEXTURE_CUBE_ARRAY:
422 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
423 dim = 4;
424 break;
425 default:
426 assert(!"unknown texture target");
427 dim = 0;
428 break;
429 }
430
431 if (shadow_or_sample) {
432 switch (tgsi_tex) {
433 case TGSI_TEXTURE_SHADOW1D:
434 /* there is a gap */
435 *shadow_or_sample = 2;
436 break;
437 case TGSI_TEXTURE_SHADOW2D:
438 case TGSI_TEXTURE_SHADOWRECT:
439 case TGSI_TEXTURE_SHADOWCUBE:
440 case TGSI_TEXTURE_SHADOW1D_ARRAY:
441 case TGSI_TEXTURE_SHADOW2D_ARRAY:
442 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
443 *shadow_or_sample = dim;
444 break;
445 case TGSI_TEXTURE_2D_MSAA:
446 case TGSI_TEXTURE_2D_ARRAY_MSAA:
447 *shadow_or_sample = 3;
448 break;
449 default:
450 /* no shadow nor sample */
451 *shadow_or_sample = -1;
452 break;
453 }
454 }
455
456 return dim;
457 }
458