Lines Matching refs:r2

21     and     r2, r0, #255                @ r2<- BB
23 GET_VREG r0, r2 @ r0<- vBB
85 mov r2, rINST, lsr #12 @ r2<- B
87 GET_VREG r0, r2 @ r0<- vB
121 and r2, r3, #255 @ r2<- BB
122 GET_VREG r0, r2 @ r0<- vBB
155 and r2, r0, #255 @ r2<- BB
158 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
160 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
161 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
163 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
195 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
198 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
272 $instr @ r0/r1<- op, r2-r3 changed
344 and r2, r0, #255 @ r2<- BB
346 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
348 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
349 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
350 cmp r0, r2
354 cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP
375 and r2, r0, #255 @ r2<- BB
377 GET_VREG r0, r2 @ r0<- vBB
434 mov r2, rINST, lsr #12 @ r2<- B
436 GET_VREG r0, r2 @ r0<- vB
464 and r2, r3, #255 @ r2<- BB
465 GET_VREG r0, r2 @ r0<- vBB
540 and r2, r0, #255 @ r2<- BB
542 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
544 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
545 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
546 mul ip, r2, r1 @ ip<- ZxW
547 umull r1, lr, r2, r0 @ r1/lr <- ZxX
548 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
550 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX))
555 SET_VREG_WIDE_BY_ADDR r1, r2 , r0 @ vAA/vAA+1<- r1/r2
572 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
574 mul ip, r2, r1 @ ip<- ZxW
575 umull r1, lr, r2, r0 @ r1/lr <- ZxX
576 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
579 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX))
581 SET_VREG_WIDE_BY_ADDR r1, r2, r0 @ vAA/vAA+1<- r1/r2
630 and r2, r0, #255 @ r2<- BB
632 GET_VREG r0, r2 @ r0<- vBB
638 sdiv r2, r0, r1
639 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed
670 sdiv r2, r0, r1
671 mls r1, r1, r2, r0 @ r1<- op
695 mov r2, rINST, lsr #12 @ r2<- B
697 GET_VREG r0, r2 @ r0<- vB
703 sdiv r2, r0, r1
704 mls r1, r1, r2, r0 @ r1<- op
728 and r2, r3, #255 @ r2<- BB
729 GET_VREG r0, r2 @ r0<- vBB
736 sdiv r2, r0, r1
737 mls r1, r1, r2, r0 @ r1<- op
783 GET_VREG r2, r0 @ r2<- vCC
786 and r2, r2, #63 @ r2<- r2 & 0x3f
788 mov r1, r1, asl r2 @ r1<- r1 << r2
789 rsb r3, r2, #32 @ r3<- 32 - r2
790 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
791 subs ip, r2, #32 @ ip<- r2 - 32
792 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
794 mov r0, r0, asl r2 @ r0<- r0 << r2
807 GET_VREG r2, r3 @ r2<- vB
810 and r2, r2, #63 @ r2<- r2 & 0x3f
812 mov r1, r1, asl r2 @ r1<- r1 << r2
813 rsb r3, r2, #32 @ r3<- 32 - r2
814 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
815 subs ip, r2, #32 @ ip<- r2 - 32
817 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
818 mov r0, r0, asl r2 @ r0<- r0 << r2
845 GET_VREG r2, r0 @ r2<- vCC
848 and r2, r2, #63 @ r0<- r0 & 0x3f
850 mov r0, r0, lsr r2 @ r0<- r2 >> r2
851 rsb r3, r2, #32 @ r3<- 32 - r2
852 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
853 subs ip, r2, #32 @ ip<- r2 - 32
854 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
856 mov r1, r1, asr r2 @ r1<- r1 >> r2
869 GET_VREG r2, r3 @ r2<- vB
872 and r2, r2, #63 @ r2<- r2 & 0x3f
874 mov r0, r0, lsr r2 @ r0<- r2 >> r2
875 rsb r3, r2, #32 @ r3<- 32 - r2
876 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
877 subs ip, r2, #32 @ ip<- r2 - 32
879 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
880 mov r1, r1, asr r2 @ r1<- r1 >> r2
919 GET_VREG r2, r0 @ r2<- vCC
922 and r2, r2, #63 @ r0<- r0 & 0x3f
924 mov r0, r0, lsr r2 @ r0<- r2 >> r2
925 rsb r3, r2, #32 @ r3<- 32 - r2
926 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
927 subs ip, r2, #32 @ ip<- r2 - 32
928 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
930 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
943 GET_VREG r2, r3 @ r2<- vB
946 and r2, r2, #63 @ r2<- r2 & 0x3f
948 mov r0, r0, lsr r2 @ r0<- r2 >> r2
949 rsb r3, r2, #32 @ r3<- 32 - r2
950 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
951 subs ip, r2, #32 @ ip<- r2 - 32
953 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
954 mov r1, r1, lsr r2 @ r1<- r1 >>> r2