1 /*******************************************************************************
2 * Copyright (C) 2018 Cadence Design Systems, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to use this Software with Cadence processor cores only and
7 * not with any other processors and platforms, subject to
8 * the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included
11 * in all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 
21 ******************************************************************************/
22 
23 
24 #include <xtensa/coreasm.h>
25 #include <xtensa/simcall.h>
26 #define PIF_CACHED  1
27 #define PIF_BYPASS  2
28 #define PIF_CACHED_WBA   4
29 #define PIF_CACHED_WBNA  5
30 #define PIF_INVALID 15
31 
32 #ifdef __cplusplus
33 #if __cplusplus
34 extern "C" {
35 #endif
36 #endif
37 
38 
39 
40 /*set memory mapping attribute*/
41 .macro set_access_mode am
42     rdtlb1 a4, a3
43     ritlb1 a5, a3
44     srli a4, a4, 4
45     slli a4, a4, 4
46     srli a5, a5, 4
47     slli a5, a5, 4
48     addi a4, a4, \am
49     addi a5, a5, \am
50     wdtlb a4, a3
51     witlb a5, a3
52 .endm
53 
54 
55 
56 
57 #ifdef __cplusplus
58     #if __cplusplus
59         }
60     #endif
61 #endif
62 
63