1 /* 2 * Copyright (C) 2010-2019 NXP Semiconductors 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef _PHNXPNCIHAL_H_ 17 #define _PHNXPNCIHAL_H_ 18 19 #include <hardware/nfc.h> 20 #include <phNxpNciHal_utils.h> 21 #include "NxpMfcReader.h" 22 #include "NxpNfcCapability.h" 23 24 /********************* Definitions and structures *****************************/ 25 #define MAX_RETRY_COUNT 5 26 #define NCI_MAX_DATA_LEN 300 27 #define NCI_POLL_DURATION 500 28 #define HAL_NFC_ENABLE_I2C_FRAGMENTATION_EVT 0x07 29 #undef P2P_PRIO_LOGIC_HAL_IMP 30 #define NCI_VERSION_2_0 0x20 31 #define NCI_VERSION_1_1 0x11 32 #define NCI_VERSION_1_0 0x10 33 #define NCI_VERSION_UNKNOWN 0x00 34 typedef void(phNxpNciHal_control_granted_callback_t)(); 35 36 /*ROM CODE VERSION FW*/ 37 #define FW_MOBILE_ROM_VERSION_PN551 0x10 38 #define FW_MOBILE_ROM_VERSION_PN553 0x11 39 #define FW_MOBILE_ROM_VERSION_PN557 0x12 40 /* NCI Data */ 41 42 #define NCI_MT_CMD 0x20 43 #define NCI_MT_RSP 0x40 44 #define NCI_MT_NTF 0x60 45 46 #define CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED 0x02 47 #define CORE_RESET_TRIGGER_TYPE_POWERED_ON 0x01 48 #define NCI_MSG_CORE_RESET 0x00 49 #define NCI_MSG_CORE_INIT 0x01 50 #define NCI_MT_MASK 0xE0 51 #define NCI_OID_MASK 0x3F 52 53 #define NXP_MAX_CONFIG_STRING_LEN 260 54 #define NCI_HEADER_SIZE 3 55 56 typedef struct nci_data { 57 uint16_t len; 58 uint8_t p_data[NCI_MAX_DATA_LEN]; 59 } nci_data_t; 60 61 typedef enum { 62 HAL_STATUS_CLOSE = 0, 63 HAL_STATUS_OPEN, 64 HAL_STATUS_MIN_OPEN 65 } phNxpNci_HalStatus; 66 67 typedef enum { 68 GPIO_UNKNOWN = 0x00, 69 GPIO_STORE = 0x01, 70 GPIO_STORE_DONE = 0x02, 71 GPIO_RESTORE = 0x10, 72 GPIO_RESTORE_DONE = 0x20, 73 GPIO_CLEAR = 0xFF 74 } phNxpNciHal_GpioInfoState; 75 76 typedef struct phNxpNciGpioInfo { 77 phNxpNciHal_GpioInfoState state; 78 uint8_t values[2]; 79 } phNxpNciGpioInfo_t; 80 81 /* Macros to enable and disable extensions */ 82 #define HAL_ENABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 1) 83 #define HAL_DISABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 0) 84 typedef struct phNxpNciInfo { 85 uint8_t nci_version; 86 bool_t wait_for_ntf; 87 } phNxpNciInfo_t; 88 /* NCI Control structure */ 89 typedef struct phNxpNciHal_Control { 90 phNxpNci_HalStatus halStatus; /* Indicate if hal is open or closed */ 91 pthread_t client_thread; /* Integration thread handle */ 92 uint8_t thread_running; /* Thread running if set to 1, else set to 0 */ 93 phLibNfc_sConfig_t gDrvCfg; /* Driver config data */ 94 95 /* Rx data */ 96 uint8_t* p_rx_data; 97 uint16_t rx_data_len; 98 99 /* Rx data */ 100 uint8_t* p_rx_ese_data; 101 uint16_t rx_ese_data_len; 102 103 /* libnfc-nci callbacks */ 104 nfc_stack_callback_t* p_nfc_stack_cback; 105 nfc_stack_data_callback_t* p_nfc_stack_data_cback; 106 107 /* control granted callback */ 108 phNxpNciHal_control_granted_callback_t* p_control_granted_cback; 109 110 /* HAL open status */ 111 bool_t hal_open_status; 112 113 /* HAL extensions */ 114 uint8_t hal_ext_enabled; 115 116 /* Waiting semaphore */ 117 phNxpNciHal_Sem_t ext_cb_data; 118 sem_t syncSpiNfc; 119 120 uint16_t cmd_len; 121 uint8_t p_cmd_data[NCI_MAX_DATA_LEN]; 122 uint16_t rsp_len; 123 uint8_t p_rsp_data[NCI_MAX_DATA_LEN]; 124 125 /* retry count used to force download */ 126 uint16_t retry_cnt; 127 uint8_t read_retry_cnt; 128 phNxpNciInfo_t nci_info; 129 130 /* to store and restore gpio values */ 131 phNxpNciGpioInfo_t phNxpNciGpioInfo; 132 } phNxpNciHal_Control_t; 133 134 typedef struct phNxpNciClock { 135 bool_t isClockSet; 136 uint8_t p_rx_data[20]; 137 bool_t issetConfig; 138 } phNxpNciClock_t; 139 140 typedef struct phNxpNciRfSetting { 141 bool_t isGetRfSetting; 142 uint8_t p_rx_data[20]; 143 } phNxpNciRfSetting_t; 144 145 typedef struct phNxpNciMwEepromArea { 146 bool_t isGetEepromArea; 147 uint8_t p_rx_data[32]; 148 } phNxpNciMwEepromArea_t; 149 150 typedef enum { 151 NFC_FORUM_PROFILE, 152 EMV_CO_PROFILE, 153 INVALID_PROFILe 154 } phNxpNciProfile_t; 155 /* NXP Poll Profile control structure */ 156 typedef struct phNxpNciProfile_Control { 157 phNxpNciProfile_t profile_type; 158 uint8_t bClkSrcVal; /* Holds the System clock source read from config file */ 159 uint8_t 160 bClkFreqVal; /* Holds the System clock frequency read from config file */ 161 uint8_t bTimeout; /* Holds the Timeout Value */ 162 } phNxpNciProfile_Control_t; 163 164 /* Internal messages to handle callbacks */ 165 #define NCI_HAL_OPEN_CPLT_MSG 0x411 166 #define NCI_HAL_CLOSE_CPLT_MSG 0x412 167 #define NCI_HAL_POST_INIT_CPLT_MSG 0x413 168 #define NCI_HAL_PRE_DISCOVER_CPLT_MSG 0x414 169 #define NCI_HAL_ERROR_MSG 0x415 170 #define NCI_HAL_HCI_NETWORK_RESET_MSG 0x416 171 #define NCI_HAL_RX_MSG 0xF01 172 173 #define NCIHAL_CMD_CODE_LEN_BYTE_OFFSET (2U) 174 #define NCIHAL_CMD_CODE_BYTE_LEN (3U) 175 176 /******************** NCI HAL exposed functions *******************************/ 177 int phNxpNciHal_check_ncicmd_write_window(uint16_t cmd_len, uint8_t* p_cmd); 178 void phNxpNciHal_request_control(void); 179 void phNxpNciHal_release_control(void); 180 int phNxpNciHal_write_unlocked(uint16_t data_len, const uint8_t* p_data); 181 /******************************************************************************* 182 ** 183 ** Function phNxpNciHal_configFeatureList 184 ** 185 ** Description Configures the featureList based on chip type 186 187 ** Returns none 188 *******************************************************************************/ 189 void phNxpNciHal_configFeatureList(uint8_t* init_rsp, uint16_t rsp_len); 190 #endif /* _PHNXPNCIHAL_H_ */ 191