| /art/libelffile/dwarf/ |
| D | register.h | 24 class Reg {
26 explicit Reg(int reg_num) : num_(reg_num) { } in Reg() function
38 static Reg ArmCore(int num) { return Reg(num); } // R0-R15. in ArmCore()
39 static Reg ArmFp(int num) { return Reg(64 + num); } // S0–S31. in ArmFp()
40 static Reg ArmDp(int num) { return Reg(256 + num); } // D0–D31. in ArmDp()
41 static Reg Arm64Core(int num) { return Reg(num); } // X0-X31. in Arm64Core()
42 static Reg Arm64Fp(int num) { return Reg(64 + num); } // V0-V31. in Arm64Fp()
43 static Reg Riscv64Core(int num) { return Reg(num); } // X0-X31 in Riscv64Core()
44 static Reg Riscv64Fp(int num) { return Reg(32 + num); } // F0-F31 in Riscv64Fp()
45 static Reg X86Core(int num) { return Reg(num); } in X86Core()
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| D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
83 void ALWAYS_INLINE RelOffsetForMany(Reg reg_base, in RelOffsetForMany()
94 RelOffset(Reg(reg_base.num() + i), offset); in RelOffsetForMany()
101 void ALWAYS_INLINE RestoreMany(Reg reg_base, uint32_t reg_mask) { in RestoreMany()
108 Restore(Reg(reg_base.num() + i)); in RestoreMany()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
153 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
161 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
170 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
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| D | headers.h | 42 Reg return_address_register, in WriteCIE()
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| /art/compiler/debug/ |
| D | elf_debug_frame_writer.h | 40 using Reg = dwarf::Reg; in WriteCIE() local
48 opcodes.DefCFA(Reg::ArmCore(13), 0); // R13(SP). in WriteCIE()
52 opcodes.Undefined(Reg::ArmCore(reg)); in WriteCIE()
54 opcodes.SameValue(Reg::ArmCore(reg)); in WriteCIE()
60 opcodes.Undefined(Reg::ArmFp(reg)); in WriteCIE()
62 opcodes.SameValue(Reg::ArmFp(reg)); in WriteCIE()
65 auto return_reg = Reg::ArmCore(14); // R14(LR). in WriteCIE()
71 opcodes.DefCFA(Reg::Arm64Core(31), 0); // R31(SP). in WriteCIE()
75 opcodes.Undefined(Reg::Arm64Core(reg)); in WriteCIE()
77 opcodes.SameValue(Reg::Arm64Core(reg)); in WriteCIE()
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| D | elf_debug_loc_writer.h | 32 using Reg = dwarf::Reg; variable
34 static Reg GetDwarfCoreReg(InstructionSet isa, int machine_reg) { in GetDwarfCoreReg()
38 return Reg::ArmCore(machine_reg); in GetDwarfCoreReg()
40 return Reg::Arm64Core(machine_reg); in GetDwarfCoreReg()
42 return Reg::Riscv64Core(machine_reg); in GetDwarfCoreReg()
44 return Reg::X86Core(machine_reg); in GetDwarfCoreReg()
46 return Reg::X86_64Core(machine_reg); in GetDwarfCoreReg()
53 static Reg GetDwarfFpReg(InstructionSet isa, int machine_reg) { in GetDwarfFpReg()
57 return Reg::ArmFp(machine_reg); in GetDwarfFpReg()
59 return Reg::Arm64Fp(machine_reg); in GetDwarfFpReg()
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| /art/compiler/utils/ |
| D | assembler_test.h | 54 typename Reg,
79 std::string RepeatR(void (Ass::*f)(Reg), const std::string& fmt) { in RepeatR() argument
80 return RepeatTemplatedRegister<Reg>(f, in RepeatR()
86 std::string Repeatr(void (Ass::*f)(Reg), const std::string& fmt) { in Repeatr() argument
87 return RepeatTemplatedRegister<Reg>(f, in Repeatr()
93 std::string RepeatRR(void (Ass::*f)(Reg, Reg),
95 const std::vector<std::pair<Reg, Reg>>* except = nullptr) {
96 return RepeatTemplatedRegisters<Reg, Reg>(f,
105 std::string RepeatRRNoDupes(void (Ass::*f)(Reg, Reg), const std::string& fmt) { in RepeatRRNoDupes() argument
106 return RepeatTemplatedRegistersNoDupes<Reg, Reg>(f, in RepeatRRNoDupes()
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| /art/compiler/debug/dwarf/ |
| D | dwarf_test.cc | 39 const Reg reg(6); in TEST_F()
77 opcodes.Offset(Reg(0x3F), -offset); in TEST_F()
79 opcodes.Offset(Reg(0x40), -offset); in TEST_F()
81 opcodes.Offset(Reg(0x40), offset); in TEST_F()
87 opcodes.Register(reg, Reg(1)); in TEST_F()
93 opcodes.Restore(Reg(0x3F)); in TEST_F()
95 opcodes.Restore(Reg(0x40)); in TEST_F()
107 opcodes.DefCFA(Reg(4), 100); // ESP in TEST_F()
111 opcodes.RelOffset(Reg(0), 0); // push R0 in TEST_F()
113 opcodes.RelOffset(Reg(1), 4); // push R1 in TEST_F()
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.h | 46 static inline dwarf::Reg DWARFReg(vixl::aarch64::CPURegister reg) { in DWARFReg()
48 return dwarf::Reg::Arm64Fp(reg.GetCode()); in DWARFReg()
51 return dwarf::Reg::Arm64Core(reg.GetCode()); in DWARFReg()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 40 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
41 return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode())); in DWARFReg()
44 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg()
45 return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode())); in DWARFReg()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.h | 391 template <typename Reg,
392 void (Riscv64Assembler::*opS)(Reg, FRegister, FRegister),
393 void (Riscv64Assembler::*opD)(Reg, FRegister, FRegister)>
394 void FpBinOp(Reg rd, FRegister rs1, FRegister rs2, DataType::Type type);
404 template <typename Reg,
405 void (Riscv64Assembler::*opS)(Reg, FRegister),
406 void (Riscv64Assembler::*opD)(Reg, FRegister)>
407 void FpUnOp(Reg rd, FRegister rs1, DataType::Type type);
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| D | code_generator_riscv64.cc | 793 template <typename Reg,
794 void (Riscv64Assembler::*opS)(Reg, FRegister, FRegister),
795 void (Riscv64Assembler::*opD)(Reg, FRegister, FRegister)>
797 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp()
852 template <typename Reg,
853 void (Riscv64Assembler::*opS)(Reg, FRegister),
854 void (Riscv64Assembler::*opD)(Reg, FRegister)>
856 Reg rd, FRegister rs1, DataType::Type type) { in FpUnOp()
6033 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(reg), offset); in GenerateFrameEntry()
6043 __ cfi().RelOffset(dwarf::Reg::Riscv64Fp(reg), offset); in GenerateFrameEntry()
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| D | code_generator_x86_64.cc | 1649 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
1650 return dwarf::Reg::X86_64Core(static_cast<int>(reg)); in DWARFReg()
1653 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg()
1654 return dwarf::Reg::X86_64Fp(static_cast<int>(reg)); in DWARFReg()
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| D | code_generator_x86.cc | 1204 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
1205 return dwarf::Reg::X86Core(static_cast<int>(reg)); in DWARFReg()
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| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64.cc | 78 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(RA), offset); in BuildFrame()
83 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(enum_cast<XRegister>(reg)), offset); in BuildFrame()
88 __ cfi().RelOffset(dwarf::Reg::Riscv64Fp(enum_cast<FRegister>(reg)), offset); in BuildFrame()
108 __ cfi().Restore(dwarf::Reg::Riscv64Fp(enum_cast<FRegister>(reg))); in RemoveFrame()
113 __ cfi().Restore(dwarf::Reg::Riscv64Core(enum_cast<XRegister>(reg))); in RemoveFrame()
118 __ cfi().Restore(dwarf::Reg::Riscv64Core(RA)); in RemoveFrame()
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| D | assembler_riscv64.h | 1873 template <typename Reg>
1874 static inline bool IsShortReg(Reg reg) { in IsShortReg()
1875 static_assert(std::is_same_v<Reg, XRegister> || std::is_same_v<Reg, FRegister>); in IsShortReg()
2243 template <typename Reg>
2244 static constexpr uint32_t EncodeShortReg(const Reg reg) { in EncodeShortReg()
2519 template <typename Reg>
2520 void EmitCI(uint32_t funct3, Reg rd_rs1, uint32_t imm6, uint32_t opcode) { in EmitCI()
2542 template <typename Reg>
2543 void EmitCSS(uint32_t funct3, uint32_t offset6, Reg rs2, uint32_t opcode) { in EmitCSS()
2579 template <typename Reg>
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| D | assembler_riscv64_test.cc | 1095 template <typename Reg, typename Imm>
1096 std::string RepeatCTemplateRegImm(void (Riscv64Assembler::*f)(Reg, Imm), in RepeatCTemplateRegImm() argument
1097 ArrayRef<const Reg> registers, in RepeatCTemplateRegImm()
1098 std::string (Base::*GetName)(const Reg&), in RepeatCTemplateRegImm() argument
1107 for (Reg reg : registers) { in RepeatCTemplateRegImm()
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| /art/compiler/ |
| D | cfi_test.h | 52 dwarf::WriteCIE(is64bit, dwarf::Reg(8), initial_opcodes, &debug_frame_data_); in GenerateExpected()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 29 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
30 return dwarf::Reg::X86_64Core(static_cast<int>(reg)); in DWARFReg()
32 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg()
33 return dwarf::Reg::X86_64Fp(static_cast<int>(reg)); in DWARFReg()
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 35 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
36 return dwarf::Reg::X86Core(static_cast<int>(reg)); in DWARFReg()
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