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/art/test/593-checker-boolean-2-integral-conv/smali/
DSmaliTests.smali35 ## CHECK-DAG: <<Zero:i\d+>> IntConstant 0
37 ## CHECK-DAG: <<Cond:z\d+>> Equal [<<Arg>>,<<Zero>>]
39 ## CHECK-DAG: <<Phi:i\d+>> Phi [<<One>>,<<Zero>>]
45 ## CHECK-DAG: <<Zero:i\d+>> IntConstant 0
47 ## CHECK-DAG: <<Sel:i\d+>> Select [<<Zero>>,<<One>>,<<Arg>>]
70 ## CHECK-DAG: <<Zero:i\d+>> IntConstant 0
72 ## CHECK-DAG: <<Cond:z\d+>> Equal [<<Arg>>,<<Zero>>]
74 ## CHECK-DAG: <<Phi:i\d+>> Phi [<<One>>,<<Zero>>]
80 ## CHECK-DAG: <<Zero:i\d+>> IntConstant 0
82 ## CHECK-DAG: <<Sel:i\d+>> Select [<<Zero>>,<<One>>,<<Arg>>]
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/art/compiler/utils/riscv64/
Dmanaged_register_riscv64_test.cc31 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromXRegister(Zero); in TEST()
35 EXPECT_EQ(Zero, reg.AsXRegister()); in TEST()
152 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
158 Riscv64ManagedRegister reg_Zero = Riscv64ManagedRegister::FromXRegister(Zero); in TEST()
160 EXPECT_TRUE(reg_Zero.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
168 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
177 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
186 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
195 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromXRegister(Zero))); in TEST()
Dassembler_riscv64.cc73 if (rd != Zero && rd != SP && IsImmCLuiEncodable(imm20)) { in Lui()
90 if (rd == Zero && IsInt<12>(offset)) { in Jal()
102 if (rd == RA && rs1 != Zero && offset == 0) { in Jalr()
105 } else if (rd == Zero && rs1 != Zero && offset == 0) { in Jalr()
118 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Beq()
121 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Beq()
132 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Bne()
135 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Bne()
184 if (rd != Zero && rs1 == SP && IsUint<8>(offset) && IsAligned<4>(offset)) { in Lw()
200 if (rd != Zero && rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) { in Ld()
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Dassembler_riscv64_test.cc164 secondary_register_names_.emplace(Zero, "zero"); in SetUpHelpers()
210 Zero, in GetRegisters()
694 std::string temp_name = (rd != Zero) ? rd_name : GetRegisterName(TMP); in GetPrintCallRd()
1000 if (reg != Zero) { in TestLoadLiteral()
1137 CHECK_EQ(regs[0], Zero); in RepeatCRImm()
1228 CHECK_EQ(regs[0], Zero); in RepeatCRRNonZero()
1270 CHECK_EQ(regs[0], Zero); in RepeatRNoZero()
3514 if (reg == Zero || reg == SP) { in TEST_F()
8566 Zero); in TEST_F()
8575 Zero); in TEST_F()
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Djni_macro_assembler_riscv64.cc486 __ Stored(Zero, TR, thread_held_mutex_mutator_lock_offset.Int32Value()); in TryToTransitionFromRunnableToNative()
521 __ ScW(scratch, Zero, TR, AqRl::kNone); in TryToTransitionFromNativeToRunnable()
/art/runtime/interpreter/mterp/armng/
Dother.S95 CLEAR_SHADOW_PAIR r4, r2, r3 @ Zero out the shadow regs
108 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
121 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
135 CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs
256 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
270 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
285 CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs
298 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
Darithmetic.S166 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
201 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
269 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
292 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
556 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
790 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
814 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
854 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
878 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
930 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
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Darray.S21 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
/art/runtime/arch/riscv64/
Dregisters_riscv64.cc40 if (rhs >= Zero && rhs < kNumberOfXRegisters) { in operator <<()
Dcontext_riscv64.cc68 DCHECK_NE(reg, static_cast<uint32_t>(Zero)); // Zero/X0 is immutable (hard-wired zero) in SetGPR()
83 gprs_[Zero] = const_cast<uint64_t*>(&gZero); // hard-wired zero in SmashCallerSaves()
Dregisters_riscv64.h28 Zero = 0, // X0, hard-wired zero enumerator
/art/disassembler/
Ddisassembler_riscv64.cc44 Zero = 0, enumerator
390 os_ << (rd == Zero ? "j " : "jal "); in Print32Jal()
391 if (rd != Zero && rd != RA) { in Print32Jal()
415 if (rd == Zero && rs1 == RA && imm12 == 0) { in Print32Jalr()
417 } else if (rd == Zero && imm12 == 0) { in Print32Jalr()
449 if (rs2 == Zero) { in Print32BCond()
451 } else if (rs1 == Zero && (funct3 == 4u || funct3 == 5u)) { in Print32BCond()
719 } else if (rd == Zero && rs1 == Zero) { in Print32BinOpImm()
781 if (high_bits == 0x40000000u && funct3 == /*SUB*/ 0u && rs1 == Zero) { in Print32BinOp()
783 } else if (!narrow && funct3 == /*SLT*/ 2u && rs2 == Zero) { in Print32BinOp()
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/art/test/647-sinking-catch/smali/
DTestCase.smali22 const-string v1, "Zero"
/art/runtime/verifier/
Dreg_type_cache.h104 const ConstantType& Zero() REQUIRES_SHARED(Locks::mutator_lock_) { in Zero() function
Dreg_type_cache.cc324 left_resolved = &Zero(); in FromUnresolvedMerge()
341 right_resolved = &Zero(); in FromUnresolvedMerge()
Dreg_type.cc336 return cache->Zero(); in GetSuperClass()
Dreg_type_test.cc766 const RegType& zero = cache.Zero(); in TEST_F()
Dmethod_verifier.cc4878 return reg_types_.Zero(); in DetermineCat1Constant()
/art/compiler/optimizing/
Dcode_generator_riscv64.cc88 return Zero; in InputXRegisterOrZero()
1003 __ AmoSwapD(Zero, swap_src, addr, AqRl::kRelease); in StoreSeqCst()
1005 __ AmoSwapW(Zero, swap_src, addr, AqRl::kRelease); in StoreSeqCst()
1441 __ Mv(out, Zero); in DivRemOneOrMinusOne()
1445 __ Subw(out, Zero, dividend); in DivRemOneOrMinusOne()
1448 __ Sub(out, Zero, dividend); in DivRemOneOrMinusOne()
2204 __ Min(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
2208 __ Max(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
3453 __ Stored(Zero, TR, GetExceptionTlsOffset()); in VisitClearException()
3907 __ Mv(out, Zero); in VisitInstanceOf()
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Dintrinsics_riscv64.cc1201 __ Bgt(temp, Zero, &loop); in VisitStringEquals()
3831 return Zero; in PrepareXRegister()
4741 __ Storew(Zero, TR, Thread::InterruptedOffset<kRiscv64PointerSize>().Int32Value()); in VisitThreadInterrupted()