/art/runtime/arch/arm64/ |
D | memcmp16_arm64.S | 52 lsl limit, limit, #1 /* Half-words to bytes. */ 78 lsl limit, limit, #3 /* Bits -> bytes. */ 80 lsl mask, mask, limit 112 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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D | quick_entrypoints_arm64.S | 1026 str w2, [x3, x1, lsl #2] // Heap reference = 32b. 1034 str w2, [x3, x1, lsl #2] // Heap reference = 32b. 1057 str w2, [x3, x1, lsl #2] // Heap reference = 32b. 1485 lsl \xTemp1, \xCount, \xTemp0 // Calculate data size 1507 lsl \xTemp1, \xCount, #1 1514 lsl \xTemp1, \xCount, #2 1521 lsl \xTemp1, \xCount, #3 1913 add x0, x0, x2, lsl #1 2034 tst wIP0, wIP0, lsl #1 2109 lsl \wreg, wIP0, #LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT [all …]
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/art/runtime/interpreter/mterp/arm64ng/ |
D | other.S | 10 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 37 lsl w0, w0, #16 // r0<- BBBB0000 94 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 95 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb 96 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb 116 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb 125 lsl x0, x0, #48
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D | control_flow.S | 78 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa 131 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb 133 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2
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D | main.S | 177 add \reg, xIBASE, \reg, lsl #${handler_size_bits} 211 and \scaled_vreg, \scaled_mask_reg, \src_reg, lsl #(2 - \lsb) 220 lsl wip2, \vreg, #2 228 lsl wip2, \vreg, #2 399 lsl x14, x14, #2 408 add \refs, x14, ip2, lsl #2 411 add \fp, \refs, ip, lsl #2 647 add ip2, xREFS, x3, lsl #2 // pointer to first argument in reference array 648 add ip2, ip2, x2, lsl #2 // pointer to last argument in reference array 649 add x5, xFP, x3, lsl #2 // pointer to first argument in register array [all …]
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D | array.S | 134 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb 136 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 (array data off.)
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/art/runtime/interpreter/mterp/armng/ |
D | main.S | 182 add pc, rIBASE, \reg, lsl #${handler_size_bits} 189 ldr \reg, [rFP, \vreg, lsl #2] 192 ldr \reg, [rREFS, \vreg, lsl #2] 195 str \reg, [rFP, \vreg, lsl #2] 197 str \reg, [rREFS, \vreg, lsl #2] 200 str \reg, [rFP, \vreg, lsl #2] 201 str \reg, [rREFS, \vreg, lsl #2] 204 add \tmpreg, rFP, \vreg, lsl #2 207 str \tmpreg, [rREFS, \vreg, lsl #2] 216 ldr \vreg, [rFP, \vreg, lsl #2] [all …]
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D | control_flow.S | 78 orrs rINST, r0, r1, lsl #16 // wINST<- AAAAaaaa 131 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 133 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
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D | invoke.S | 99 ldr r0, [r2, r3, lsl #2] 115 ldr r0, [r2, r4, lsl #2] 168 ldr r0, [r0, r2, lsl #2]
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D | array.S | 16 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width 87 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width 94 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width 141 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 143 add r0, rPC, r0, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
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D | other.S | 10 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 37 mov r0, r0, lsl #16 @ r0<- BBBB0000 91 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 94 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 120 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 133 mov r1, r1, lsl #16 @ r1<- BBBB0000
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D | arithmetic.S | 859 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2)) 884 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2)) 935 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2)) 960 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
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/art/runtime/arch/arm/ |
D | memcmp16_arm.S | 189 orr ip, ip, lr, lsl #16 194 orreq ip, ip, lr, lsl #16 199 orreq ip, ip, lr, lsl #16 204 orreq ip, ip, lr, lsl #16
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D | quick_entrypoints_arm.S | 741 str r2, [r3, r1, lsl #2] 749 str r2, [r3, r1, lsl #2] 766 str r2, [r3, r1, lsl #2] 1179 lsl r2, r1, r3 // Calculate data size 1209 lsl r2, r1, #1 1220 lsl r2, r1, #2 1231 lsl r2, r1, #3 1637 add r0, r0, r2, lsl #1 1899 lsl \reg, ip, #LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT 1957 ldr ip, [ip, \index_reg, lsl #2] // 4 bytes. [all …]
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/art/compiler/optimizing/ |
D | code_generator_arm_vixl.cc | 5529 __ lsl(pl, o_h, low, temp); in HandleShift() local
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