D | assembler_riscv64.cc | 867 void Riscv64Assembler::Csrrwi(XRegister rd, uint32_t csr, uint32_t uimm5) { in Csrrwi() argument 869 EmitI(ToInt12(csr), uimm5, 0x5, rd, 0x73); in Csrrwi() 872 void Riscv64Assembler::Csrrsi(XRegister rd, uint32_t csr, uint32_t uimm5) { in Csrrsi() argument 874 EmitI(ToInt12(csr), uimm5, 0x6, rd, 0x73); in Csrrsi() 877 void Riscv64Assembler::Csrrci(XRegister rd, uint32_t csr, uint32_t uimm5) { in Csrrci() argument 879 EmitI(ToInt12(csr), uimm5, 0x7, rd, 0x73); in Csrrci() 3980 void Riscv64Assembler::VRgather_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VRgather_vi() argument 3985 EmitR(funct7, vs2, uimm5, enum_cast<uint32_t>(VAIEncoding::kOPIVI), vd, 0x57); in VRgather_vi() 3996 void Riscv64Assembler::VSlideup_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSlideup_vi() argument 4001 EmitR(funct7, vs2, uimm5, enum_cast<uint32_t>(VAIEncoding::kOPIVI), vd, 0x57); in VSlideup_vi() [all …]
|