1 /*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "disassembler_arm64.h"
18
19 #include <inttypes.h>
20
21 #include <regex>
22
23 #include <sstream>
24
25 #include "android-base/logging.h"
26 #include "android-base/stringprintf.h"
27
28 using android::base::StringPrintf;
29
30 using namespace vixl::aarch64; // NOLINT(build/namespaces)
31
32 namespace art {
33 namespace arm64 {
34
35 // This enumeration should mirror the declarations in
36 // runtime/arch/arm64/registers_arm64.h. We do not include that file to
37 // avoid a dependency on libart.
38 enum {
39 TR = 19,
40 IP0 = 16,
41 IP1 = 17,
42 FP = 29,
43 LR = 30
44 };
45
AppendRegisterNameToOutput(const Instruction * instr,const CPURegister & reg)46 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
47 const CPURegister& reg) {
48 USE(instr);
49 if (reg.IsRegister() && reg.Is64Bits()) {
50 if (reg.GetCode() == TR) {
51 AppendToOutput("tr");
52 return;
53 } else if (reg.GetCode() == LR) {
54 AppendToOutput("lr");
55 return;
56 }
57 // Fall through.
58 }
59 // Print other register names as usual.
60 Disassembler::AppendRegisterNameToOutput(instr, reg);
61 }
62
Visit(vixl::aarch64::Metadata * metadata,const Instruction * instr)63 void CustomDisassembler::Visit(vixl::aarch64::Metadata* metadata, const Instruction* instr) {
64 vixl::aarch64::Disassembler::Visit(metadata, instr);
65 const std::string& form = (*metadata)["form"];
66
67 // These regexs are long, but it is an attempt to match the mapping entry keys in the
68 // #define DEFAULT_FORM_TO_VISITOR_MAP(VISITORCLASS) in the file
69 // external/vixl/src/aarch64/decoder-visitor-map-aarch64.h
70 // for the ::VisitLoadLiteralInstr, ::VisitLoadStoreUnsignedOffset or ::VisitUnconditionalBranch
71 // function addresess key values.
72 // N.B. the mapping are many to one.
73 if (std::regex_match(form, std::regex("(ldrsw|ldr|prfm)_(32|64|d|b|h|q|s)_loadlit"))) {
74 VisitLoadLiteralInstr(instr);
75 return;
76 }
77
78 if (std::regex_match(form, std::regex(
79 "(ldrb|ldrh|ldrsb|ldrsh|ldrsw|ldr|prfm|strb|strh|str)_(32|64|d|b|h|q|s)_ldst_pos"))) {
80 VisitLoadStoreUnsignedOffsetInstr(instr);
81 return;
82 }
83
84 if (std::regex_match(form, std::regex("(bl|b)_only_branch_imm"))) {
85 VisitUnconditionalBranchInstr(instr);
86 return;
87 }
88 }
89
VisitLoadLiteralInstr(const Instruction * instr)90 void CustomDisassembler::VisitLoadLiteralInstr(const Instruction* instr) {
91 if (!read_literals_) {
92 return;
93 }
94
95 // Get address of literal. Bail if not within expected buffer range to
96 // avoid trying to fetch invalid literals (we can encounter this when
97 // interpreting raw data as instructions).
98 void* data_address = instr->GetLiteralAddress<void*>();
99
100 if (data_address < base_address_ || data_address >= end_address_) {
101 AppendToOutput(" (?)");
102 return;
103 }
104
105 // Output information on literal.
106 Instr op = instr->Mask(LoadLiteralMask);
107 switch (op) {
108 case LDR_w_lit:
109 case LDR_x_lit:
110 case LDRSW_x_lit: {
111 int64_t data = op == LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
112 : *reinterpret_cast<int32_t*>(data_address);
113 AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data);
114 break;
115 }
116 case LDR_s_lit:
117 case LDR_d_lit: {
118 double data = (op == LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
119 : *reinterpret_cast<double*>(data_address);
120 AppendToOutput(" (%g)", data);
121 break;
122 }
123 default:
124 break;
125 }
126 }
127
VisitLoadStoreUnsignedOffsetInstr(const Instruction * instr)128 void CustomDisassembler::VisitLoadStoreUnsignedOffsetInstr(const Instruction* instr) {
129 if (instr->GetRn() == TR) {
130 AppendThreadOfsetName(instr);
131 }
132 }
133
VisitUnconditionalBranchInstr(const Instruction * instr)134 void CustomDisassembler::VisitUnconditionalBranchInstr(const Instruction* instr) {
135 if (instr->Mask(UnconditionalBranchMask) == BL) {
136 const Instruction* target = instr->GetImmPCOffsetTarget();
137 if (target >= base_address_ &&
138 target < end_address_ &&
139 target->Mask(LoadStoreMask) == LDR_x &&
140 target->GetRn() == TR &&
141 target->GetRt() == IP0 &&
142 target->GetNextInstruction() < end_address_ &&
143 target->GetNextInstruction()->Mask(UnconditionalBranchToRegisterMask) == BR &&
144 target->GetNextInstruction()->GetRn() == IP0) {
145 AppendThreadOfsetName(target);
146 }
147 }
148 }
149
AppendThreadOfsetName(const vixl::aarch64::Instruction * instr)150 void CustomDisassembler::AppendThreadOfsetName(const vixl::aarch64::Instruction* instr) {
151 int64_t offset = instr->GetImmLSUnsigned() << instr->GetSizeLS();
152 std::ostringstream tmp_stream;
153 options_->thread_offset_name_function_(tmp_stream, static_cast<uint32_t>(offset));
154 AppendToOutput(" ; %s", tmp_stream.str().c_str());
155 }
156
Dump(std::ostream & os,const uint8_t * begin)157 size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) {
158 const Instruction* instr = reinterpret_cast<const Instruction*>(begin);
159 decoder.Decode(instr);
160 os << FormatInstructionPointer(begin)
161 << StringPrintf(": %08x\t%s\n", instr->GetInstructionBits(), disasm.GetOutput());
162 return kInstructionSize;
163 }
164
Dump(std::ostream & os,const uint8_t * begin,const uint8_t * end)165 void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
166 for (const uint8_t* cur = begin; cur < end; cur += kInstructionSize) {
167 Dump(os, cur);
168 }
169 }
170
171 } // namespace arm64
172 } // namespace art
173