1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_ 18 #define ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_ 19 20 #include "disassembler.h" 21 22 // TODO(VIXL): Make VIXL compile with -Wshadow. 23 #pragma GCC diagnostic push 24 #pragma GCC diagnostic ignored "-Wshadow" 25 #include "aarch64/decoder-aarch64.h" 26 #include "aarch64/disasm-aarch64.h" 27 #pragma GCC diagnostic pop 28 29 namespace art { 30 namespace arm64 { 31 32 class CustomDisassembler final : public vixl::aarch64::Disassembler { 33 public: CustomDisassembler(DisassemblerOptions * options)34 explicit CustomDisassembler(DisassemblerOptions* options) 35 : vixl::aarch64::Disassembler(), 36 read_literals_(options->can_read_literals_), 37 base_address_(options->base_address_), 38 end_address_(options->end_address_), 39 options_(options) { 40 if (!options->absolute_addresses_) { 41 MapCodeAddress(0, 42 reinterpret_cast<const vixl::aarch64::Instruction*>(options->base_address_)); 43 } 44 } 45 46 // Use register aliases in the disassembly. 47 void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr, 48 const vixl::aarch64::CPURegister& reg) override; 49 50 // Intercepts the instruction flow captured by the parent method, 51 // to specially instrument for particular instruction types. 52 void Visit(vixl::aarch64::Metadata* metadata, const vixl::aarch64::Instruction* instr) override; 53 54 private: 55 // Improve the disassembly of literal load instructions. 56 void VisitLoadLiteralInstr(const vixl::aarch64::Instruction* instr); 57 58 // Improve the disassembly of thread offset. 59 void VisitLoadStoreUnsignedOffsetInstr(const vixl::aarch64::Instruction* instr); 60 61 // Improve the disassembly of branch to thunk jumping to pointer from thread entrypoint. 62 void VisitUnconditionalBranchInstr(const vixl::aarch64::Instruction* instr); 63 64 void AppendThreadOfsetName(const vixl::aarch64::Instruction* instr); 65 66 // Indicate if the disassembler should read data loaded from literal pools. 67 // This should only be enabled if reading the target of literal loads is safe. 68 // Here are possible outputs when the option is on or off: 69 // read_literals_ | disassembly 70 // true | 0x72681558: 1c000acb ldr s11, pc+344 (addr 0x726816b0) 71 // false | 0x72681558: 1c000acb ldr s11, pc+344 (addr 0x726816b0) (3.40282e+38) 72 const bool read_literals_; 73 74 // Valid address range: [base_address_, end_address_) 75 const void* const base_address_; 76 const void* const end_address_; 77 78 DisassemblerOptions* options_; 79 }; 80 81 class DisassemblerArm64 final : public Disassembler { 82 public: DisassemblerArm64(DisassemblerOptions * options)83 explicit DisassemblerArm64(DisassemblerOptions* options) : 84 Disassembler(options), disasm(options) { 85 decoder.AppendVisitor(&disasm); 86 } 87 88 size_t Dump(std::ostream& os, const uint8_t* begin) override; 89 void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override; 90 91 private: 92 vixl::aarch64::Decoder decoder; 93 CustomDisassembler disasm; 94 95 DISALLOW_COPY_AND_ASSIGN(DisassemblerArm64); 96 }; 97 98 } // namespace arm64 99 } // namespace art 100 101 #endif // ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_ 102