1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_TEGRA_DRM_H_ 8 #define _UAPI_TEGRA_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) 14 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) 15 struct drm_tegra_gem_create { 16 __u64 size; 17 __u32 flags; 18 __u32 handle; 19 }; 20 struct drm_tegra_gem_mmap { 21 __u32 handle; 22 __u32 pad; 23 __u64 offset; 24 }; 25 struct drm_tegra_syncpt_read { 26 __u32 id; 27 __u32 value; 28 }; 29 struct drm_tegra_syncpt_incr { 30 __u32 id; 31 __u32 pad; 32 }; 33 struct drm_tegra_syncpt_wait { 34 __u32 id; 35 __u32 thresh; 36 __u32 timeout; 37 __u32 value; 38 }; 39 #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) 40 struct drm_tegra_open_channel { 41 __u32 client; 42 __u32 pad; 43 __u64 context; 44 }; 45 struct drm_tegra_close_channel { 46 __u64 context; 47 }; 48 struct drm_tegra_get_syncpt { 49 __u64 context; 50 __u32 index; 51 __u32 id; 52 }; 53 struct drm_tegra_get_syncpt_base { 54 __u64 context; 55 __u32 syncpt; 56 __u32 id; 57 }; 58 struct drm_tegra_syncpt { 59 __u32 id; 60 __u32 incrs; 61 }; 62 struct drm_tegra_cmdbuf { 63 __u32 handle; 64 __u32 offset; 65 __u32 words; 66 __u32 pad; 67 }; 68 struct drm_tegra_reloc { 69 struct { 70 __u32 handle; 71 __u32 offset; 72 } cmdbuf; 73 struct { 74 __u32 handle; 75 __u32 offset; 76 } target; 77 __u32 shift; 78 __u32 pad; 79 }; 80 struct drm_tegra_waitchk { 81 __u32 handle; 82 __u32 offset; 83 __u32 syncpt; 84 __u32 thresh; 85 }; 86 struct drm_tegra_submit { 87 __u64 context; 88 __u32 num_syncpts; 89 __u32 num_cmdbufs; 90 __u32 num_relocs; 91 __u32 num_waitchks; 92 __u32 waitchk_mask; 93 __u32 timeout; 94 __u64 syncpts; 95 __u64 cmdbufs; 96 __u64 relocs; 97 __u64 waitchks; 98 __u32 fence; 99 __u32 reserved[5]; 100 }; 101 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 102 #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 103 #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 104 struct drm_tegra_gem_set_tiling { 105 __u32 handle; 106 __u32 mode; 107 __u32 value; 108 __u32 pad; 109 }; 110 struct drm_tegra_gem_get_tiling { 111 __u32 handle; 112 __u32 mode; 113 __u32 value; 114 __u32 pad; 115 }; 116 #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) 117 #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) 118 struct drm_tegra_gem_set_flags { 119 __u32 handle; 120 __u32 flags; 121 }; 122 struct drm_tegra_gem_get_flags { 123 __u32 handle; 124 __u32 flags; 125 }; 126 #define DRM_TEGRA_GEM_CREATE 0x00 127 #define DRM_TEGRA_GEM_MMAP 0x01 128 #define DRM_TEGRA_SYNCPT_READ 0x02 129 #define DRM_TEGRA_SYNCPT_INCR 0x03 130 #define DRM_TEGRA_SYNCPT_WAIT 0x04 131 #define DRM_TEGRA_OPEN_CHANNEL 0x05 132 #define DRM_TEGRA_CLOSE_CHANNEL 0x06 133 #define DRM_TEGRA_GET_SYNCPT 0x07 134 #define DRM_TEGRA_SUBMIT 0x08 135 #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 136 #define DRM_TEGRA_GEM_SET_TILING 0x0a 137 #define DRM_TEGRA_GEM_GET_TILING 0x0b 138 #define DRM_TEGRA_GEM_SET_FLAGS 0x0c 139 #define DRM_TEGRA_GEM_GET_FLAGS 0x0d 140 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 141 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) 142 #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) 143 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) 144 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) 145 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 146 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) 147 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) 148 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 149 #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) 150 #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) 151 #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) 152 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) 153 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) 154 #define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0) 155 struct drm_tegra_channel_open { 156 __u32 host1x_class; 157 __u32 flags; 158 __u32 context; 159 __u32 version; 160 __u32 capabilities; 161 __u32 padding; 162 }; 163 struct drm_tegra_channel_close { 164 __u32 context; 165 __u32 padding; 166 }; 167 #define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) 168 #define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) 169 #define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | DRM_TEGRA_CHANNEL_MAP_WRITE) 170 struct drm_tegra_channel_map { 171 __u32 context; 172 __u32 handle; 173 __u32 flags; 174 __u32 mapping; 175 }; 176 struct drm_tegra_channel_unmap { 177 __u32 context; 178 __u32 mapping; 179 }; 180 #define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0) 181 struct drm_tegra_submit_buf { 182 __u32 mapping; 183 __u32 flags; 184 struct { 185 __u64 target_offset; 186 __u32 gather_offset_words; 187 __u32 shift; 188 } reloc; 189 }; 190 #define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0 191 #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1 192 #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2 193 struct drm_tegra_submit_cmd_gather_uptr { 194 __u32 words; 195 __u32 reserved[3]; 196 }; 197 struct drm_tegra_submit_cmd_wait_syncpt { 198 __u32 id; 199 __u32 value; 200 __u32 reserved[2]; 201 }; 202 struct drm_tegra_submit_cmd { 203 __u32 type; 204 __u32 flags; 205 union { 206 struct drm_tegra_submit_cmd_gather_uptr gather_uptr; 207 struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt; 208 __u32 reserved[4]; 209 }; 210 }; 211 struct drm_tegra_submit_syncpt { 212 __u32 id; 213 __u32 flags; 214 __u32 increments; 215 __u32 value; 216 }; 217 struct drm_tegra_channel_submit { 218 __u32 context; 219 __u32 num_bufs; 220 __u32 num_cmds; 221 __u32 gather_data_words; 222 __u64 bufs_ptr; 223 __u64 cmds_ptr; 224 __u64 gather_data_ptr; 225 __u32 syncobj_in; 226 __u32 syncobj_out; 227 struct drm_tegra_submit_syncpt syncpt; 228 }; 229 struct drm_tegra_syncpoint_allocate { 230 __u32 id; 231 __u32 padding; 232 }; 233 struct drm_tegra_syncpoint_free { 234 __u32 id; 235 __u32 padding; 236 }; 237 struct drm_tegra_syncpoint_wait { 238 __s64 timeout_ns; 239 __u32 id; 240 __u32 threshold; 241 __u32 value; 242 __u32 padding; 243 }; 244 #define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) 245 #define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) 246 #define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) 247 #define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) 248 #define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) 249 #define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) 250 #define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) 251 #define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) 252 #ifdef __cplusplus 253 } 254 #endif 255 #endif 256